Fifo Port Descriptions - Xilinx Virtex-5 FPGA User Manual

Figure 4-19
X-Ref Target - Figure 4-19

FIFO Port Descriptions

Table 4-15
Table 4-15: FIFO I/O Port Names and Descriptions
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
shows the FIFO18 primitive.
lists the FIFO I/O port names and descriptions.
Port Name Direction
DI Input
DIP Input
WREN Input
WRCLK Input
RDEN Input
RDCLK Input
RESET Input
DO Output
DOP Output
FULL Output
ALMOSTFULL Output
EMPTY Output
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FIFO18
DI[15:0] DO[15:0]
DIP[1:0] DOP[1:0]
RDEN WRCOUNT[11:0]
RDCLK RDCOUNT[11:0]
FULL
WREN
EMPTY
WRCLK
ALMOSTFULL
RST
ALMOSTEMPTY
RDERR
WRERR
Figure 4-19: FIFO18 Primitive
Data input.
Parity-bit input.
Write enable. When WREN = 1, data will be written to
memory. When WREN = 0, write is disabled.
Clock for write domain operation.
Read enable. When RDEN = 1, data will be read to output
register. When RDEN = 0, read is disabled.
Clock for read domain operation.
Asynchronous reset of all FIFO functions, flags, and
pointers. RESET must be asserted for three clock cycles.
Data output, synchronous to RDCLK.
Parity-bit output, synchronous to RDCLK.
All entries in FIFO memory are filled. No additional writes
are accepted. Synchronous to WRCLK.
Almost all entries in FIFO memory have been filled.
Synchronous to WRCLK. The offset for this flag is user
configurable. See Table 4-16
deassertion.
FIFO is empty. No additional reads are accepted.
Synchronous to RDCLK.
FIFO Port Descriptions
ug190_4_15_040606
Description
for the clock latency for flag
143