Programmable Clock Module Switch Position Chart; Four-Pole Sw Dip2 Settings; Eight-Pole Sw Dip1 Settings - Xilinx Virtex-5 FPGA ML550 User Manual
Networking interfaces platform
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Also See for Virtex-5 FPGA ML550:
- User manual (385 pages) ,
- User manual (108 pages) ,
- User manual (89 pages)
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Chapter 2: Getting Started
Programmable Clock Module Switch Position Chart
18
Downloaded from
Elcodis.com
electronic components distributor
Select change to COM# where # is either 1, 2, 3, or 4.
10. The GUI reflects the frequency set at Clock Module 2 and initially reports 400 MHz.
More information resides in the file
C:\ML550 BERT REV1.x\DDR_8TO1_16CHAN_PICO_REV1.x\README.doc.
Also refer to the ML550 Networking Interfaces Board.ppt presentation on
the kit CD-ROM.
11. The clock frequency can be changed by clicking on the +100 MHz, +10 MHz,
–100 MHz, and –10 MHz GUI buttons to the left of the Frequency display. More
detailed information is available in the CD file BERTGUI_README.doc.
Four-Pole SW DIP2 Settings
Always
OFF
Eight-Pole SW DIP1 Settings
700 MHz
OFF
690 MHz
ON
680 MHz
OFF
670 MHz
ON
660 MHz
OFF
650 MHz
ON
600 MHz
OFF
400 MHz
OFF
Switch Position
1
2
3
OFF
OFF
OFF
Switch Position
1
2
3
ON
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
www.xilinx.com
4
4
5
6
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
ON
ON
OFF
OFF
ON
OFF
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
R
7
8
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
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