Guidelines For Expanding The Parallel-To-Serial Converter Bit Width - Xilinx Virtex-5 FPGA User Manual

Chapter 8: Advanced SelectIO Logic Resources
Figure 8-16
master and slave OSERDES modules. Ports Q3-Q6 are used for the last four bits of the
parallel interface on the slave OSERDES (LSB to MSB).
X-Ref Target - Figure 8-16
Table 8-8
Table 8-8: OSERDES SDR/DDR Data Width Availability

Guidelines for Expanding the Parallel-to-Serial Converter Bit Width

1.
2.
3.
4.
5.
The slave inputs used for data widths requiring width expansion are listed in
Table 8-9: Slave Inputs Used for Data Width Expansion
376
illustrates a block diagram of a 10:1 DDR parallel-to-serial converter using the
Data Inputs[0:5]
Data Inputs[6:9]
Figure 8-16: Block Diagram of OSERDES Width Expansion
lists the data width availability for SDR and DDR mode.
SDR Data Widths
DDR Data Widths
Both the OSERDES modules must be adjacent master and slave pairs.
Set the SERDES_MODE attribute for the master OSERDES to MASTER and the slave
OSERDES to SLAVE. See
The user must connect the SHIFTIN ports of the MASTER to the SHIFTOUT ports of
the SLAVE.
The SLAVE only uses the ports D3 to D6 as an input.
DATA_WIDTH for Master and Slave are equal. See
Data Width
7
8
10
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SERDES_MODE = MASTER
D1
D2
OSERDES
D3
D4 (Master)
D5
D6
SHIFTIN1 SHIFTIN2
SHIFTOUT1 SHIFTOUT2
D1
D2
OSERDES
D3
D4
(Slave)
D5
D6
SERDES_MODE=SLAVE
2, 3, 4, 5, 6, 7, 8
4, 6, 8, 10
"SERDES_MODE Attribute."
Slave Inputs Used
D3
D3–D4
D3–D6
Data Out
OQ
OQ
ug190_8_16_100307
"DATA_WIDTH Attribute."
Table
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
8-9.