Ilogic Timing Characteristics, Ddr - Xilinx Virtex-5 FPGA User Manual

Clock Event 4
•

ILOGIC Timing Characteristics, DDR

Figure 7-7
used, T
OPPOSITE_EDGE mode. For other modes, add the appropriate latencies as shown in
Figure 7-4, page
X-Ref Target - Figure 7-7
(Reset)
Figure 7-7: ILOGIC in IDDR Mode Timing Characteristics (OPPOSITE_EDGE Mode)
Clock Event 1
•
•
Clock Event 2
•
Clock Event 9
•
Table 7-5
in the Virtex-5 FPGA Data Sheet.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
At time T before Clock Event 4, the SR signal (configured as synchronous reset in
ISRCK
this case) becomes valid-High resetting the input register and reflected at the Q1
output of the IOB at time T
illustrates the ILOGIC in IDDR mode timing characteristics. When IDELAY is
is replaced by T
IDOCK
321.
1 2
CLK
T
T
IDOCK
IDOCK
D
T
ICE1CK
CE1
SR
T
ICKQ
Q1
Q2
At time T before Clock Event 1, the input clock enable signal becomes valid-
ICE1CK
High at the CE1 input of both of the DDR input registers, enabling them for incoming
data. Since the CE1 and D signals are common to both DDR registers, care must be
taken to toggle these signals between the rising edges and falling edges of CLK as
well as meeting the register setup-time relative to both clocks.
At time T before Clock Event 1 (rising edge of CLK), the input signal becomes
IDOCK
valid-High at the D input of both registers and is reflected on the Q1 output of input
register 1 at time T
ICKQ
At time T before Clock Event 2 (falling edge of CLK), the input signal becomes
IDOCK
valid-Low at the D input of both registers and is reflected on the Q2 output of input
register 2 at time T
ICKQ
At time T before Clock Event 9, the SR signal (configured as synchronous reset in
ISRCK
this case) becomes valid-High resetting Q1 at time T
at time T after Clock Event 10.
ICKQ
describes the function and control signals of the ILOGIC switching characteristics
www.xilinx.com
after Clock Event 4.
ICKQ
. The example shown uses IDDR in
IDOCKD
3 4 5 6
T
ICKQ
after Clock Event 1.
after Clock Event 2 (no change in this case).
ILOGIC Resources
7 8 9 10
T
ISRCK
T
ICKQ
UG190_7_07_041206
after Clock Event 9, and Q2
ICKQ
11
T
ICKQ
323