Fifo Attributes - Xilinx Virtex-5 FPGA User Manual

FIFO Attributes

Table 4-17
configured by setting the DATA_WIDTH attribute. The
Templates"
Table 4-17: FIFO18 and FIFO36 Attributes
Attribute Name
ALMOST_FULL_OFFSET
ALMOST_EMPTY_OFFSET
FIRST_WORD_FALL_THROUGH
DO_REG
DATA_WIDTH
(1, 2)
LOC
EN_SYN
Notes:
1. If FIFO18 is constrained to FIFO18_X#Y#, then RAMB18 can not be constrained to RAMB18_X#Y# since the same location would be
used.
2. If a FIFO18 is constrained to FIFO18_X#Y#, corresponding to the lower RAMB18_X#Y# of the RAMB18 pair, a RAMB18 can be
constrained to the upper RAMB18_X#Y# of the pair.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
lists the FIFO18 and FIFO36 attributes. The size of the multirate FIFO can be
section has examples for setting the attributes.
Type Values
13-bit See Table 4-19
HEX
13-bit See Table 4-19
HEX
Boolean FALSE,
TRUE
1-bit 0, 1
Binary
Integer 4, 9, 18, 36, 72
String Valid FIFO18 or
FIFO36 location
Boolean FALSE,
TRUE
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"FIFO VHDL and Verilog
Default
Setting determines the difference
between FULL and ALMOSTFULL
conditions. Must be set using
hexadecimal notation.
Setting determines the difference
between EMPTY and ALMOSTEMPTY
conditions. Must be set using
hexadecimal notation.
FALSE If TRUE, the first word written into the
empty FIFO appears at the FIFO output
without RDEN asserted.
1 For multirate (asynchronous) FIFO, must
be set to 1.
For synchronous FIFO, DO_REG must be
set to 0 for flags and data to follow a
standard synchronous FIFO operation.
When DO_REG is set to 1, effectively a
pipeline register is added to the output of
the synchronous FIFO. Data then has a
one clock cycle latency. However, the
clock-to-out timing is improved.
4
Sets the location of the FIFO18 or FIFO36.
FALSE When set to TRUE, ties WRCLK and
RDCLK together.
When set to TRUE, FWFT must be
FALSE.
When set to FALSE, DO_REG must be 1.
FIFO Attributes
Notes
147