Lvds Loopback Board (Xilinx P/N 0431395); Voltage Regulators (Ti Pth05000); Voltage Regulator ±5% Margin Adjustment (In 2.5% Increments) - Xilinx Virtex-5 FPGA ML550 User Manual

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LVDS Loopback Board (Xilinx P/N 0431395)

Voltage Regulators (TI PTH05000)

AC to DC
Converter
5V DC @6A
Voltage Regulator ±5% Margin Adjustment (in 2.5% Increments)
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
Downloaded from Elcodis.com electronic components distributor
outputs a halved frequency on pins U17.12 and U17.11, DIVCLK_P and DIVCLK_N
respectively. As previously mentioned, these output pins are connected to the FPGA.
LVDS transmit to receive loopback can be achieved with either the LVDS Loopback board
included in the kit, or with the Precision Interconnect Blue Ribbon Cables (Xilinx P/N
HW-LVDS-CBL-80, order separately).
LVDS Loopback Board details.
Figure 3-7 shows the voltage regulators used on ML550 Development Board to provide
various on-board voltage sources. As shown in
5.0V voltage to the board. This voltage source is provided to all on-board regulators to
generate the 1.0V, 2.5V, and 3.3V voltages for the digital section of the board. All Bank
V voltages are 2.5V.
CCO
System System
3.3V
VR1
3.3V
Regulator
Regulator
2.1 mm
J20
Barrel
− +
Plug
Figure 3-7: Block Diagram of the Five Voltage Regulators
Onboard digital voltages are as follows:
•
1.0V V (VR2)
CCINT
•
2.5V V (VR5)
CCAUX
•
2.5V V (VR4)
CCO
•
2.5V System (VR3)
•
3.3V System (VR1)
The regulators shown in
the FPGA, or they can be enabled or inhibited through the use of on-board jumpers. The
jumpers use the following conventions:
Appendix B, "LVDS Loopback Board"
Figure
V
CCO
2.5V
2.5V
VR3 VR4
2.5V
2.5V
Regulator
On/Off
SW8
Table 3-9 can have their outputs controlled over a ±5% range by
www.xilinx.com
Voltage Regulators (TI PTH05000)
3-7, connector J20 provides the main
V V
CCAUX CCINT
2.5V 1.0V
VR5 VR2
2.5V 1.0V
Regulator Regulator
5V
3 Amp
Fuse
F1
UG202_3_07_120706
includes
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