Qdrii Write Operation - Xilinx Virtex-5 FPGA ML561 User Manual
Memory interfaces development board
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QDRII Write Operation
This subsection shows the test results for the QDR2_D_BY0_B5 signal from FPGA3 (U34)
to QDRII memory (U35) measured at 300 MHz (600 Mb/s), where the unit interval
(UI) = 167 ns.
VCC0V7...
0.9V
R1586
49.9 ohms
28.5 ohms
4.404 ps
71.0 ohms
0.027 in
27.482 ps
U35.G11
QDR2_D_BY0_B5
AutoPadstk_3
TL2
TL4
K7R323684M_1.8V
D5
QDR2_D...
22.9 fF
Figure 7-39: Post-Layout IBIS Schematics of QDRII Write Data Bit (QDR2_D_BY0_B5)
Table 7-11: Circuit Elements of QDRII Write Data bit (QDR2_D_BY0_B5)
Table 7-12: QDRII Write Operation Correlation Results
Measurement
Hardware at probe
point
Simulation correlation
slow-weak corner
Correlation Delta:
HW vs. Simulation
Extrapolation at IOB
slow-weak corner
Extrapolation at IOB
fast-strong corner
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
49.0 ohms
5.283 ps
0.035 in
QDR2_D_BY0_B5
TL6
49.0 ohms
11.902 ps
0.079 in
QDR2_D_BY0_B5
TL5
C7
QDR2_D...
22.9 fF
500.0 fF
Element
Driver
Receiver
Probe Point
PCB Termination
Trace Length
DVW
ISI
(% UI)
(% UI)
1.40 ns
(50 + 70) = 120 ps (7.2%)
(84.1%)
1.39 ns
(136 + 91) = 227 ps (13.6%)
(83.5%)
10 ps
107 ps (6.4%)
(0.6%)
1.38 ns
(172 + 141) = 313 ps
(83%)
(18.8%)
1.49 ns
(126 + 91) = 217 ps (13.0%)
(89%)
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Signal Integrity Correlation Results
49.8 ohms
45.1 ohms
520.665 ps
7.862 ps
3.333 in
AutoPadstk_19
QDR2_D_BY0_B5
TL7
TL8
QDR2_D...
QDR2_D...
399.1 fF
58.1 fF
Designation
U34.M31
FPGA HSTL_I_18
U35.G11
QDRII memory
C7
Via under Memory
R1586
External termination at memory
TL 2, 5, 8, 1
3.46 inches
Noise Margin
(VIH + VIL) = Total
(% of VREF)
(340 + 400) = 740 mV
(82.2%)
(344 + 398) = 742 mV
(82.5%)
2 mV (0.3%)
(329 + 358) = 687 mV
(76.3%)
(353 + 376) = 729 mV
(81.0%)
28.5 ohms
70.8 ohms
4.473 ps
16.339 ps
0.028 in
AutoPadstk_3
QDR2_D_BY0_B5
TL3
TL1
QDR2_D...
QDR2_D...
22.9 fF
177.3 fF
UG199_c7_39_070907
Description
Overshoot / Undershoot
Margin
(% of VREF)
(450 + 400) = 850 mV
(94.5%)
(483 + 452) = 935 mV
(103.9%)
85 mV (9.4%)
(400 + 361) = 761 mV
(84.5%)
(156 + 30) = 186 mV
(20.7%)
U34.M31
Virtex-5 FPGA
QDR2_D_BY0_B5
81
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