Jtag Port - Xilinx Virtex-5 FPGA ML555 User Manual

Chapter 4: Configuration
connector/header P38 is used to enable or bypass the Platform Flash device U1, and
connector/header P20 is used to enable or bypass the second Platform Flash device U15.
To enable the CPLD for JTAG configuration, the shunts on P39 are connected from pin 1 to
pin 2, and a second shunt connects pin 3 to pin 4. To bypass the CPLD, a single shunt is
installed on P39, connected from pin 2 to pin 3.
To enable the Platform Flash devices for JTAG configuration, two shunts are installed on
connectors P38/P20, connecting from pin 1 to pin 2 for the first shunt, and connecting pin
3 and 4 for the second shunt. To bypass the Platform Flash devices, a single shunt on
P38/P20 is connected from pin 2 to pin 3. The default board configuration enables all four
devices in the JTAG scan chain.
JTAG
Connector
P5
FPGA
TDI
TMS
TCK

JTAG Port

The ML555 board provides a JTAG connector (P5) to configure the FPGA and program
JTAG devices located in the JTAG chain.
JTAG connector. The JTAG cable connects to P5, and the connector on the ML555 board
has a keyed, plastic shroud to ensure that the device programming cable connects
properly.
90
U10 U6
CPLD
TDO TDI TDO
TMS
TCK
Figure 4-3: JTAG Chain
www.xilinx.com
P39
4
3
2
U1
1
Platform Flash
#1
TDI TDO
TMS
TCK
Figure 4-4 shows the pin assignments for the
P5
JTAG
Connector
2.5V
1 2
3 4
5 6
7 8
9 10
11 12
13 14
2 mm
UG201_c4_04_070306
Figure 4-4: JTAG Cable Hook-up
P38
4
3
2
U15
1
Platform Flash
#2
TDI TDO
TMS
TCK
UG201_c4_03_070706
TMS
TCK
TDO
TDI
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R
P20
4
3
2
1