Dcm Design Guidelines; Clock Deskew; Clock Deskew Operation - Xilinx Virtex-5 FPGA User Manual

DCM Design Guidelines

This section provides a detailed description on using the Virtex-5 FPGA DCM and design
guidelines.

Clock Deskew

The Virtex-5 FPGA DCM offers a fully digital, dedicated, on-chip clock deskew. The
deskew feature provides zero propagation delay between the source clock and output
clock, low clock skew among output clock signals distributed throughout the device, and
advanced clock domain control.
The deskew feature also functions as a clock mirror of a board-level clock serving multiple
devices. This is achieved by driving the CLK0 output off-chip to the board (and to other
devices on the board) and then bringing the clock back in as a feedback clock. See the
"Application Examples"
simplifies and improves system-level design involving high-fanout, high-performance
clocks.

Clock Deskew Operation

The deskew feature utilizes the DLL circuit in the DCM. In its simplest form, the DLL
consists of a single variable delay line (containing individual small delay elements or
buffers) and control logic. The incoming clock drives the delay line. The output of every
delay element represents a version of the incoming clock (CLKIN) delayed at a different
point. The clock distribution network routes the clock to all internal registers and to the
clock feedback CLKFB pin. The control logic contains a phase detector and a delay-line
selector. The phase detector compares the incoming clock signal (CLKIN) against a
feedback input (CLKFB) and steers the delay-line selector, essentially adding delay to the
DCM output until the CLKIN and CLKFB coincide, putting the two clocks 360° out-of-
phase, (thus, in phase). When the edges from the input clock line up with the edges from
the feedback clock, the DCM achieves a lock. The two clocks have no discernible
difference. Thus, the DCM output clock compensates for the delay in the clock distribution
network, effectively removing the delay between the source clock and its loads. The size of
each intrinsic delay element is a DCM_TAP (see the AC Characteristics table in the Virtex-5
FPGA Data Sheet).
X-Ref Target - Figure 2-3
To provide the correct clock deskew, the DCM depends on the dedicated routing and
resources used at the clock source and feedback input. An additional delay element (see
"Deskew
Xilinx ISE tools analyze the routing around the DCM to determine if a delay must be
inserted to compensate for the clock source or feedback path. Thus, using dedicated
routing is required to achieve predictable deskew.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
section. Taking advantage of the deskew feature greatly
Figure 2-3 illustrates a simplified DLL circuit.
Variable
CLKIN
Delay Line
Control
Figure 2-3: Simplified DLL Circuit
Adjust") is available to compensate for the clock source or feedback path. The
www.xilinx.com
DCM Design Guidelines
Clock
CLKOUT
Distribution
Network
CLKFB
ug190_2_03_032506
63