Lvds Interface - Xilinx Virtex-5 FPGA ML555 User Manual

Chapter 3: Hardware Description

LVDS Interface

The ML555 board supports low voltage differential signaling (LVDS) applications with 24
transmit channels and 24 receive channels of LVDS signals. Two Samtec QSE-DP
connectors are provided, one for the transmit interface and a second for the receive
interface. Single data rate (SDR) and double data rate (DDR) LVDS applications can be
designed targeting the ML555 board. An SDR SFI-4 interface or XSBI interface consists of
16 LVDS data channels and a forwarded clock. A DDR SPI4.2 like interface consists of 16
LVDS data channels and one forwarded clock. Xilinx has several SDR and DDR LVDS
reference designs that can be ported to run on the ML555 board.
The LVDS transmit and receive connectors can be connected to each other for loopback
testing as shown in
with the kit, but can be ordered separately from Xilinx as part number HW-LVDS-CBL-80.
The LVDS transmit and receive connectors can also be connected to either an ML450 or
ML550 networking interfaces board from Xilinx. Additional information on Xilinx board
products is located at www.xilinx.com/products/devboards/index.htm.
Figure 3-5
44
Figure 3-6, page
shows the P32 and P33 LVDS connectors.
www.xilinx.com
49. The loopback interface cables are not provided
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
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