Ecc Timing Characteristics; Standard Ecc Write Timing (Figure 4-31); Standard Ecc Read Timing (Figure 4-32) - Xilinx Virtex-5 FPGA User Manual

Chapter 4: Block RAM

ECC Timing Characteristics

The various ECC timing parameters are also shown in
Since write clock and read clock are independent of each other, all write timing in
Figure 4-31
RDCLK.
Standard ECC Write Timing
•
•
•
•
Standard ECC Read Timing
•
•
DO_REG = 0
DO_REG = 1
168
is referenced to WRCLK. All read timing in
At time TRCCK_EN, before time T1W, write enable becomes valid at the WREN input
of the block RAM.
At time TRCCK_ADDR, before time T1W, write address a becomes valid at the
WRADDR[8:0] inputs of the block RAM. WRADDR input is not needed for FIFO.
At time TRDCK_DI_ECC (standard ECC), before time T1W, write data A (hex)
becomes valid at the DI[63:0] inputs of the block RAM.
At time TRCKO_ECC_PARITY (standard ECC), after time T1W, ECC parity data PA
(hex) becomes valid at the ECCPARITY[7:0] output pins of the block RAM.
At time TRCCK_EN, before time T1R, read enable becomes valid at the RDEN input
of the block RAM.
At time TRCCK_ADDR, before time T1R, write address a becomes valid at the
RDADDR[8:0] inputs of the block RAM. RDADDR input is not needed for FIFO.
♦
At time TRCKO_DO (latch mode), after time T1R, data A (hex) becomes valid at
the DO[63:0] output pins of the block RAM.
♦
At time TRCKO_DOP (latch mode), after time T1R, data PA (hex) becomes valid
at the DOP[7:0] output pins of the block RAM.
♦
At time TRCKO_ECC_SBITERR (latch mode), after time T1R, SBITERR is asserted
if single-bit error is detected and corrected on data set A.
♦
At time TRCKO_ECC_DBITERR (latch mode), after time T2R, DBITERR is
asserted if double-bit error is detected on data set B.
♦
At time TRCKO_DO (register mode), after time T2R, data A (hex) becomes valid
at the DO[63:0] output pins of the block RAM.
♦
At time TRCKO_DOP (register mode), after time T2R, data PA (hex) becomes
valid at the DOP[7:0] output pins of the block RAM.
♦
At time TRCKO_ECCR_SBITERR (register mode), after time T2R, SBITERR is
asserted if single-bit error is detected and corrected on data set A.
♦
At time TRCKO_ECCR_DBITERR (register mode), after time T3R, DBITERR is
asserted if double-bit error is detected on data set B.
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Figure 4-31
(Figure 4-31)
(Figure 4-32)
and Figure 4-32.
Figure 4-32 is referenced to
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009