Transmitter Termination; Receiver Termination - Xilinx Virtex-5 FPGA User Manual

Transmitter Termination

The Virtex-5 FPGA LVDS transmitter does not require any external termination.
lists the allowed attributes corresponding to the Virtex-5 FPGA LVDS current-mode
drivers. Virtex-5 FPGA LVDS current-mode drivers are a true current source and produce
the proper (EIA/TIA compliant) LVDS signal.

Receiver Termination

Figure 6-87
50 Ω transmission lines.
X-Ref Target - Figure 6-87
Figure 6-88
50 Ω transmission lines.
X-Ref Target - Figure 6-88
Table 6-36
Table 6-36: Allowed Attributes of the LVDS I/O Standard
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
is an example of differential termination for an LVDS receiver on a board with
External Termination
LVDS_25
Figure 6-87: LVDS_25 Receiver Termination
is an example of a differential termination for an LVDS receiver on a board with
IOB
LVDS_25
Figure 6-88: LVDS_25 With DIFF_TERM Receiver Termination
lists the available Virtex-5 FPGA LVDS I/O standards and attributes supported.
Attributes
IOSTANDARD
DIFF_TERM
www.xilinx.com
Specific Guidelines for I/O Supported Standards
IOB
Z 0
R DIFF = 2Z 0 = 100Ω
Z 0
Z = 50Ω
0
0
Z = 50Ω
0 0
Primitives
IBUFDS/IBUFGDS
LVDS_25, LVDSEXT_25
TRUE, FALSE
Table 6-36
IOB
LVDS_25
+
–
ug190_6_81_030506
IOB
LVDS_25
+
R DIFF = 100Ω
Data in
–
ug190_6_82_030506
OBUFDS/OBUFTDS
N/A
295