Sstl2_I, Sstl18_I; Sstl2_I_Dci, Sstl18_I_Dci; Sstl2_Ii, Sstl18_Ii; Diff_Sstl2_I, Diff_Sstl18_I - Xilinx Virtex-5 FPGA User Manual

SSTL2_I, SSTL18_I

Class I signaling uses V
the receiver. A series resistor (25 Ω at 2.5V, 20 Ω at 1.8V) must be connected to the
transmitter output.

SSTL2_I_DCI, SSTL18_I_DCI

The DCI transmitter provides the internal series resistance (25 Ω at 2.5V, 20 Ω at 1.8V). The
DCI receiver has an internal split thevenin termination powered from V
equivalent V

SSTL2_II, SSTL18_II

Class II signaling uses V
the receiver and transmitter respectively. A series resistor (25 Ω at 2.5V, 20 Ω at 1.8V) must
be connected to the transmitter output for a unidirectional link. For a bidirectional link,
25 Ω series resistors must connected the transmitters of the transceivers.
SSTL2_II_DCI, SSTL18_II_DCI
The DCI circuits have a split thevenin termination powered from V
series resistor (25 Ω at 2.5V, 20 Ω at 1.8V). For a unidirectional link the internal series
resistance is supplied only for the transmitter. A bidirectional link has the internal series
resistor for both transmitters.

DIFF_SSTL2_I, DIFF_SSTL18_I

Differential SSTL 2.5V and 1.8V Class I pairs complementary single-ended SSTL_I type
drivers with a differential receiver.

DIFF_SSTL2_I_DCI, DIFF_SSTL18_I_DCI

Differential SSTL 2.5V and 1.8V Class I pairs complementary single-ended SSTL_II type
drivers with a differential receiver, including on-chip differential split thevenin
termination.

DIFF_SSTL2_II, DIFF_SSTL18_II

Differential SSTL 2.5V and 1.8V Class II pairs complementary single-ended SSTL_II type
drivers with a differential receiver. For a bidirectional link, a series resistor must be
connected to both transmitters.
DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI
Differential SSTL 2.5V and 1.8V Class II pairs complementary single-ended SSTL_II type
drivers with a differential receiver, including on-chip differential termination. DCI can be
used for unidirectional and bidirectional links.
SSTL2_II_T_DCI, SSTL18_II_T_DCI
SSTL2_II_T_DCI and SSTL18_II_T_DCI provide on-chip split thevenin termination
powered from V
standards are 3-stated. When not 3-stated, these two standards do not have parallel
termination but when invoked they have an internal series resistor (25 Ω at 2.5V and
20 Ω at 1.8V.)
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
/2) as a parallel termination voltage to a 50 Ω resistor at
(V
TT CCO
voltage and termination impedance.
TT
/2) as a parallel termination voltage to a 50 Ω resistor at
(V
TT CCO
that creates an equivalent termination voltage of V
CCO
www.xilinx.com
creating an
CCO
and an internal
CCO
/2 when these
CCO
275