Phase Locked Loop (Pll) - Xilinx Virtex-5 FPGA User Manual

Chapter 3: Phase-Locked Loops (PLLs)
X-Ref Target - Figure 3-1
From any IBUFG implementation
From any BUFG implementation

Phase Locked Loop (PLL)

Virtex-5 devices contain up to six CMT tiles. The PLLs main purpose is to serve as a
frequency synthesizer for a wide range of frequencies, and to serve as a jitter filter for
either external or internal clocks in conjunction with the DCMs of the CMT.
The PLL block diagram shown in
components.
X-Ref Target - Figure 3-2
90
Figure 3-1: Block Diagram of the Virtex-5 FPGA CMT
D
Clock Pin
Figure 3-2: Block Diagram of the Virtex-5 FPGA PLL
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DCM1
clkout_pll<5:0>
PLL
DCM2
Figure 3-2 provides a general overview of the PLL
PFD CP LF
M
To any BUFG
implementation
To any BUFG
implementation
To any BUFG
implementation
UG190_c3_01_022709
VCO O0
O1
O2
O3
O4
O5
ug190_3_02_030506
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009