Iddr Vhdl And Verilog Templates; Ilogic Timing Models; Ilogic Timing Characteristics - Xilinx Virtex-5 FPGA User Manual

Chapter 7: SelectIO Logic Resources
Table 7-4: IDDR Attributes

IDDR VHDL and Verilog Templates

The Libraries Guide includes templates for instantiation of the IDDR primitive in VHDL
and Verilog.

ILOGIC Timing Models

This section describes the timing associated with the various resources within the ILOGIC
block.

ILOGIC Timing Characteristics

Figure 7-6
T
X-Ref Target - Figure 7-6
Clock Event 1
•
•
322
Attribute Name
DDR_CLK_EDGE Sets the IDDR mode of operation with
respect to clock edge
INIT_Q1 Sets the initial value for Q1 port
INIT_Q2 Sets the initial value for Q2 port
SRTYPE Set/Reset type with respect to clock (C) ASYNC (default), SYNC
illustrates ILOGIC register timing. When IDELAY is used, T
.
IDOCKD
1
CLK
T
IDOCK
D
T
ICE1CK
CE1
SR
Q1
Figure 7-6: ILOGIC Input Register Timing Characteristics
At time T before Clock Event 1, the input clock enable signal becomes valid-
ICE1CK
High at the CE1 input of the input register, enabling the input register for incoming
data.
At time T before Clock Event 1, the input signal becomes valid-High at the D
IDOCK
input of the input register and is reflected on the Q1 output of the input register at
time T after Clock Event 1.
ICKQ
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Description
2 3
T
ICKQ
Possible Values
OPPOSITE_EDGE (default),
SAME_EDGE,
SAME_EDGE_PIPELINED
0 (default), 1
0 (default), 1
is replaced by
IDOCK
4 5
T
ISRCK
T
ICKQ
ug190_7_06_041206
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009