Sstl18_Ii_T_Dci (1.8V) Split-Thevenin Termination - Xilinx Virtex-5 FPGA User Manual
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Table 6-35
Table 6-35: Differential SSTL (1.8V) Class II DC Voltage Specifications
Notes:
1. V
2. Per EIA/JESD8-6, "The value of V
3. V
4. V
5. V
SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination
Figure 6-86
SSTL18_II_T_DCI (1.8V) with on-chip split-Thevenin termination. In this bidirectional I/O
standard, when 3-stated, the termination is invoked on the receiver and not on the driver.
Because the Thevenin termination on the I/O is disabled for a driving I/O, the line is
equivalent to the SSTL18_I termination scheme. This allows the line to be driven by the
weaker SSTL class I driver. The SSTL18_II_T_DCI standard behaves like a normal
SSTL18_II I/O in a bidirectional environment but has the advantage of lower drive
strength and lower power consumption due to the optimized termination circuit.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
lists the differential SSTL (1.8V) Class II DC voltage specifications.
V
CCO
Input Parameters
V
TT
(1)
V
(DC)
IN
(3)
V
(DC)
ID
V
(AC)
ID
(4)
V
(AC)
IX
Output Parameters
(5)
V
(AC)
OX
(DC) specifies the allowable DC excursion of each differential input.
IN
the use conditions specified by the user."
(DC) specifies the input differential voltage required for switching.
ID
(AC) indicates the voltage where the differential input signals must cross.
IX
(AC) indicates the voltage where the differential output signals must cross.
OX
shows a sample circuit illustrating a valid termination technique for
www.xilinx.com
Specific Guidelines for I/O Supported Standards
Min
1.7
–
–0.30
0.25
0.50
0.675
0.725
is to be selected by the user to provide optimum noise margin in
REF
Typ
Max
1.8
1.9
× 0.5
V
–
CCO
–
V
+ 0.30
CCO
–
V
+ 0.60
CCO
–
V
+ 0.60
CCO
–
1.125
–
1.075
293
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