Nominal Pcb Specifications; Pcb Construction; Signal Return Current Management; Load Traces - Xilinx Virtex-5 FPGA User Manual

Chapter 6: SelectIO Resources

Nominal PCB Specifications

The nominal SSO table
parameters meet the following requirements.
Note:
SSO Calculator must be used to determine the SSO limit, according to the physical factors of the
unique PCB.

PCB Construction

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Signal Return Current Management

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Load Traces

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Power Distribution System Design

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306
(Table
In cases where PCB parameters do not meet all requirements listed below, the Virtex-5 FPGA
V and GND vias should have a drill diameter no less than 11 mils (279 µ).
CCO
Total board thickness must be no greater than 62 mils (1575 µ).
Traces must be referenced to a plane on an adjacent PCB layer.
The reference plane must be either GND or the V
driver.
The reference layer must remain uninterrupted for its full length from device to
device.
All IOB output buffers must drive controlled impedance traces with characteristic
impedance of 50Ω ± 10%.
Total capacitive loading at the far end of the trace (input capacitance of receiving
device) must be no more than 10 pF.
Designed according to the Virtex-5 FPGA PCB Designer's Guide.
♦
Decoupling capacitors per the device guideline
♦
Approved solder land patterns
V and GND planes cannot be separated by more than 5.0 mils (152 µ)
CCO
www.xilinx.com
6-40) contains SSO limits for cases where the PCB
CCO
associated with the output
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009