Distributed Ram Timing Characteristics - Xilinx Virtex-5 FPGA User Manual

Chapter 5: Configurable Logic Blocks (CLBs)

Distributed RAM Timing Characteristics

The timing characteristics of a 16-bit distributed RAM implemented in a Virtex-5 FPGA
slice (LUT configured as RAM) are shown in
X-Ref Target - Figure 5-28
AX/BX/CX/DX
Clock Event 1: Write Operation
During a Write operation, the contents of the memory at the address on the ADDR inputs
are changed. The data written to this memory location is reflected on the A/B/C/D
outputs synchronously.
•
•
•
This is also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time
T
Clock Event 2: Read Operation
All Read operations are asynchronous in distributed RAM. As long as WE is Low, the
address bus can be asserted at any time. The contents of the RAM on the address bus are
reflected on the A/B/C/D outputs after a delay of length T
a LUT). The address (F) is asserted after clock event 2, and the contents of the RAM at
address (F) are reflected at the output after a delay of length T
206
1
T
WC
T
WPH
T
WPL
CLK
T
AS
A/B/C/D
2
(ADDR)
T
DS
1
(DI)
T
WS
WE
T
SHCKO
DATA_OUT
A/B/C/D
Output
WRITE
Figure 5-28: Slice Distributed RAM Timing Characteristics
At time T before clock event 1, the write-enable signal (WE) becomes valid-High,
WS
enabling the RAM for a Write operation.
At time T before clock event 1, the address (2) becomes valid at the A/B/C/D
AS
inputs of the RAM.
At time T before clock event 1, the DATA becomes valid (1) at the DI input of the
DS
RAM and is reflected on the A/B/C/D output at time T
and T after clock event 1.
SHCKO WOSCO
www.xilinx.com
Figure 5-28.
2 3 4
F 3
X 0
T
ILO
1 MEM(F) 0
READ WRITE
5 6
4 5 E
1 0 X
1 0
WRITE WRITE READ
UG190_5_28_050506
after clock event 1.
SHCKO
(propagation delay through
ILO
.
ILO
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
7
T
ILO
MEM(E)