Selectmap Interface - Xilinx Virtex-5 FPGA ML555 User Manual

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Table 4-2: P5 JTAG Header Signal Descriptions and Pin Assignments
Signal Name
Notes:
1. This JTAG connectivity assumes that all four devices are in the JTAG configuration chain.
2. The JTAG_TDO connection is made to the second Platform Flash device, U15. The JTAG_TMS and

SelectMAP Interface

The SelectMAP interface is connected to the Platform Flash devices indirectly through the
CPLD. For the SelectMAP interface to operate correctly, the CPLD needs to be
programmed (via JTAG) such that the correct connections are made between the FPGA
and the Flash. The CPLD on the ML555 board has a default image programmed into the
device to permit selection of up to four static design images in the two Platform Flash
configuration devices. The source HDL code and CPLD constraint file are located on the
CD-ROM provided with the ML555 kit.
Figure 4-5
Table 4-3
respectively. The two Platform Flash devices are connected in parallel, with the exception
of the chip-enable inputs. The CPLD has one chip-enable output for each Platform Flash
device.
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Description
JTAG_TMS JTAG TMS to
FPGA/CPLD/Flash
JTAG_TCK JTAG TCK to
FPGA/CPLD/Flash
JTAG_TDO JTAG TDO from Flash
JTAG_TDI JTAG TDI to FPGA TDI
JTAG_TCK signals are connected to both U1 and U15 Platform Flash devices.
is a general schematic for the Flash/CPLD/FPGA SelectMAP Interface.
through Table 4-5
www.xilinx.com
P5 Pin FPGA Pin
Number
4
6
8
10
list the pinouts for the FPGA, CPLD, and Platform Flash,
SelectMAP Interface
CPLD Pin
Number Number
AC14 10
AB15 11
N/A N/A
AC15 N/A
Flash Pin
Number
E2
H3
(2)
E6
N/A
91