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About This Guide
This user guide is a description of the Virtex
Development Board. Complete and up-to-date documentation of the Virtex-5 family of
FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5.
Guide Contents
This manual contains the following chapters:
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Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/virtex5.
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ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
Chapter 1, "Introduction"
Chapter 2, "Getting Started"
Chapter 3, "Hardware Description"
Chapter 4, "Configuration"
Appendix A, "LVDS"
Appendix B, "LVDS Loopback Board"
Appendix C, "LCD Interface"
Appendix D, "ML550 Starter UCF"
Virtex-5 Family Overview
The features and product selection of the Virtex-5 family are outlined in this overview.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
Virtex-5 FPGA User Guide
Chapters in this guide cover the following topics:
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Clocking Resources
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Clock Management Technology (CMT)
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Phase-Locked Loops (PLLs)
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Block RAM
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Configurable Logic Blocks (CLBs)
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SelectIO™ Resources
www.xilinx.com
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-5 FPGA ML550 Networking Interfaces
Preface
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