General Slice Timing Model And Parameters - Xilinx Virtex-5 FPGA User Manual

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General Slice Timing Model and Parameters

A simplified Virtex-5 FPGA slice is shown in

omitted for clarity. Only the elements relevant to the timing paths described in this section

X-Ref Target - Figure 5-25

Virtex-5 FPGA User Guide

UG190 (v5.0) June 19, 2009

Figure 5-25: Simplified Virtex-5 FPGA Slice

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CLB / Slice Timing Models

5-25. Some elements of the slice are

UG190_5_25_050506