General Slice Timing Model And Parameters - Xilinx Virtex-5 FPGA User Manual

General Slice Timing Model and Parameters

A simplified Virtex-5 FPGA slice is shown in
omitted for clarity. Only the elements relevant to the timing paths described in this section
are shown.
X-Ref Target - Figure 5-25
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
LUT
D
6
O6
Inputs
O5
DX
LUT
C
6
O6
Inputs
O5
CX
LUT
B
6
O6
Inputs
O5
BX
LUT
A
6
O6
Inputs
O5
AX
CE
CLK
SR
REV
(DX)
Figure 5-25: Simplified Virtex-5 FPGA Slice
www.xilinx.com
Figure
F7BMUX
F8MUX
F7AMUX
CLB / Slice Timing Models
5-25. Some elements of the slice are
FE/LAT
D Q
CE
CLK
SR REV
FE/LAT
D Q
CE
CLK
SR REV
FE/LAT
D Q
CE
CLK
SR REV
FE/LAT
D Q
CE
CLK
SR REV
D
DMUX
DQ
C
CMUX
CQ
B
BMUX
BQ
A
AMUX
AQ
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