Input Ddr Primitive (Iddr) - Xilinx Virtex-5 FPGA User Manual

X-Ref Target - Figure 7-4
C
CE
D0A D1A D2A
D
Q1
Q2
Figure 7-4: Input DDR Timing in SAME_EDGE_PIPELINED Mode

Input DDR Primitive (IDDR)

Figure 7-5
signals.
primitive.
X-Ref Target - Figure 7-5
Table 7-3: IDDR Port Signals
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A
D0A
D1A
shows the block diagram of the IDDR primitive.
Table 7-4 describes the various attributes available and default values for the IDDR
Figure 7-5: IDDR Primitive Block Diagram
Port
Function
Name
Q1 and Q2 Data outputs
C Clock input port
CE Clock enable port
D Data input (DDR) IDDR register input from IOB.
R Reset
S Set
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D2A D4A
D3A D5A
S
D
IDDR
CE
C
R
ug190_7_05_062207
IDDR register outputs.
The C pin represents the clock input pin.
The enable pin affects the loading of data into the DDR
flip-flop. When Low, clock transitions are ignored and new
data is not loaded into the DDR flip-flop. CE must be High
to load new data into the DDR flip-flop.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted High.
ILOGIC Resources
D6A D8A
D7A D9A
ug190_7_04_041206
Table 7-3 lists the IDDR port
Q1
Q2
Description
D10A
D11A
321