Timing Characteristics Of 2:1 Sdr Serialization - Xilinx Virtex-5 FPGA User Manual

Chapter 8: Advanced SelectIO Logic Resources
Table 8-11: OSERDES Switching Characteristics (Continued)

Timing Characteristics of 2:1 SDR Serialization

In
X-Ref Target - Figure 8-17
Clock Event 1
On the rising edge of CLKDIV, the word AB is driven from the FPGA logic to the D1 and
D2 inputs of the OSERDES (after some propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word AB is sampled into the OSERDES from the D1 and
D2 inputs.
Clock Event 3
The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDES. This
latency is consistent with the
CLK cycle.
378
Symbol
Combinatorial
T
OSCO_OQ
T
OSCO_TQ
Figure 8-17, the timing of a 2:1 SDR data serialization is illustrated.
Clock Clock
Event 1 Event 2
CLKDIV
CLK
D1
D2
OQ
Figure 8-17: OSERDES Data Flow and Latency in 2:1 SDR Mode
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Description
Asynchronous Reset to OQ
Asynchronous Reset to TQ
Clock
Event 3
A C E
B D F
A B C
Table 8-10 listing of a 2:1 SDR mode OSERDES latency of one
D E F
UG190_8_17_100307
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009