Clb Primitives; Distributed Ram Primitives - Xilinx Virtex-5 FPGA User Manual

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CLB Primitives

More information on the CLB primitives are available in the software libraries guide.

Distributed RAM Primitives

Seven primitives are available; from 32 x 2 bits to 256 x 1 bit. Three primitives are single-
port RAM, two primitives are dual-port RAM, and two primitives are quad-port RAM, as
shown in
Table 5-11: Single-Port, Dual-Port, and Quad-Port Distributed RAM
Primitive
RAM32X1S
RAM32X1D
RAM32M
RAM64X1S
RAM64X1D
RAM64M
RAM128X1S
RAM128X1D
RAM256X1S
The input and output data are 1-bit wide (with the exception of the 32-bit RAM).
Figure 5-32
primitives. The A, ADDR, and DPRA signals are address buses.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
At time T before clock event 1, data from CIN input becomes valid-High at the
CINCK
D input of the slice register. This is reflected on any of the AQ/BQ/CQ/DQ pins at
time T after clock event 1.
CKO
At time T before clock event 3, the SR signal (configured as synchronous reset)
SRCK
becomes valid-High, resetting the slice register. This is reflected on any of the
AQ/BQ/CQ/DQ pins at time T
Table 5-11.
RAM Size
32-bit
32-bit
32-bit
64-bit
64-bit
64-bit
128-bit
128-bit
256-bit
shows generic single-port, dual-port, and quad-port distributed RAM
www.xilinx.com
after clock event 3.
CKO
Type
Single-port
Dual-port
Quad-port
Single-port
Dual-port
Quad-port
Single-port
Dual-port
Single-port
CLB Primitives
Address Inputs
A[4:0] (read/write)
A[4:0] (read/write)
DPRA[4:0] (read)
ADDRA[4:0] (read)
ADDRB[4:0] (read)
ADDRC[4:0] (read)
ADDRD[4:0] (read/write)
A[5:0] (read/write)
A[5:0] (read/write)
DPRA[5:0] (read)
ADDRA[5:0] (read)
ADDRB[5:0] (read)
ADDRC[5:0] (read)
ADDRD[5:0] (read/write)
A[6:0] (read/write)
A[6:0], (read/write)
DPRA[6:0] (read)
A[7:0] (read/write)
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