Qdrii And Rldram Ii Memories - Xilinx Virtex-5 FPGA ML561 User Manual

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QDRII and RLDRAM II Memories

Figure 3-5
signals among the different banks of the FPGA #3 device.
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
summarizes the distribution of QDRII and RLDRAM II component interface
BANK 124
BANK 120
BANK 116
BANK 112
BANK 114
BANK 118
BANK 122
BANK 126
Figure 3-5: FPGA #3 Banks for QDRII SRAM and RLDRAM II Interfaces (Top View)
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BANK 5 (20)
BANK 20 (40) BANK 3 (20)
RLDII Data General I/O
DQ 0, 1 & D0
BANK 1 (20)
System ACE Controls
BANK 12 (40)
RLDII Data
(Configuration)
DQ 2, 3 & D1
BANK 0
BANK 18 (40) BANK 2 (20)
RLDII Data
Inter-FPGA MII Links
D 2, 3
BANK 22 (40) BANK 4 (20)
RLDII Address
Global Clock Inputs
and Control
BANK 6 (20)
Memory Details
BANK 23 (40)
BANK 19 (40)
QDRII Data
Q1, 3 & D1
BANK 15 (40)
QDRII Data
D7, 2, 3, 0
BANK 11 (40)
QDRII Data
Q0, 2 & D6
BANK 13 (40)
QDRII Data
Q4, 5, 6
BANK 17 (40)
QDRII Data
Q7 & D4, 5
BANK 21 (40)
QDRII Address
and Control
BANK 25 (40)
UG199_c3_05_050106
25