Conflict Avoidance; Asynchronous Clocking; Synchronous Clocking - Xilinx Virtex-5 FPGA User Manual

X-Ref Target - Figure 4-4

Conflict Avoidance

Virtex-5 FPGA block RAM memory is a true dual-port RAM where both ports can access
any memory location at any time. When accessing the same memory location from both
ports, the user must, however, observe certain restrictions. There are two fundamentally
different situations: The two ports either have a common clock (synchronous clocking), or
the clock frequency and phase is different for the two ports (asynchronous clocking).

Asynchronous Clocking

Asynchronous clocking is the more general case, where the active edges of both clocks do
not occur simultaneously:
•
•

Synchronous Clocking

Synchronous clocking is the special case, where the active edges of both port clocks occur
simultaneously:
•
•
•
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
CLK
WE
DI
XXXX
ADDR
aa
DO
0000
EN
Disable Read
Figure 4-4: NO_CHANGE Mode Waveforms
There are no timing constraints when both ports perform a read operation.
When one port performs a write operation, the other port must not read- or write-
access the same memory location. The simulation model will produce an error if this
condition is violated. If this restriction is ignored, a read or write operation will
produce unpredictable results. There is, however, no risk of physical damage to the
device. If a read and write operation is performed, then the write will store valid data
at the write location.
There are no timing constraints when both ports perform a read operation.
When one port performs a write operation, the other port must not write into the
same location, unless both ports write identical data.
When one port performs a write operation, the write operation succeeds; the other
port can reliably read data from the same location if the write port is in READ_FIRST
mode. DATA_OUT on both ports will then reflect the previously stored data.
If the write port is in either WRITE_FIRST or in NO_CHANGE mode, then the DATA-
OUT on the read port would become invalid (unreliable). The mode setting of the
read-port does not affect this operation.
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Synchronous Dual-Port and Single-Port RAMs
1111 2222
bb cc
MEM(aa)
Write
MEM(bb)=1111 MEM(cc)=2222
XXXX
dd
MEM(dd)
Write Read
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