Sdram Memory - Xilinx Virtex-5 FPGA ML550 User Manual

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SDRAM Memory

The ML550 Development Board provides 64 MBytes of SDRAM memory (Micron
Semiconductor MT46V64M8BN-75). The high-level block diagram of the SDRAM interface
is shown in
FFG1136 package used on the ML550 Development Board.
Table 3-2: SDRAM Memory Interface Signal Descriptions
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
Figure 3-2. Table 3-2
Virtex-5
FPGA
Figure 3-2: Block Diagram of the SDRAM Interface
Signal Name
A0 Address 0
A1 Address 1
A2 Address 2
A3 Address 3
A4 Address 4
A5 Address 5
A6 Address 6
A7 Address 7
A8 Address 8
A9 Address 9
A10 Address 10
A11 Address 11
A12 Address12
DQ0 Data 0
DQ1 Data 1
www.xilinx.com
lists the SDRAM memory interface signals for the
DQ[7:0], DQS0
Address[12:0]
BA[1:0]
DM0
CSn
RASn
CASn
WEn
CKE
CLKP, CLKN
Description
SDRAM Memory
32M x 16
SDRAM
ug202_3_02_032607
FPGA Pin Number
(FFG1136 Package, Bank 12)
J5
J6
T6
R6
K6
K7
P6
P7
L4
P5
N5
L6
M7
T10
F6
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