Missing Input Clock Or Feedback Clock; Pll Use Models; Clock Network Deskew - Xilinx Virtex-5 FPGA User Manual

Missing Input Clock or Feedback Clock

When the input clock or feedback clock is lost, the PLL will drive the output clocks to a
lower or higher frequency, causing all of the output clocks to increase/decrease in
frequency. The frequency increase/decrease can cause the clock output frequencies to
change to as much as six times the original configuration.

PLL Use Models

There are several methods to design with the PLL. The PLL wizard in ISE software can
assist with generating the various PLL parameters. Additionally, the PLL can be manually
instantiated as a component. It is also possible for the PLL to be merge with an IP core. The
IP core would contain and manage the PLL.

Clock Network Deskew

One of the predominant uses of the PLL is for clock network deskew.
PLL in this mode. The clock output from one of the O counters is used to drive logic within
the fabric and/or the I/Os. The feedback counter is used to control the exact phase
relationship between the input clock and the output clock (if, for example a 90° phase shift
is required). The associated clock waveforms are shown to the right for the case where the
input clock and output clock need to be phase aligned. This configuration is the most
flexible, but it does require two global clock networks
X-Ref Target - Figure 3-10
There are certain restrictions on implementing the feedback. The CLKFBOUT output can
be used to provide the feedback clock signal. The fundamental restriction is that both input
frequencies to the PFD must be identical. Therefore, the following relationship must be
met:
As an example, if ƒ
frequency are both 498 MHz. Since the M value in the feedback path is 3, both input
frequencies at the PFD are 166 MHz.
In another more complex scenario has an input frequency of 66.66 MHz and D = 2, M = 15,
and O = 2. The VCO frequency in this case is 500 MHz and the O output frequency is
250 MHz. Therefore, the feedback frequency at the PFD is 500/15 or 33.33 MHz, matching
the 66.66MHz/2 input clock frequency at the PFD.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
IBUFG
1 2
CLKIN1 CLKOUT0
3
CLKFBIN CLKOUT1
RST CLKOUT2
CLKOUT3
CLKOUT4
PLL
CLKOUT5
CLKFBOUT
Figure 3-10: Clock Deskew Using Two BUFGs
is 166 MHz, D = 1, M = 3, and O = 1, then VCO and the clock output
IN
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BUFG
4 5
To Logic
BUFG
6
f f
IN VCO
------ - = f = ------------ -
FB
D M
PLL Use Models
Figure 3-10
(Figure 3-10).
1
2
3
4
5
6
UG190_3_10_040809
Equation 3-8
shows the
105