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3.5.5 Look-Up Table
The Look-Up Table contains three 16x4-bit wide palettes. In gray shade modes, the "green" palette can be configured for
the re-mapping of 16 possible shades of gray. In color modes, all three palettes can be configured for the re-mapping of
4096 possible colors.
3.5.6 Port Decoder
According to configuration settings VD1, VD12 - VD4, IOCS# and address lines AB9-1, the Port Decoder validates a given
I/O cycle.
3.5.7 Memory Decoder
According to configuration settings VD15 - VD13, MEMCS# and address lines AB19-17, the Memory Decoder validates
a given memory cycle.
3.5.8 Data Bus Conversion
According to configuration setting VD0, Data Bus Conversion maps the external data bus, either 8-bit or 16-bit, into the
internal odd and even data bus.
3.5.9 Address Generator
The Address Generator generates display refresh addresses to be used to access display memory.
3.5.10 MPU / CRT Selector
The MPU / CRT Selector grants access to the display memory from either the MPU or the display refresh circuitry.
3.5.11 Display Data Formatter
The Display Data Formatter reads in the display data from the display memory and outputs the correct format for all
supported gray shade and color selections.
3.5.12 Clock Inputs / Timing
Clock Inputs / Timing generates the internal master clock according to gray-level / color selected and display memory
interface. The master clock (MCLK) can be:
- MCLK = input clock
- MCLK = 1/2 input clock
- MCLK = 1/4 input clock.
Pixel clock = input clock = f
3.5.13 SRAM Interface
The SRAM Interface generates the necessary signals to interface to the Display Memory (SRAM).
S1D13503
X18A-A-001-08
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Hardware Functional Specification
Issue Date: 01/01/29
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