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Memory Tab
Memory Clock
Access Time
Memory Type
WE# Control
Memory
Performance
S1D13504
X19A-B-008-03
The Memory tab contains settings that control the configuration of the DRAM used for the
S1D13504 display buffer.
Note
The memory type and access time determines the optimal memory clock.
Memory Configuration
Memory Clock
Access Time
These settings must be configured based on the specifi-
cation of the DRAM being used. For each of the
following settings refer to the DRAM manufacturer's
specification unless otherwise noted.
The current Memory Clock (MCLK) frequency is
displayed here.
Selects the access time of the DRAM.
The S1D13504 evaluation boards use 50ns DRAM.
13504DCFG Driver Configuration Program
Epson Research and Development
Vancouver Design Center
Refresh Time
1 MCLK R/W Delay
Suspend Mode
Installed Memory
Issue Date: 01/10/26
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