Functional Block Diagram; Functional Block Descriptions; Host Interface; Memory Controller - Epson S1D13704 Technical Manual

Embedded memory color lcd controller
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Epson Research and Development
Vancouver Design Center

4 Functional Block Diagram

Register
Generic MPU
MC68K
Host
SH-3
SH-4
Bus Clock

4.1 Functional Block Descriptions

4.1.1 Host Interface

4.1.2 Memory Controller

4.1.3 Sequence Controller

Hardware Functional Specification
Issue Date: 01/02/08
20k x 16-bit SRAM
Memory
Controller
I/F
Memory Clock

Figure 4-1: System Block Diagram Showing Data Paths

The Host Interface provides the means for the CPU/MPU to communicate with the display
memory and internal registers.
The Memory Controller arbitrates between CPU accesses and display refresh accesses. It
also generates the necessary signals to control the SRAM frame buffer.
The Sequence Controller controls data flow from the Memory Controller through the Look-
Up Table and to the LCD Interface. It also generates memory addresses for display refresh
accesses.
Power Save
Clocks
Look-Up
Table
Sequence Controller
Pixel Clock
*
Page 15
LCD
LCD
I/F
S1D13704
X26A-A-001-04

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