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3.1 Internal Block Diagram
IOR#, IOW#,
IOCS#, MEMCS#,
MEMR#, MEMW#,
Bus Signal
BHE#, AB[19:0]
Translation
READY
DB[15:0]
3.2 Functional Block Descriptions
Bus Signal Translation
According to configuration setting VD2, the Bus Signal Translation block translates either
MC68000 type MPU signals or MPU controlled by a READY type signals to internal bus interface
signals.
Control Registers
The register block contains the 16 internal control and configuration registers. These registers can be
accessed by either direct-mapping or using the built-in internal index register.
Sequence Controller
The Sequence Controller block generates horizontal and vertical display timings according to the
configuration registers settings.
LCD Panel Interface
The LCD Interface block performs frame rate modulation and output data pattern formatting for
both passive monochrome and passive color LCD panels.
Look-Up Table
The Look-Up Table block contains three 16 × 4-bit wide palettes. In gray shade modes, the "green"
palette can be configured for the re-mapping of 16 possible shades of gray. In color modes, all three
palettes can be configured for the re-mapping of 4096 possible colors. See Section 8.2, Look-Up
Table Architecture for details.
Port Decoder
According to configuration settings VD1, VD12–VD4, IOCS# and address lines AB9–1, the Port
Decoder validates a given I/O cycle.
Memory Decoder
According to configuration settings VD15–VD13, MEMCS# and address lines AB19–17, the Mem-
ory Decoder validates a given memory cycle.
S18A-A-011-01
S1D13503 Series Hardware Functional Specification
Control Registers
Port
Decoder
Memory
Decoder
Data Bus
Address
Conversion
Generator
Timing Generator
Power Save
Oscillator
OSC1
OSC2
VWE# VOE#
Figure 3-6 Internal Block Diagram
Sequence
Controller
Look-Up
Table
MPU/CRT
Display Data
Selector
Formatter
SRAM Interface
VA[15:0],
VD[15:0]
VSC0#, VSC1#
LCDENB
UD[3:0],
LCD
LD[3:0],
Panel
LP, YD,
Interface
XSCL,
WF (XSCL2)
1-7
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