Storage Synchronization (Sync, Lwsync, Lwarx, Stwcx, And Eieio) - IBM Power7 Optimization And Tuning Manual

APIs
There are three ways to set the SMT priority when it is running on POWER processors:
1. Modify the SMT priority directly using the PPR register.
2. Modify the SMT priority through the usage of special no-ops.
3. Using the AIX thread_set_smt_priority system call.
On POWER7 and earlier, code that is running in problem-state can only set the SMT priority
level to Low, Medium-Low, or Medium. On POWER7+, code that is running in problem-state
can additionally set the SMT priority to Very-Low.
For more information about this topic, see 2.4, "Related publications" on page 51.

2.3.4 Storage synchronization (sync, lwsync, lwarx, stwcx, and eieio)

The Power Architecture storage model provides for out-of-order storage accesses, providing
opportunities for performance enhancement when accesses do not need to be in order.
However, when accessing storage shared by multiple processor cores or shared with I/O
devices, it is important that accesses occur in the correct order that is required for the sharing
mechanisms that is used.
The architecture provides mechanisms for synchronization of such storage accesses and
defines an architectural model that ought to be adhered to by software. Several
synchronization instructions are provided by the architecture, such as sync, lwsync, lwarx,
stcwx, and eieio. There are also operating system-specific locking services provided that
enforce such synchronization. Software must be carefully designed when you use these
mechanisms to ensure optimal performance while providing appropriate data consistency
because of their inherent heavyweight nature.
Concepts and benefits
The Power Architecture defines a storage model that provides weak ordering of storage
accesses. The order in which memory accesses are performed might differ from the program
order and the order in which the instructions that cause the accesses are run.
The Power Architecture provides a set of instructions that enforce storage access
synchronization, and the AIX kernel provides a set of kernel services that provide locking
mechanisms and associated synchronization support.
with an inherent cost because of the nature of synchronization. Thus, it is important to
intelligently use the correct storage mechanisms for the various types of storage access
scenarios to ensure that accesses are performed in program order while minimizing
their impact.
30
Power ISA Version 2.06 Revision B, available at:
http://power.org/wp-content/uploads/2012/07/PowerISA_V2.06B_V2_PUBLIC.pdf
31
thread_set_smt_priority system call, available at:
http://publib.boulder.ibm.com/infocenter/aix/v7r1/index.jsp?topic=/com.ibm.aix.kerneltechref/doc/kte
chrf1/thread_set_smt_priority.htm
32
Power ISA Version 2.06 Revision B, available at:
http://power.org/wp-content/uploads/2012/07/PowerISA_V2.06B_V2_PUBLIC.pdf
33
Ibid
34
thread_set_smt_priority or thread_read_smt_priority System Call, available at:
http://publib.boulder.ibm.com/infocenter/aix/v7r1/index.jsp?topic=/com.ibm.aix.kerneltechref/doc/ktech
rf1/thread_set_smt_priority.htm
35
PowerPC storage model and AIX programming: What AIX programmers need to know about how their software
accesses shared storage, by Lyons, et al, available at:
http://www.ibm.com/developerworks/systems/articles/powerpc.html
36
Ibid
32
33
34
35
36
However, such mechanisms come
Chapter 2. The POWER7 processor
30, 31
37