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Table 1.4 Measurement Items (cont)
Classification
Type
Operand bus
Access
performance
count (cont)
(cont)
Access
miss count
Measurement Item
Number of internal-
RAM access for
operand fetch
(READ) (XY-RAM or
L memory (O-L
memory))
Number of internal-
RAM access for
operand fetch
(WRITE) (XY-RAM
or L memory (O-L
memory))
Number of I-L
memory access for
operand fetch
(READ/WRITE)
Number of U-RAM
access (READ)
Number of U-RAM
access (WRITE)
Number of operand
cache miss (READ)
Option
Note
XLR
The number of accesses to XY
memory in the MPU during
memory access (read) of an
operand.
(Accesses via the XY bus and
the operand bus are included.
When MOVX and MOVY are
executed simultaneously, it
increments one count
regardless of the read or write.)
XLW
The number of accesses to XY
memory in the MPU during
memory access (write) of an
operand.
(Accesses via the XY bus and
the operand bus are included.
When MOVX and MOVY are
executed simultaneously, it
increments one count
regardless of the read or write.)
ILRW
The number of accesses to I-L
memory in the MPU during
memory access (read/write) of
an operand.
UR
The number of U-memory
accesses during memory
access (read) of an operand.
(Accesses via the cache are
not included.)
UW
The number of U-memory
accesses during memory
access (write) of an operand.
(Accesses via the cache are
not included.)
CMR
The number of cache misses
by an operand cache access
(read) (number of accesses to
the outside of the CPU core
due to a cache miss).
Cache misses are not counted
by the PREF instruction.
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