Renesas SH-4A User Manual page 68

Table 1.4 Measurement Items (cont)
Classification Type
Instruction bus Instruction
performance (cont)
(cont)
Operand bus Access
performance count
44
Measurement Item
Number of
instruction cache
miss
Number of internal-
RAM access for
instruction fetch (XY-
RAM or L memory
(O-L memory))
Number of I-L
memory access for
instruction fetch
Number of U
memory access for
instruction fetch
Number of memory
access for operand
fetch (READ)
Number of memory
access for operand
fetch (WRITE)
Number of operand
cache access
(READ)
Number of operand
cache access
(WRITE)
Option Note
ICM The number of cache misses
by an instruction cache access
(the number of accesses to the
outside of the CPU core due to
a cache miss).
XL The number of accesses for
the XY memory in the MPU
during memory accesses of the
opcode.
ILIF The number of accesses for
the I-L memory in the MPU
during memory accesses of the
opcode.
ULF The number of accesses for
the U memory in the MPU
during memory accesses of the
opcode.
MR The number of memory
accesses by an operand read
(equal to loading on the
operand bus).
Accesses by the PREF
instruction or canceled
accesses are not included.
MW The number of memory
accesses by an operand write
(equal to storing memory on
the operand bus).
Canceled accesses are not
included.
CR The number of operand-cache
reads during memory access
(read) of an operand.
CW The number of operand-cache
reads during memory access
(write) of an operand.