Page 1 REJ09B0158-0100 SH7780 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC Engine Family SH7780 Series R8A77800A Rev.1.00 Revision Date: Dec. 13, 2005...
Page 2 Rev.1.00 Dec. 13, 2005 Page ii of l...
Page 3 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 4: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Modules The configuration of the functional description of each module differs according to the module.
Page 6: Preface
Preface This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems.
Page 7 Abbreviations Arithmetic Logic Unit ASID Address Space Identifier Ball Grid Array Compare Match Timer (Timer/Counter) Clock Pulse Generator Central Processing Unit Double Data Rate DDRIF DDR-SDRAM Interface Direct Memory Access DMAC Direct Memory Access Controller FIFO First-In First-Out FLCTL NAND Flash Memory Controller Floating-point Unit Audio Codec HSPI...
Page 8 MMCIF Multimedia Card Interface Memory Management Unit Most Significant Bit Program Counter Peripheral Component Interconnect PCIC PCI (local bus) Controller RISC Reduced Instruction Set Computer Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO Serial Sound Interface Test Access Port Translation Lookaside Buffer Timer Unit...
Page 9: Table Of Contents
Contents Section 1 Overview....................1 SH7780 Features........................1 Block Diagram ........................9 Pin Arrangement ........................10 Pin Functions ........................11 Memory Address Map ......................27 SuperHyway Bus ......................... 30 SuperHyway Memory (SuperHyway RAM)................ 31 Section 2 Programming Model ................33 Data Formats........................33 Register Descriptions ......................
Page 10 Register Descriptions......................97 5.2.1 TRAPA Exception Register (TRA) ................ 98 5.2.2 Exception Event Register (EXPEVT)..............99 5.2.3 Interrupt Event Register (INTEVT)..............100 Exception Handling Functions................... 101 5.3.1 Exception Handling Flow ..................101 5.3.2 Exception Handling Vector Addresses ..............101 Exception Types and Priorities ..................102 Exception Flow ........................
Page 11 Section 7 Memory Management Unit (MMU) ..........147 Overview of MMU ......................147 7.1.1 Address Spaces ..................... 149 Register Descriptions ......................156 7.2.1 Page Table Entry High Register (PTEH) .............. 157 7.2.2 Page Table Entry Low Register (PTEL) ............... 158 7.2.3 Translation Table Base Register (TTB) ..............
Page 12 7.7.5 Memory-Mapped PMB Configuration..............192 7.7.6 Notes on Using 32-Bit Address Extended Mode ..........194 Section 8 Caches....................197 Features..........................197 Register Descriptions......................200 8.2.1 Cache Control Register (CCR) ................201 8.2.2 Queue Address Control Register 0 (QACR0)............203 8.2.3 Queue Address Control Register 1 (QACR1)............
Page 13 9.2.1 On-Chip Memory Control Register (RAMCR) ............ 229 9.2.2 L Memory Transfer Source Address Register 0 (LSA0) ........230 9.2.3 L Memory Transfer Source Address Register 1 (LSA1) ........232 9.2.4 L Memory Transfer Destination Address Register 0 (LDA0) ......234 9.2.5 L Memory Transfer Destination Address Register 1 (LDA1) ......
Page 14 10.4.3 IRL Interrupts ....................... 297 10.4.4 On-chip Module Interrupts ................... 299 10.4.5 Interrupt Priority Levels of On-chip Module Interrupts ........300 10.4.6 Interrupt Exception Handling and Priority............301 10.5 Operation ........................... 308 10.5.1 Interrupt Sequence ....................308 10.5.2 Multiple Interrupts ....................310 10.5.3 Interrupt Masking by MAI Bit................
Page 15 Section 12 DDR-SDRAM Interface (DDRIF)...........401 12.1 Features..........................401 12.2 Input/Output Pins ....................... 403 12.3 Address Space, Bus Width, and Data Alignment............... 404 12.3.1 Address Space of the DDRIF................404 12.3.2 Memory Data Bus Width ..................405 12.3.3 Data Alignment..................... 406 12.4 Register Descriptions ......................
Page 16 13.4.4 Target Access......................532 13.4.5 Host Bus Bridge Mode ..................541 13.4.6 Normal mode ......................544 13.4.7 Power Management ....................544 13.4.8 PCI Local Bus Basic Interface................545 Section 14 Direct Memory Access Controller (DMAC)........557 14.1 Features..........................557 14.2 Input/Output Pins....................... 559 14.3 Register Descriptions......................
Page 17 Section 15 Clock Pulse Generator (CPG)............613 15.1 Features..........................613 15.2 Input/Output Pins ....................... 616 15.3 Clock Operating Modes ..................... 617 15.4 Register Descriptions ......................618 15.4.1 Frequency Control Register (FRQCR) ..............619 15.4.2 PLL Control Register (PLLCR)................621 15.5 Notes on Board Design ...................... 622 Section 16 Watchdog Timer and Reset..............625 16.1 Features..........................
Page 18 17.5 Module Standby State ......................649 17.5.1 Transition to Module Standby Mode ..............649 17.5.2 Cancellation of Module Standby Mode and Resume..........649 17.6 DDR-SDRAM Power Supply Backup................650 17.6.1 Self-Refresh and Initialization ................650 17.6.2 DDR-SDRAM Backup Sequence when Turning Off System Power Supply ..651 17.7 RTC Power Supply Backup ....................
Page 19 19.3.3 Control Register (CMTCTL) ................684 19.3.4 Interrupt Status Register (CMTIRQS) ..............688 19.3.5 Channels 0 to 3 Time Registers (CMTCH0T to CMTCH3T)....... 689 19.3.6 Channels 0 to 1 Stop Time Registers (CMTCH0ST to CMTCH1ST)....689 19.3.7 Channels 0 to 3 Counters (CMTCH0C to CMTCH3C)........690 19.4 Operation ...........................
Page 20 20.4 Operation ........................... 727 20.4.1 Time Setting Procedures..................727 20.4.2 Time Reading Procedures..................728 20.4.3 Alarm Function..................... 729 20.5 Interrupts..........................730 20.6 Usage Notes ........................730 20.6.1 Register Initialization.................... 730 20.6.2 Crystal Oscillator Circuit ..................730 20.6.3 Interrupt source and request generating order............732 Section 21 Serial Communication Interface with FIFO (SCIF)......
Page 21 22.3.2 Clock Select Register (SISCR) ................804 22.3.3 Control Register (SICTR) ..................806 22.3.4 Transmit Data Register (SITDR) ................809 22.3.5 Receive Data Register (SIRDR) ................810 22.3.6 Transmit Control Data Register (SITCR) ............. 811 22.3.7 Receive Control Data Register (SIRCR) .............. 812 22.3.8 Status Register (SISTR)..................
Page 22 Section 24 Multimedia Card Interface (MMCIF) ..........865 24.1 Features..........................865 24.2 Input/Output Pins....................... 866 24.3 Register Descriptions......................867 24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)..........871 24.3.2 Command Start Register (CMDSTRT) ..............872 24.3.3 Operation Control Register (OPCR)..............873 24.3.4 Card Status Register (CSTR)................
Page 23 25.3.7 TX Status Register (HACTSR)................967 25.3.8 RX Interrupt Enable Register (HACRIER)............969 25.3.9 RX Status Register (HACRSR) ................970 25.3.10 HAC Control Register (HACACR) ..............971 25.4 AC 97 Frame Slot Structure....................973 25.5 Operation ........................... 974 25.5.1 Receiver ........................ 974 25.5.2 Transmitter......................
Page 24 27.3.4 Address Register (FLADR) ................1030 27.3.5 Data Counter Register (FLDTCNTR) ..............1032 27.3.6 Data Register (FLDATAR) ................1033 27.3.7 Interrupt DMA Control Register (FLINTDMACR) ........... 1034 27.3.8 Ready Busy Timeout Setting Register (FLBSYTMR) ........1039 27.3.9 Ready Busy Timeout Counter (FLBSYCNT)............. 1040 27.3.10 Data FIFO Register (FLDTFIFO)...............
Page 25 28.2.19 Port G Data Register (PGDR)................1084 28.2.20 Port H Data Register (PHDR)................1085 28.2.21 Port J Data Register (PJDR) ................1085 28.2.22 Port K Data Register (PKDR)................1086 28.2.23 Port L Data Register (PLDR)................1086 28.2.24 Port M Data Register (PMDR) ................1087 28.2.25 Port E Pull-Up Control Register (PEPUPR) ............
Page 26 29.6 Usage Notes ........................1132 Section 30 User Debugging Interface (H-UDI)..........1135 30.1 Features..........................1135 30.2 Input/Output Pins......................1137 30.3 Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS) .......... 1138 30.4 Register Descriptions....................... 1140 30.4.1 Instruction Register (SDIR) ................1141 30.4.2 Interrupt Source Register (SDINT)..............
Page 27 31.4 AC Characteristic Test Conditions................... 1214 31.5 Change in Delay Time Based on Load Capacitance ............1215 Appendix ......................1217 CPU Operation Mode Register (CPUOPM) ..............1217 Instruction Prefetching and Its Side Effects..............1219 Speculative Execution for Subroutine Return..............1220 Register Address Map...................... 1221 Package Dimensions ......................
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Page 29 Figures Section 1 Overview Figure 1.1 SH7780 Block Diagram ....................9 Figure 1.2 SH7780 Pin Arrangement.................... 10 Figure 1.3 Physical Address Space of SH7780................28 Figure 1.4 Relationship between AREASEL Bits and Memory Address Map......29 Section 2 Programming Model Figure 2.1 Data Formats .......................
Page 30 Section 7 Memory Management Unit (MMU) Figure 7.1 Role of MMU......................149 Figure 7.2 Virtual Address Space (AT in MMUCR = 0)............150 Figure 7.3 Virtual Address Space (AT in MMUCR = 1)............151 Figure 7.4 P4 Area........................153 Figure 7.5 Physical Address Space..................... 154 Figure 7.6 UTLB Configuration ....................
Page 31 Figure 11.2 Correspondence between Virtual Address Space and External Memory Space of LBSC......................321 Figure 11.3 External Memory Space Allocation (29-bit address mode)........323 Figure 11.4 Basic Timing of SRAM Interface................362 Figure 11.5 Example of 32-Bit Data-Width SRAM Connection ..........363 Figure 11.6 Example of 16-Bit Data-Width SRAM Connection ..........
Page 32 Figure 11.34 Wait Cycles between Access Cycles ..............394 Figure 11.35 Arbitration Sequence..................... 396 Figure 11.36 Example of the Bus Release Restraint by the DMAC CHCR LCKN bit ....398 Section 12 DDR-SDRAM Interface (DDRIF) Figure 12.1 DDRIF Block Diagram ................... 402 Figure 12.2 Physical Address Space of This LSI ...............
Page 33 Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ..535 Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 0) ................537 Figure 13.13 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 1) ................
Page 34 Section 15 Clock Pulse Generator (CPG) Figure 15.1 Block Diagram of CPG ................... 614 Figure 15.2 Points for Attention when Using Crystal Resonator..........622 Figure 15.3 Points for Attention when Using PLL and DLL Circuit.......... 623 Section 16 Watchdog Timer and Reset Figure 16.1 Block Diagram of WDT ..................
Page 35 Figure 19.5 CMT_CTRn Assert Timing (channel 0 and 1) ............694 Figure 19.6 32-Bit Timer Mode: Output Compare (channel 1 and channel 0) ......694 Figure 19.7 32-bit Timer Mode: Output Compare Operation Timing (Example of High output in Active and Not Active by CMTCHnST)....695 Figure 19.8 32-bit Timer Mode: Output Compare Operation Timing (Example of High output in Active and Not Active by CMTFRT)......
Page 36 Figure 21.12 Sample Serial Reception Flowchart (2)..............780 Figure 21.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ..........782 Figure 21.14 Sample Operation Using Modem Control (SCIF0_RTS) (Only in Channel 0)..782 Figure 21.15 Data Format in Clocked Synchronous Communication ........783 Figure 21.16 Sample SCIF Initialization Flowchart ..............
Page 37 Figure 23.4 Timing Conditions when FBS = 1................864 Section 24 Multimedia Card Interface (MMCIF) Figure 24.1 Block Diagram of MMCIF..................866 Figure 24.2 DR Access Example ....................899 Figure 24.3 Example of Command Sequence for Commands Not Requiring Command Response ................ 903 Figure 24.4 Example of Operational Flow for Commands Not Requiring Command Response ................
Page 38 Figure 24.18 Example of Command Sequence for Commands with Write Data (Stream Transfer)....................924 Figure 24.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer) ..................925 Figure 24.20 Example of Operational Flow for Commands with Write Data (1) (Open-ended Multiple Block Transfer) ..............
Page 39 Figure 25.5 Sample Flowchart for Off-Chip Codec Register Read (1) ........978 Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (2) ........979 Figure 25.7 Sample Flowchart for Off-Chip Codec Register Read (3) ........980 Section 26 Serial Sound Interface (SSI) Module Figure 26.1 Block Diagram of SSI Module ................
Page 40 Figure 27.7 Sector Access when Unusable Sector Exists in Continuous Sectors..... 1048 Figure 27.8 NAND Flash Command Access (Block Erase)............. 1050 Figure 27.9 NAND Flash Sector Access (Flash Write) Using DMA ........1051 Figure 27.10 NAND Flash Command Access (Flash Read) ............ 1052 Section 28 General Purpose I/O (GPIO) Figure 28.1 Port Data Output Timing (Example of Port A) .............
Page 41 Figure 31.18 PCMCIA I/O Bus Cycle (TEDx = 1, THEx = 1, IW/PCIW = 1, One Internal Wait, Dynamic Bus Sizing)........1175 Figure 31.19 MPX Basic Bus Cycle: Read................1176 Figure 31.20 MPX Basic Bus Cycle: Write................1177 Figure 31.21 MPX Bus Cycle: Burst Read................1178 Figure 31.22 MPX Bus Cycle: Burst Write ................
Page 42 Figure 31.56 SSI Receive Timing (2)..................1206 Figure 31.57 Command Issue Timing of NAND-type Flash Memory ........1208 Figure 31.58 Address Issue Timing of NAND-type Flash Memory......... 1209 Figure 31.59 Data Read Timing of NAND-type Flash Memory ..........1209 Figure 31.60 Data Write Timing of NAND-type Flash Memory ..........1210 Figure 31.61 Status Read Timing of NAND-type Flash Memory ..........
Page 43 Tables Section 1 Overview Table 1.1 SH7780 Features....................... 2 Table 1.2 Pin Functions ......................11 Section 2 Programming Model Table 2.1 Initial Register Values..................... 35 Table 2.2 Bit Allocation for FPU Exception Handling............45 Section 3 Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions ...........
Page 44 Section 7 Memory Management Unit (MMU) Table 7.1 Register Configuration..................156 Table 7.2 Register States in Each Processing State .............. 156 Section 8 Caches Table 8.1 Cache Features...................... 197 Table 8.2 Store Queue Features .................... 197 Table 8.3 Register Configuration..................200 Table 8.4 Register States in Each Processing State ..............
Page 45 Table 11.10 16-Bit External Device/Big-Endian Access and Data Alignment..... 353 Table 11.11 8-Bit External Device/Big-Endian Access and Data Alignment....... 354 Table 11.12 32-Bit External Device/Little-Endian Access and Data Alignment....355 Table 11.13 16-Bit External Device/Little-Endian Access and Data Alignment....355 Table 11.14 8-Bit External Device/Little-Endian Access and Data Alignment....
Page 46 Section 15 Clock Pulse Generator (CPG) Table 15.1 CPG Pin Configuration..................616 Table 15.2 Clock Operating Modes ..................617 Table 15.3 Register configuration................... 618 Table 15.4 Register States of CPG in Each Processing Mode ..........618 Section 16 Watchdog Timer and Reset Table 16.1 Pin Configuration....................
Page 47 Section 21 Serial Communication Interface with FIFO (SCIF) Table 21.1 Pin Configuration....................739 Table 21.2 Register Configuration..................740 Table 21.3 Register States of SCIF in Each Processing Mode ..........741 Table 21.4 SCSMR Settings ....................758 Table 21.5 SCSMR Settings for Serial Transfer Format Selection......... 770 Table 21.6 SCSMR and SCSCR Settings for SCIF Clock Source Selection......
Page 48 Section 25 Audio Codec Interface (HAC) Table 25.1 Pin Configuration....................956 Table 25.2 Register Configuration..................957 Table 25.3 Register States of HAC in Each Processing Mode ..........957 Table 25.4 AC97 Transmit Frame Structure................973 Table 25.5 AC97 Receive Frame Structure ................974 Section 26 Serial Sound Interface (SSI) Module Table 26.1 Pin Configuration....................
Page 49 = −20 to 75°C / −40 to 85°C)......... 1156 Table 31.2 DC Characteristics (T Table 31.3 Permissible Output Currents ................1159 Table 31.4 Clock Timing ...................... 1159 Table 31.5 Clock and Control Signal Timing ............... 1160 Table 31.6 Control Signal Timing ..................1163 Table 31.7 Bus Timing ......................
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Page 51: Section 1 Overview
Section 1 Overview Section 1 Overview SH7780 Features The SH7780 is an integrated system-on-a-chip microprocessor that is designed as a high performance, embedded, stand-alone Host Processor aimed at the multimedia, infotainment and consumer networking market. The SH7780 features a DDR-SDRAM interface that can be coupled to the DDR320* or 266 SDRAM.
Page 52: Section 1 Overview
• PCI bus interface (External bus):  32-bit address/data multiplexing  External bus frequency: 33M or 66 MHz • Renesas Technology original architecture • 32-bit internal data bus • General-register files:  Sixteen 32-bit general registers (eight 32-bit shadow registers) ...
Page 53 Section 1 Overview Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt generation for IEEE754 compliance •...
Page 54: Contents
Section 1 Overview Item Features • Memory 4 Gbytes of physical address space, 256 address space identifiers management (address space identifier ASID: 8 bits) unit (MMU) • Supports single virtual memory mode and multiple virtual memory mode • Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, or 1 Mbyte •...
Page 55 Section 1 Overview Item Features • Interrupt controller Nine independent external interrupts: NMI and IRQ7 to IRQ0 (INTC)  NMI: Fall/rise selectable  IRQ: Fall/rise/high level/low level selectable 15-level signed external interrupts: IRL3 to IRL0, or IRL7 to IRL4 • •...
Page 56 Section 1 Overview Item Features • PCI bus controller PCI bus controller (subset of revision 2.2) (PCIC)  32-bit bus  33 MHz/66 MHz support • PCI master/target support • PCI host function support  Built-in bus arbiter • Interrupt requests can be sent to CPU •...
Page 57 Section 1 Overview Item Features • Timer unit (TMU) 6-channel auto-reload 32-bit timer • Input-capture function (only channel 2) • Choice of seven types counter input clocks (external and peripheral clocks) • Compare Match 4-channel auto-reload 32-bit timers Timer (CMT) •...
Page 58 Section 1 Overview Item Features • Audio codec Digital interface for audio codec interface (HAC) • Supports transfer for slot 1 to slot 4 • Choice of 16- or 20-bit DMA transfer • Supports various sampling rates by adjusting slot data •...
Page 59: Block Diagram
Section 1 Overview Block Diagram (External bus) LBSC I-cache (External bus) DDRIF (External bus) PCIC DMAC O-cache SCIF SuperHyway channel 0 HSPI LRAM multiplexed INTC FLCTL SH-4A core SuperHyway SCIF router [Legend] channel 1 AUD: Advanced user debugger multiplexed CMT: Timer/counter MMCIF CPG:...
Page 60: Pin Arrangement
Section 1 Overview Pin Arrangement Figure 1.2 SH7780 Pin Arrangement Rev.1.00 Dec. 13, 2005 Page 10 of 1286 REJ09B0158-0100...
Page 61: Pin Functions
Section 1 Overview Pin Functions Table 1.2 lists the pin functions of the SH7780. In the I/O column, I, O, and IO indicate input, output, and input/output, respectively. In the GPIO column, for example, A0 indicates the port A0, which also functions as a general I/O port (input/output). Table 1.2 Pin Functions Pin Name...
Page 62 Section 1 Overview Pin Name Function GPIO* SCIF1_TXD/MCCLK/MODE5 O/O/I SCIF 1 transmit data/ H6(O) card clock output/mode control 5 XTAL2 RTC clock EXTAL2 RTC crystal resonator VDD-RTC — RTC VDD VSS-RTC — RTC GND VSSQ-DDR — DDR I/O GND VCCQ-DDR —...
Page 63 Section 1 Overview Pin Name Function GPIO* SCIF0_RXD/HSPI_RX/FRB I/I/I SCIF receive data/HSPI receive data input/NAND flash ready or busy TCLK/IOIS16 IO/I TMU clock/PCMCIA IOIS16 XRTCSTBI RTC standby VSSQ — I/O GND MDA0 DDR data VCCQ-DDR — DDR I/O VCC VSSQ-DDR —...
Page 64 Section 1 Overview Pin Name Function GPIO* SCIF0_TXD/HSPI_TX/FWE/MODE8 O/O/O/I SCIF0 transmit data/HSPI transmit H3(O) data/NAND flash write enable/ mode control 8 SCIF0_SCK/HSPI_CLK/FRE IO/IO/O SCIF0 serial clock/HSPI serial clock/NAND flash read enable VDDQ — I/O VDD IRQ/IRL7/FD7 I/IO IRL IRQ interrupt request 7/ NAND flash data MDA1 DDR data...
Page 65 Section 1 Overview Pin Name Function GPIO* — Internal VDD IRQ/IRL6/FD6/MODE6 I/IO/I IRL IRQ interrupt request 6/NAND flash data/mode control 6 IRQ/IRL5/FD5/MODE4 I/IO/I IRL IRQ interrupt request 5/NAND flash data/mode control 4 MDA2 DDR data MDA17 DDR data MDA18 DDR data VCCQ-DDR —...
Page 66 Section 1 Overview Pin Name Function GPIO* MDA3 DDR data MDA19 DDR data MDA20 DDR data VCCQ-DDR — DDR I/O VCC VSSQ-DDR — DDR I/O GND VDDQ — I/O VDD VDDQ — I/O VDD IRQ/IRL1 IRL IRQ interrupt request 1 IRQ/IRL0 IRL IRQ interrupt request 0 Nonmaskable interrupt...
Page 67 Section 1 Overview Pin Name Function GPIO* MDA7 DDR data MDA6 DDR data MDQM2 DDR data mask VDD-DLL1 — DLL1 VDD VSS-DLL1 — DLL1 GND — Internal VDD AD10 PCI address/data AD12 PCI address/data PCI address/data CBE0 PCI command/byte enable MDQM0 DDR data mask MDQS0...
Page 68 Section 1 Overview Pin Name Function GPIO* MDQM3 DDR data mask — Internal VDD — Internal GND — Internal GND — Internal GND — Internal GND VSSQ — I/O GND — Internal GND — Internal GND — Internal GND VDDQ —...
Page 69 Section 1 Overview Pin Name Function GPIO* PCI parity STOP PCI transaction stop MDA9 DDR data MDA26 DDR data MDA27 DDR data VSSQ-DDR — DDR I/O GND VSSQ-DDR — DDR I/O GND — Internal GND — Internal GND VSSQ-DDR — DDR I/O GND VSSQ —...
Page 70 Section 1 Overview Pin Name Function GPIO* — Internal GND — Internal VDD AD17 PCI address/data AD19 PCI address/data AD16 PCI address/data AD18 PCI address/data MDA11 DDR data MDA30 DDR data MDA31 DDR data VCCQ-DDR — DDR I/O VCC VCCQ-DDR —...
Page 71 Section 1 Overview Pin Name Function GPIO* — Internal GND — Internal GND — Internal GND — Internal GND — Internal GND — Internal VDD CBE3 PCI command/byte enable AD25 PCI address/data IDSEL PCI configuration device select AD24 PCI address/data MDA15 DDR data MDA14...
Page 72 Section 1 Overview Pin Name Function GPIO* Address bus STATUS0/CMT_CTR0 O/IO Status0/CMT0 timer counter STATUS1/CMT_CTR1 O/IO Status1/CMT1 timer counter — Internal VDD — Internal VDD — Internal GND REQ2 Bus request (PCI host) REQ1 Bus request (PCI host) GNT2 PCI bus grant GNT1 PCI bus grant Address bus...
Page 73 Section 1 Overview Pin Name Function GPIO* AA10 VSS — Internal GND AA11 VDD — Internal VDD AA12 VDDQ — I/O VDD AA13 VSSQ — I/O GND AA14 VSSQ — I/O GND AA15 VDD — Internal VDD AA16 VSS — Internal GND AA17 VDDQ —...
Page 74 Section 1 Overview Pin Name Function GPIO* AB15 VDDQ — I/O VDD AB16 VSSQ — I/O GND AB17 BACK Bus acknowledgement AB18 CS4 Chip select 4 AB19 CS6 Chip select 6 AB20 VSS-PLL3 — PLL3 GND AB21 VDD — Internal VDD AB22 VDDQ —...
Page 75 Section 1 Overview Pin Name Function GPIO* AC20 CS1 Chip select 1 AC21 VSS-PLL2 — PLL2 GND AC22 VDD — Internal VDD AC23 VDDQ — I/O VDD AC24 VDDQ — I/O VDD AC25 MPMD Mode control Address bus VDDQ — I/O VDD Address bus Address bus...
Page 76 Section 1 Overview Pin Name Function GPIO* AD25 VSSQ — I/O GND VSSQ — I/O GND Address bus Address bus Address bus Address bus Data bus Data bus WE3/IOWR Selection signal for D31 to D24 Data bus AE10 D17 Data bus AE11 WE2/IORD Selection signal for D23 to D16/PCMCIA IORD...
Page 77: Memory Address Map
Section 1 Overview Memory Address Map The SH7780 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical address spaces (normal mode and extended mode). For details of mappings from the virtual address space to the physical address spaces, see section 7, Memory Management Unit (MMU). The external memory space of the SH7780 consists of the LBSC space, DDRIF space and PCIC space.
Page 78: Figure 1.3 Physical Address Space Of Sh7780
Section 1 Overview H'0000 0000 Area 0 (LBSC) H'0400 0000 Area 1 (LBSC) H'0800 0000 Area 2 (LBSC/DDRIF) 29-bit physical address space H'0C00 0000 Area 3 (DDRIF) (Normal mode) H'1000 0000 Area 4 (LBSC/DDRIF/PCIC) H'1400 0000 Area 5 (LBSC/DDRIF) H'1800 0000 Area 6 (LBSC) H'1C00 0000 Area 7 (Reserved)
Page 79: Figure 1.4 Relationship Between Areasel Bits And Memory Address Map
Section 1 Overview MMSELR.AREASEL[2:0]* B'000 B'001 B'010 B'011 B'100 H'0000 0000 Area 0 (LBSC) LBSC LBSC LBSC LBSC LBSC H'0400 0000 Area 1 (LBSC) LBSC LBSC LBSC LBSC LBSC H'0800 0000 Area 2 (LBSC/DDRIF) LBSC LBSC DDRIF-0 DDRIF-0 DDRIF-0 H'0C00 0000 29-bit physical Area 3 (DDRIF) DDRIF-1...
Page 80: Superhyway Bus
Section 1 Overview SuperHyway Bus The SH7780 is implemented with the SuperHyway bus as the system bus. The SuperHyway bus is a 32-bit-address, 64-bit-data internal bus capable of up to 200 MHz operation that is connected to on-chip modules to allow high speed communication. Each module that is connected to the SuperHyway bus operates as an initiator (i.e.
Page 81: Superhyway Memory (Superhyway Ram)
Section 1 Overview SuperHyway Memory (SuperHyway RAM) The SH7780 includes an on-chip SuperHyway memory which stores instructions or data. The SuperHyway memory has the following features. • Capacity × × Total SuperHyway memory capacity is 32 Kbytes (512 words 256 bits 2 pages).
Page 82 Section 1 Overview Rev.1.00 Dec. 13, 2005 Page 32 of 1286 REJ09B0158-0100...
Page 83: Section 2 Programming Model
Section 2 Programming Model Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. Data Formats The data formats supported in this LSI are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits)
Page 84: Register Descriptions
Section 2 Programming Model Register Descriptions 2.2.1 Privileged Mode and Banks Processing Modes: This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted.
Page 85: Table 2.1 Initial Register Values
Section 2 Programming Model Floating-Point Registers and System Registers Related to FPU: There are thirty-two floating- point registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–...
Page 86: Figure 2.2 Cpu Register Configuration In Each Processing Mode
Section 2 Programming Model R0 _ BANK0* R0 _ BANK0* R0 _ BANK1* R1 _ BANK0* R1 _ BANK1* R1 _ BANK0* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK0* R3 _ BANK1* R4 _ BANK0* R4 _ BANK1* R4 _ BANK0*...
Page 87: General Registers
Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode.
Page 88: Floating-Point Registers
Section 2 Programming Model Note on Programming: As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0).
Page 89: Figure 2.4 Floating-Point Registers
Section 2 Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR=0 FPSCR.FR=1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XD10 XF10...
Page 90: Control Registers
Section 2 Programming Model 2.2.4 Control Registers Status Register (SR): BIt: Initial value: R/W: BIt: IMASK Initial value: R/W: Initial Bit Name Value Description — Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. Processing Mode Selects the processing mode.
Page 91 Section 2 Programming Model Initial Bit Name Value Description 27 to 16 — All 0 Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs.
Page 92: System Registers
Section 2 Programming Model Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined): The contents of SR are saved to SSR in the event of an exception or interrupt. Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 93 Section 2 Programming Model Floating-Point Status/Control Register (FPSCR) BIt: Cause Initial value: R/W: BIt: Cause Enable (EN) Flag Initial value: R/W: Initial Bit Name Value Description 31 to 22 — All 0 Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
Page 94 Section 2 Programming Model Initial Bit Name Value Description 17 to 12 Cause All 0 FPU Exception Cause Field FPU Exception Enable Field 11 to 7 Enable (EN) All 0 FPU Exception Flag Field 6 to 2 Flag All 0 Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0.
Page 95: Figure 2.5 Relationship Between Sz Bit And Endian
Section 2 Programming Model <Big endian> Floating-point register DR (2i) FR (2i) FR (2i+1) 32 31 Memory area 8n+3 8n+4 8n+7 <Little endian> Floating-point register DR (2i) DR (2i) DR (2i) *1, *2 FR (2i) FR (2i+1) FR (2i) FR (2i+1) FR (2i) FR (2i+1) 32 31...
Page 96: Memory-Mapped Registers
Section 2 Programming Model Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. •...
Page 97: Data Formats In Registers
Section 2 Programming Model Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Figure 2.6 Formats of Byte Data and Word Data in Register Rev.1.00 Dec.
Page 98: Data Formats In Memory
Section 2 Programming Model Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register.
Page 99: Processing States
Section 2 Programming Model Processing States This LSI has major three processing states: the reset state, instruction execution state, and power- down state. Reset State: In this state the CPU is reset. The reset state is divided into the power-on reset state and the manual reset.
Page 100: Usage Note
Section 2 Programming Model Usage Note 2.7.1 Notes on self-modified codes* This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the processing speed. Therefore if the instruction in the memory is modified and it is executed immediately, then the pre-modified code that is prefetched are likely to be executed. In order to execute the modified code definitely, one of the following sequences should be executed between the execution of modifying codes and modified codes.
Page 101: Section 3 Instruction Set
Section 3 Instruction Set Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size.
Page 102 Section 3 Instruction Set T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below.
Page 103: Addressing Modes
Section 3 Instruction Set Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 104 Section 3 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 Word: Rn + (word), or 4 (longword), according to the operand...
Page 105 Section 3 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC + 4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size.
Page 106 Section 3 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC + 4 with 12-bit PC + 4 + disp × 2 → Branch- displacement disp added after being sign-extended Target multiplied by 2.
Page 107: Instruction Set
Section 3 Instruction Set Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source operand...
Page 108 Section 3 Instruction Set Item Format Description Privileged mode "Privileged" means the instruction can only be executed in privileged mode. T bit Value of T bit after —: No change instruction execution  "New" means the instruction which is newly added in this LSI.
Page 109: Table 3.4 Fixed-Point Transfer Instructions
Section 3 Instruction Set Table 3.4 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit New imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — — (disp × 2 + PC + 4) → sign 1001nnnndddddddd — — —...
Page 110 → Rn Rm:Rn middle 32 bits → Rn XTRCT Rm,Rn 0010nnnnmmmm1101 — — — The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the Note: displacement (disp). Rev.1.00 Dec. 13, 2005 Page 60 of 1286 REJ09B0158-0100...
Page 111: Table 3.5 Arithmetic Operation Instructions
Section 3 Instruction Set Table 3.5 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn — — — 0011nnnnmmmm1100 #imm,Rn Rn + imm → Rn — — — 0111nnnniiiiiiii Rn + Rm + T → Rn, ADDC Rm,Rn —...
Page 112 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit DMULU.L Rm,Rn Unsigned, — — — 0011nnnnmmmm0101 Rn × Rm → MAC, 32 × 32 → 64 bits Rn – 1 → Rn; — — Comparison 0100nnnn00010000 when Rn = 0, result 1 →...
Page 113: Table 3.6 Logic Operation Instructions
Section 3 Instruction Set Table 3.6 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — — AND.B (R0 + GBR) & imm 11001101iiiiiiii —...
Page 114: Table 3.7 Shift Instructions
Section 3 Instruction Set Table 3.7 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — — LSB → Rn → T ROTR 0100nnnn00000101 — — T ← Rn ← T ROTCL 0100nnnn00100100 — —...
Page 115: Table 3.8 Branch Instructions
Section 3 Instruction Set Table 3.8 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — — 4 → PC When T = 1, nop BF/S label Delayed branch;...
Page 116: Table 3.9 System Control Instructions
Section 3 Instruction Set Table 3.9 System Control Instructions Instruction Operation Instruction Code Privileged T Bit New 0 → MACH, MACL CLRMAC 0000000000101000 — — — 0 → S CLRS 0000000001001000 — — — 0 → T CLRT 0000000000001000 — —...
Page 117 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit No operation 0000000000001001 — — — OCBI Invalidates operand cache 0000nnnn10010011 — — — block OCBP Writes back and invalidates 0000nnnn10100011 — — — operand cache block OCBWB Writes back operand cache 0000nnnn10110011 —...
Page 118 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit PR → Rn PR,Rn — — — 0000nnnn00101010 Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 STS.L MACH,@-Rn — — — Rn – 4 → Rn, MACL → (Rn) STS.L MACL,@-Rn —...
Page 119: Table 3.10 Floating-Point Single-Precision Instructions
Section 3 Instruction Set Table 3.10 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H'0000 0000 → FRn FLDI0 1111nnnn10001101 — — — H'3F80 0000 → FRn FLDI1 1111nnnn10011101 — — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — —...
Page 120: Table 3.11 Floating-Point Double-Precision Instructions
Section 3 Instruction Set Table 3.11 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — — FFFF → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 — — — When DRn = DRm, 1 →...
Page 121: Table 3.13 Floating-Point Graphics Acceleration Instructions
Section 3 Instruction Set Table 3.13 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn — — — 1111nnn1mmm01100 XDm → DRn FMOV XDm,DRn — — — 1111nnn0mmm11100 XDm → XDn FMOV XDm,XDn —...
Page 122 Section 3 Instruction Set Rev.1.00 Dec. 13, 2005 Page 72 of 1286 REJ09B0158-0100...
Page 123: Section 4 Pipelining
Section 4 Pipelining Section 4 Pipelining This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. Pipelines Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of seven stages: instruction sfetch (I1/I2), decode and register read (ID), execution (E1/E2/E3), and write-back (WB).
Page 124: Table 4.1 Representations Of Instruction Execution Patterns
Section 4 Pipelining Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.1 Representations of Instruction Execution Patterns Representation Description CPU EX pipe is occupied CPU LS pipe is occupied (with memory access) CPU LS pipe is occupied (without memory access) Either CPU EX pipe or CPU LS pipe is occupied E1/S1...
Page 125: Figure 4.2 Instruction Execution Patterns (1)
Section 4 Pipelining 1 issue cycle + 0 to 2 branch cycles (1-1) BF, BF/S, BT, BT/S, BRA, BSR: In branch instructions that are categorized Note: E1/S1 E2/s2 E3/s3 as (1-1), the number of branch cycles may be reduced by prefetching. (I1) (I2) (ID)
Page 126: Figure 4.2 Instruction Execution Patterns (2)
Section 4 Pipelining (2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT Note: Except for AND#, OR#, TST#, and XOR# instructions using GBR relative addressing mode (2-2) 1-step operation (LS type): 1 issue cycle MOVA...
Page 127: Figure 4.2 Instruction Execution Patterns (3)
Section 4 Pipelining (3-1) Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR) (3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles E1S1 E2S2 E3S3 (3-3) TAS.B: 4 issue cycles E1S1 E2S2 E3S3 E1S1 E2S2 E3S3 (3-4) PREF, OCBI, OCBP, OCBWB, MOVCA.L, SYNCO: 1 issue cycle (3-5) LDTLB: 1 issue cycle E1s1 E2s2...
Page 128: Figure 4.2 Instruction Execution Patterns (4)
Section 4 Pipelining (4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle (4-2) LDC to DBR/SGR: 4 issue cycles (4-3) LDC to GBR: 1 issue cycle (4-4) LDC to SR: 4 issue cycles + 3 branch cycles E1s1 E2s2 E3s3 (Branch to the (I1) (I2) (ID)
Page 129: Figure 4.2 Instruction Execution Patterns (5)
Section 4 Pipelining (4-9) STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-10) STC from SR: 1 issue cycle E1s1 E2s2 E3s3 (4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-12) STC.L from SR: 1 issue cycle E1S1 E2S2 E3S3 (4-13) LDS to PR: 1 issue cycle (4-14) LDS.L to PR: 1 issue cycle (4-15) STS from PR: 1 issue cycle (4-16) STS.L from PR: 1 issue cycle...
Page 130: Figure 4.2 Instruction Execution Patterns (6)
Section 4 Pipelining (5-1) LDS to MACH/L: 1 issue cycle (5-2) LDS.L to MACH/L: 1 issue cycle (5-3) STS from MACH/L: 1 issue cycle (5-4) STS.L from MACH/L: 1 issue cycle (5-5) MULS.W, MULU.W: 1 issue cycle (5-6) DMULS.L, DMULU.L, MUL.L: 1 issue cycle (5-7) CLRMAC: 1 issue cycle (5-8) MAC.W: 2 issue cycle (5-9) MAC.L: 2 issue cycle...
Page 131: Figure 4.2 Instruction Execution Patterns (7)
Section 4 Pipelining (6-1) LDS to FPUL: 1 issue cycle (6-2) STS from FPUL: 1 issue cycle (6-3) LDS.L to FPUL: 1 issue cycle (6-4) STS.L from FPUL: 1 issue cycle (6-5) LDS to FPSCR: 1 issue cycle (6-6) STS from FPSCR: 1 issue cycle (6-7) LDS.L to FPSCR: 1 issue cycle (6-8) STS.L from FPSCR: 1 issue cycle (6-9) FPU load/store instruction FMOV: 1 issue cycle...
Page 132: Figure 4.2 Instruction Execution Patterns (8)
Section 4 Pipelining (6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle (6-13) FLDI0, FLDI1: 1 issue cycle (6-14) Single-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG, FPCHG (6-15) Single-precision FDIV/FSQRT: 1 issue cycle FEDS (Divider occupied cycle) (6-16) Double-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FSUB, FTRC, FCNVSD, FCNVDS...
Page 133: Figure 4.2 Instruction Execution Patterns (9)
Section 4 Pipelining (6-19) FIPR: 1 issue cycle (6-20) FTRV: 1 issue cycle (6-21) FSRRA: 1 issue cycle FEPL Function computing unit occupied cycle (6-22) FSCA: 1 issue cycle FEPL Function computing unit occupied cycle Figure 4.2 Instruction Execution Patterns (9) Rev.1.00 Dec.
Page 134: Parallel-Executability
Section 4 Pipelining Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 4.2 Instruction Groups Instruction...
Page 135 Section 4 Pipelining Instruction Group Instruction FADD FDIV FRCHG FSCA FSUB FIPR FSCHG FSRRA FCMP (S/D) FLOAT FSQRT FPCHG FCNVDS FMAC FTRC FCNVSD FMUL FTRV AND.B #imm,@(R0,GBR) LDC.L @Rm+,SR PREFI TRAPA ICBI LDTLB TST.B #imm,@(R0,GBR) LDC Rm,DBR MAC.L SLEEP XOR.B #imm,@(R0,GBR) LDC Rm, SGR MAC.W STC SR,Rn...
Page 136: Table 4.3 Combination Of Preceding And Following Instructions
Section 4 Pipelining Table 4.3 Combination of Preceding and Following Instructions Preceding Instruction (addr) Following Instruction (addr+2) Note: The following table shows the parallel-executability of pairs of instructions in this LSI. It is different from table 4.3. Preceding Instruction (addr) FLSR FLSM Following...
Page 137: Issue Rates And Execution Cycles
Section 4 Pipelining Issue Rates and Execution Cycles Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not considered in the issue rates and execution cycles in this section. 1.
Page 138: Table 4.4 Issue Rates And Execution Cycles
Section 4 Pipelining Table 4.4 Issue Rates and Execution Cycles Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Data transfer EXTS.B Rm,Rn instructions EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn Rm,Rn #imm,Rn MOVA @(disp,PC),R0 MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV.B @Rm,Rn...
Page 139 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Data transfer MOV.L Rm,@-Rn instructions MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B R0,@(disp,GBR) MOV.W R0,@(disp,GBR) MOV.L R0,@(disp,GBR) MOVCA.L R0,@Rn MOVCO.L R0,@Rn MOVLI.L...
Page 140 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Fixed-point CMP/HI Rm,Rn arithmetic CMP/HS Rm,Rn instructions CMP/PL CMP/PZ CMP/STR Rm,Rn DIV0S Rm,Rn DIV0U DIV1 Rm,Rn DMULS.L Rm,Rn DMULU.L Rm,Rn MAC.L @Rm+,@Rn+ MAC.W @Rm+,@Rn+ MUL.L Rm,Rn MULS.W Rm,Rn...
Page 141 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Logical TST.B #imm,@(R0,GBR) instructions Rm,Rn #imm,R0 XOR.B #imm,@(R0,GBR) Shift ROTL instructions ROTR ROTCL ROTCR 100 SHAD Rm,Rn 101 SHAL 102 SHAR 103 SHLD Rm,Rn 104 SHLL 105 SHLL2 106 SHLL8 107 SHLL16...
Page 142 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern System 123 NOP control 124 CLRMAC instructions 125 CLRS 126 CLRT 127 ICBI 8+5+3 128 SETS 129 SETT 130 PREFI 5+5+3 131 SYNCO Undefined Undefined 132 TRAPA #imm 8+5+1...
Page 143 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern System 154 LDS Rm,PR 4-13 control 155 LDS.L @Rm+,MACH instructions 156 LDS.L @Rm+,MACL 157 LDS.L @Rm+,PR 4-14 158 STC DBR,Rn 159 STC SGR,Rn 160 STC GBR,Rn 161 STC Rp_BANK,Rn...
Page 144 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Single- 185 FMOV.S @(R0,Rm),FRn precision 186 FMOV.S FRm,@Rn floating-point 187 FMOV.S FRm,@-Rn instructions 188 FMOV.S FRm,@(R0,Rn) 189 FLDS FRm,FPUL 6-10 190 FSTS FPUL,FRn 6-11 191 FABS 6-12 192 FADD FRm,FRn...
Page 145 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Double- 216 FDIV DRm,DRn 6-18 precision 217 FLOAT FPUL,DRn 6-16 floating-point 218 FMUL DRm,DRn 6-17 instructions 219 FNEG 6-12 220 FSQRT 6-18 221 FSUB DRm,DRn 6-16 222 FTRC DRm,FPUL...
Page 146 Section 4 Pipelining Rev.1.00 Dec. 13, 2005 Page 96 of 1286 REJ09B0158-0100...
Page 147: Section 5 Exception Handling
Section 5 Exception Handling Section 5 Exception Handling Summary of Exception Handling Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing.
Page 148: Trapa Exception Register (Tra)
Section 5 Exception Handling 5.2.1 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. Bit: Initial value: R/W:...
Page 149: Exception Event Register (Expevt)
Section 5 Exception Handling 5.2.2 Exception Event Register (EXPEVT) The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs.
Page 150: Interrupt Event Register (Intevt)
Section 5 Exception Handling 5.2.3 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. Bit: Initial value: R/W: Bit:...
Page 151: Exception Handling Functions
Section 5 Exception Handling Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 152: Exception Types And Priorities
Section 5 Exception Handling Exception Types and Priorities Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.3 Exceptions Exception Transition Direction* Exception Execution Priority Priority Vector Exception Category Mode Exception Level* Order* Address Offset...
Page 153 Section 5 Exception Handling Exception Transition Direction* Exception Execution Priority Priority Vector Exception Category Mode Exception Level* Order* Address Offset Code* General Completion Unconditional trap (TRAPA) (VBR) H'100 H'160 exception type User break after instruction (VBR/DBR) H'100/— H'1E0 execution* Interrupt Completion Nonmaskable interrupt —...
Page 154: Exception Flow
Section 5 Exception Handling Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.1 shows the relative priority order of the different kinds of exceptions (reset, general exception, and interrupt).
Page 155: Figure 5.1 Instruction Execution And Exception Handling
Section 5 Exception Handling Reset requested? Execute next instruction Is highest- General priority exception exception requested? re-exception type? Cancel instruction execution result Interrupt requested? SSR ← SR EXPEVT ← exception code SPC ← PC SR. {MD, RB, BL, FD, IMASK} ← 11101111 SGR ←...
Page 156: Exception Source Acceptance
Section 5 Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline.
Page 157: Exception Requests And Bl Bit
Section 5 Exception Handling 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A0000000).
Page 158: Description Of Exceptions
Section 5 Exception Handling Description of Exceptions The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 Resets Power-On Reset: • Condition: Power-on reset request •...
Page 159 Section 5 Exception Handling Instruction TLB Multiple-Hit Exception: • Source: Multiple ITLB address matches • Transition address: H'A0000000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 160: General Exceptions
Section 5 Exception Handling 5.6.2 General Exceptions Data TLB Miss Exception: • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 161 Section 5 Exception Handling Instruction TLB Miss Exception: • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 162 Section 5 Exception Handling Initial Page Write Exception: • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'00000100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 163 Section 5 Exception Handling Data TLB Protection Violation Exception: • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible...
Page 164 Section 5 Exception Handling Instruction TLB Protection Violation Exception: • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H'00000100 •...
Page 165 Section 5 Exception Handling Data Address Error: • Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) ...
Page 166 Section 5 Exception Handling Instruction Address Error: • Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in user mode. For details, see section 9, L Memory.
Page 167 Section 5 Exception Handling Unconditional Trap: • Source: Execution of TRAPA instruction • Transition address: VBR + H'00000100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 168 Section 5 Exception Handling General Illegal Instruction Exception: • Sources:  Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 169 Section 5 Exception Handling Slot Illegal Instruction Exception: • Sources:  Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR, ICBI, PREFI ...
Page 170 Section 5 Exception Handling General FPU Disable Exception: • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 171 Section 5 Exception Handling Slot FPU Disable Exception: • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 172 Section 5 Exception Handling Pre-Execution User Break/Post-Execution User Break: • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'00000100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 173 Section 5 Exception Handling FPU Exception: • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR .
Page 174: Interrupts
Section 5 Exception Handling 5.6.3 Interrupts NMI (Nonmaskable Interrupt): • Source: NMI pin edge detection • Transition address: VBR + H'00000600 • Transition operations: The PC and SR contents for the instruction immediately after this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 175: Priority Order With Multiple Exceptions
Section 5 Exception Handling General Interrupt Request: • Source: The interrupt mask level bits setting in SR is smaller than the interrupt level of interrupt request, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'00000600 •...
Page 176 Section 5 Exception Handling • Instructions that make two accesses to memory With MAC instructions, memory-to-memory arithmetic/logic instructions, TAS instructions, and MOVUA instructions, two data transfers are performed by a single instruction, and an exception will be detected for each of these data transfers. In these cases, therefore, the following order is used to determine priority.
Page 177: Usage Notes
Section 5 Exception Handling Usage Notes 1. Return from exception handling A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit in SR to 1 before restoring them. B.
Page 178 Section 5 Exception Handling 5. Changing the SR register value and accepting exception A. When the MD or BL bit in the SR register is changed by the LDC instruction, the acceptance of the exception is determined by the changed SR value, starting from the next instruction.* In the completion type exception, an exception is accepted after the next instruction has been executed.
Page 179: Section 6 Floating-Point Unit (Fpu)
Section 6 Floating-Point Unit (FPU) Section 6 Floating-Point Unit (FPU) Features The FPU has the following features. • Conforms to IEEE754 standard • 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Round to Nearest and Round to Zero •...
Page 180: Data Formats
Section 6 Floating-Point Unit (FPU) Data Formats 6.2.1 Floating-Point Format A floating-point number consists of the following three fields: • Sign bit (s) • Exponent field (e) • Fraction field (f) The SH-4A can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2.
Page 181 Section 6 Floating-Point Unit (FPU) Table 6.1 Floating-Point Number Formats and Parameters Parameter Single-Precision Double-Precision Total bit width 32 bits 64 bits Sign bit 1 bit 1 bit Exponent field 8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits...
Page 182: Table 6.2 Floating-Point Ranges
Section 6 Floating-Point Unit (FPU) Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFF FFFF to H'7FC0 0000 H'7FFF FFFF FFFF FFFF to H'7FF8 0000 0000 0000 Quiet non-number H'7FBF FFFF to H'7F80 0001 H'7FF7 FFFF FFFF FFFF to H'7FF0 0000 0000 0001 Positive infinity H'7F80 0000...
Page 183: Non-Numbers (Nan)
Section 6 Floating-Point Unit (FPU) 6.2.2 Non-Numbers (NaN) Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: • Sign bit: Don't care • Exponent field: All bits are 1 • Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0.
Page 184: Denormalized Numbers
Section 6 Floating-Point Unit (FPU) See SH-4A Software Manual for details of floating-point operations when a non-number (NaN) is input. 6.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. When the DN bit in FPSCR of the FPU is 1, a denormalized number (source operand or operation result) is always positive or negative zero in a floating-point operation that generates a value (an operation other than transfer instructions between registers, FNEG, or FABS).
Page 185: Register Descriptions
Section 6 Floating-Point Unit (FPU) Register Descriptions 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers comprised with two banks: FPR0_BANK0 to FPR15_BANK0, and FPR0_BANK1 to FPR15_BANK1. These thirty-two registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, and XMTRX.
Page 186: Figure 6.4 Floating-Point Registers
Section 6 Floating-Point Unit (FPU) 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0 BANK0 XMTRX FPR1 BANK0 FPR2 BANK0 FPR3 BANK0 FPR4 BANK0 FPR5 BANK0 FPR6 BANK0...
Page 187: Floating-Point Status/Control Register (Fpscr)
Section 6 Floating-Point Unit (FPU) 6.3.2 Floating-Point Status/Control Register (FPSCR) bit: Cause Initial value: R/W: bit: Cause Enable (EN) Flag Initial value: R/W: Bit Name Initial Value Description 31 to 22 — All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 188 Section 6 Floating-Point Unit (FPU) Bit Name Initial Value Description 17 to 12 Cause All 0 FPU Exception Cause Field FPU Exception Enable Field 11 to 7 Enable All 0 FPU Exception Flag Field 6 to 2 Flag All 0 Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0.
Page 189: Figure 6.5 Relation Between Sz Bit And Endian
Section 6 Floating-Point Unit (FPU) <Big endian> Floating-point register DR (2i) FR (2i) FR (2i+1) 32 31 Memory area 8n+3 8n+4 8n+7 <Little endian> Floating-point register DR (2i) DR (2i) DR (2i) *1, *2 FR (2i) FR (2i+1) FR (2i) FR (2i+1) FR (2i) FR (2i+1)
Page 190: Floating-Point Communication Register (Fpul)
Section 6 Floating-Point Unit (FPU) Table 6.3 Bit Allocation for FPU Exception Handling Invalid Division Overflow Underflow Inexact Field Name Error (E) Operation (V) by Zero (Z) Cause FPU exception Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 cause field Enable...
Page 191: Rounding
Section 6 Floating-Point Unit (FPU) Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL.
Page 192: Floating-Point Exceptions
Section 6 Floating-Point Unit (FPU) Floating-Point Exceptions 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1. When the FPU instruction is in other than delayed slot, the general FPU disable exception is occurred.
Page 193 Section 6 Floating-Point Unit (FPU) • Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result underflow • Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation result All exception events that originate in the FPU are assigned as the same exception event. The meaning of an exception is determined by software by reading from FPSCR and interpreting the information it contains.
Page 194: Graphics Support Functions
Section 6 Floating-Point Unit (FPU) Graphics Support Functions The SH-4A supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations. To enable high-speed computation with a minimum of hardware, the SH-4A ignores comparatively small values in the partial computation results of four multiplications.
Page 195: Pair Single-Precision Data Transfer
Section 6 Floating-Point Unit (FPU) • Matrix (4 × 4) × matrix (4 × 4): This operation requires the execution of four FTRV instructions. Since an inexact exception is not detected by an FIRV instruction, the inexact exception (I) bit in both the FPU exception cause field and flag field are always set to 1 when an FTRV instruction is executed.
Page 196 Section 6 Floating-Point Unit (FPU) Rev.1.00 Dec. 13, 2005 Page 146 of 1286 REJ09B0158-0100...
Page 197: Section 7 Memory Management Unit (Mmu)
Section 7 Memory Management Unit (MMU) Section 7 Memory Management Unit (MMU) This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit physical address space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit (MMU) in this LSI.
Page 198 Section 7 Memory Management Unit (MMU) When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information.
Page 199: Address Spaces
Section 7 Memory Management Unit (MMU) Virtual Memory Physical Process 1 Physical Memory Physical Process 1 Memory Memory Process 1 Virtual Physical Process 1 Process 1 Memory Memory Physical Memory Process 2 Process 2 Process 3 Process 3 Figure 7.1 Role of MMU 7.1.1 Address Spaces Virtual Address Space: This LSI supports a 32-bit virtual address space, and can access a 4-...
Page 200: Figure 7.2 Virtual Address Space (At In Mmucr = 0)
Section 7 Memory Management Unit (MMU) Mapping from the virtual address space to the 29-bit physical address space is carried out using the TLB. Physical address space H'0000 0000 H'0000 0000 Area 0 Area 1 Area 2 Area 3 U0 area Area 4 P0 area Cacheable...
Page 201: Figure 7.3 Virtual Address Space (At In Mmucr = 1)
Section 7 Memory Management Unit (MMU) Physical address space H'0000 0000 H'0000 0000 Area 0 Area 1 Area 2 Area 3 P0 area U0 area Cacheable Area 4 Cacheable Address translation possible Area 5 Address translation possible Area 6 Area 7 H'8000 0000 H'8000 0000 P1 area...
Page 202 Section 7 Memory Management Unit (MMU) • P0, P3, and U0 Areas: The P0, P3, and U0 areas allow address translation using the TLB and access using the cache. When the MMU is disabled, replacing the upper 3 bits of an address with 0s gives the corresponding physical address.
Page 203: Figure 7.4 P4 Area
Section 7 Memory Management Unit (MMU) H'E000 0000 Store queue H'E400 0000 Reserved area H'E500 0000 On-chip memory area H'E600 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data array H'F400 0000...
Page 204: Figure 7.5 Physical Address Space
Section 7 Memory Management Unit (MMU) The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 8.6.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array.
Page 205 Section 7 Memory Management Unit (MMU) Address Translation: When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes.
Page 206: Register Descriptions
Section 7 Memory Management Unit (MMU) Register Descriptions The following registers are related to MMU processing. Table 7.1 Register Configuration Access Register Name Abbreviation P4 Address* Area 7 Address* Size Page table entry high register PTEH H'FF00 0000 H'1F00 0000 Page table entry low register PTEL H'FF00 0004...
Page 207: Page Table Entry High Register (Pteh)
Section 7 Memory Management Unit (MMU) 7.2.1 Page Table Entry High Register (PTEH) PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN bit by hardware.
Page 208: Page Table Entry Low Register (Ptel)
Section 7 Memory Management Unit (MMU) Initial Bit Name Value Description  31 to 10 Virtual Page Number  9, 8 All 0 Reserved These bits are always read as 0. The write value should always be 0.  7 to 0 ASID Address Space Identifier 7.2.2...
Page 209: Translation Table Base Register (Ttb)
Section 7 Memory Management Unit (MMU) Initial Bit Name Value Description  Page Management Information  The meaning of each bit is same as that of corresponding bit in Common TLB (UTLB).  For details, see section 7.3, TLB Functions. ...
Page 210: Mmu Control Register (Mmucr)
Section 7 Memory Management Unit (MMU) 7.2.5 MMU Control Register (MMUCR) The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the P0, P3, U0, or store queue area is performed.
Page 211 Section 7 Memory Management Unit (MMU) Initial Bit Name Value Description 31 to 26 LRUI All 0 Least Recently Used ITLB These bits indicate the ITLB entry to be replaced. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss.
Page 212 Section 7 Memory Management Unit (MMU) Initial Bit Name Value Description  17, 16 All 0 Reserved These bits are always read as 0. The write value should always be 0. 15 to 10 All 0 UTLB Replace Counter These bits serve as a random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction.
Page 213 Section 7 Memory Management Unit (MMU) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. Address Translation Enable Bit These bits enable or disable the MMU. 0: MMU disabled 1: MMU enabled MMU exceptions are not generated when the AT bit is 0.
Page 214: Physical Address Space Control Register (Pascr)
Section 7 Memory Management Unit (MMU) 7.2.6 Physical Address Space Control Register (PASCR) PASCR controls the operation in the physical address space. Bit: Initial value: R/W: Bit: Initial value: R/W: Initial Bit Name Value Description  31 to 8 All 0 Reserved These bits are always read as 0.
Page 215: Instruction Re-Fetch Inhibit Control Register (Irmcr)
Section 7 Memory Management Unit (MMU) 7.2.7 Instruction Re-Fetch Inhibit Control Register (IRMCR) When the specific resource is changed, IRMCR controls whether the instruction fetch is performed again for the next instruction. The specific resource means the part of control registers, TLB, and cache.
Page 216 Section 7 Memory Management Unit (MMU) Initial Bit Name Value Description Re-Fetch Inhibit after LDTLB Execution This bit controls whether re-fetch is performed for the next instruction after the LDTLB instruction has been executed. 0: Re-fetch is performed 1: Re-fetch is not performed Re-Fetch Inhibit after Writing Memory-Mapped TLB This bit controls whether re-fetch is performed for the next instruction after writing memory-mapped...
Page 217: Tlb Functions
Section 7 Memory Management Unit (MMU) TLB Functions 7.3.1 Unified TLB (UTLB) Configuration The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the ITLB in the event of an ITLB miss The UTLB is so called because of its use for the above two purposes.
Page 218 Section 7 Memory Management Unit (MMU) • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ[1:0]: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page •...
Page 219: Figure 7.7 Relationship Between Page Size And Address Format
Section 7 Memory Management Unit (MMU) 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed •...
Page 220: Instruction Tlb (Itlb) Configuration
Section 7 Memory Management Unit (MMU) 7.3.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 7.8 shows the ITLB configuration.
Page 221: Address Translation Method
Section 7 Memory Management Unit (MMU) 7.3.3 Address Translation Method Figure 7.9 shows a flowchart of a memory access using the UTLB. Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area...
Page 222: Figure 7.10 Flowchart Of Memory Access Using Itlb
Section 7 Memory Management Unit (MMU) Figure 7.10 shows a flowchart of a memory access using the ITLB. Instruction access to virtual address (VA) VA is in P0, U0, VA is VA is VA is or P3 area in P1 area in P4 area in P2 area MMUCR.AT = 1...
Page 223: Mmu Functions
Section 7 Memory Management Unit (MMU) MMU Functions 7.4.1 MMU Hardware Management This LSI supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2.
Page 224: Mmu Instruction (Ldtlb)
Section 7 Memory Management Unit (MMU) 7.4.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, this LSI copies the contents of PTEH and PTEL to the UTLB entry indicated by the URC bit in MMUCR.
Page 225: Hardware Itlb Miss Handling
Section 7 Memory Management Unit (MMU) MMUCR 26252423 18171615 10 9 8 7 3 2 1 0 LRUI — — — TI — AT SQMD Entry specification PTEH PTEL 10 9 8 7 2928 9 8 7 6 5 4 3 2 1 0 —...
Page 226: Avoiding Synonym Problems
Section 7 Memory Management Unit (MMU) 7.4.5 Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity.
Page 227: Mmu Exceptions
Section 7 Memory Management Unit (MMU) MMU Exceptions There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 7.9 and 7.10 for the conditions under which each of these exceptions occurs.
Page 228: Instruction Tlb Miss Exception
Section 7 Memory Management Unit (MMU) 7.5.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling routine.
Page 229: Instruction Tlb Protection Violation Exception
Section 7 Memory Management Unit (MMU) 7.5.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.
Page 230: Data Tlb Multiple Hit Exception
Section 7 Memory Management Unit (MMU) 7.5.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. When a data TLB multiple hit exception occurs, a reset is executed, and cache coherency is not guaranteed.
Page 231: Data Tlb Protection Violation Exception
Section 7 Memory Management Unit (MMU) 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry.
Page 232: Initial Page Write Exception
Section 7 Memory Management Unit (MMU) 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow.
Page 233: Memory-Mapped Tlb Configuration
Section 7 Memory Management Unit (MMU) 4. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction.
Page 234: Itlb Address Array
Section 7 Memory Management Unit (MMU) 7.6.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 235: Itlb Data Array
Section 7 Memory Management Unit (MMU) 7.6.2 ITLB Data Array The ITLB data array is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 236: Utlb Address Array
Section 7 Memory Management Unit (MMU) 7.6.3 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 237: Utlb Data Array
Section 7 Memory Management Unit (MMU) 14 13 Address field 1 1 1 1 0 1 1 0 0 0 0 0 * * * * * * * * * * 10 9 8 7 Data field ASID VPN: Virtual page number ASID: Address space identifier...
Page 238: 32-Bit Address Extended Mode
Section 7 Memory Management Unit (MMU) 14 13 Address field 1 1 1 1 0 1 1 1 0 0 0 0 * * * * * * * * * * 29 28 10 9 8 7 2 1 0 Data field PPN: Physical page number...
Page 239: Overview Of 32-Bit Address Extended Mode
Section 7 Memory Management Unit (MMU) 7.7.1 Overview of 32-Bit Address Extended Mode In 32-bit address extended mode, the privileged space mapping buffer (PMB) is introduced. The PMB maps virtual addresses in the P1 or P2 area which are not translated in 29-bit address mode to the 32-bit physical address space.
Page 240: Figure 7.17 Pmb Configuration
Section 7 Memory Management Unit (MMU) Entry 0 VPN [31:24] PPN [31:24] SZ [1:0] Entry 1 VPN [31:24] PPN [31:24] SZ [1:0] Entry 2 VPN [31:24] PPN [31:24] SZ [1:0] Entry 15 VPN [31:24] PPN [31:24] SZ [1:0] C UB Figure 7.17 PMB Configuration [Legend] •...
Page 241: Pmb Function
Section 7 Memory Management Unit (MMU) With a 512-Mbyte page, PPN[31:29] are valid. • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode •...
Page 242: Memory-Mapped Pmb Configuration
Section 7 Memory Management Unit (MMU) VPN[31:30] is 10 or not. When an entry from the PMB is recorded in the ITLB, H′00, 01, and 1 are recorded in the ASID, PR, and SH fields which do not exist in the PMB, respectively. 7.7.5 Memory-Mapped PMB Configuration To enable the PMB to be managed by software, its contents are allowed to be read from and...
Page 243: Figure 7.18 Memory-Mapped Pmb Address Array
Section 7 Memory Management Unit (MMU) 12 11 Address field 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data field VPN: Physical page number : Reserved bits (write value should be 0 Validity bit and read value is undefined )
Page 244: Notes On Using 32-Bit Address Extended Mode
Section 7 Memory Management Unit (MMU) 7.7.6 Notes on Using 32-Bit Address Extended Mode When using 32-bit address extended mode, note that the items described in this section are extended or changed as follows. PASCR: The SE bit is added in bit 31 in the control register (PASCR). The bits 6 to 0 of the UB in the PASCR are invalid (Note that the bit 7 of the UB is still valid).
Page 245 Section 7 Memory Management Unit (MMU) ITLB: The PPN field in the ITLB is extended to bits 31 to 10. UTLB: The PPN field in the UTLB is extended to bits 31 to 10. The same UB bit as that in the PMB is added in each entry of the UTLB.
Page 246 Section 7 Memory Management Unit (MMU) 4. Note that the V bit is mapped to both address array and data array in PMB registration. That is, first write 0 to the V bit in one of arrays and then write 1 to the V bit in another array. Rev.1.00 Dec.
Page 247: Section 8 Caches
Section 8 Caches Section 8 Caches This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte operand cache (OC) for data. Features The features of the cache are shown in table 8.1. This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory.
Page 248: Figure 8.1 Configuration Of Operand Cache (Oc)
Section 8 Caches The operand cache of this LSI uses the 4-way set-associative, each way comprising 256 cache lines. Figure 8.1 shows the configuration of the operand cache. The instruction cache is 4-way set-associative, each way is comprising 256 cache lines. Figure 8.2 shows the configuration of the instruction cache.
Page 249: Figure 8.2 Configuration Of Instruction Cache (Ic)
Section 8 Caches Virtual address 13 12 [12:5] Longword (LW) selection Entry selection Address array Data array (way 0 to way 3) (way 0 to way 3) 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits...
Page 250: Register Descriptions
Section 8 Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each entry address.
Page 251: Cache Control Register (Ccr)
Section 8 Caches 8.2.1 Cache Control Register (CCR) CCR controls the cache operating mode, the cache write mode, and invalidation of all cache entries. CCR modifications must only be made by a program in the non-cacheable P2 area. After CCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area is performed.
Page 252 Section 8 Caches Initial Bit Name Value Description  10, 9 All 0 Reserved These bits are always read as 0. The write value should always be 0. IC Enable Bit Selects whether the IC is used. Note however when address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1.
Page 253: Queue Address Control Register 0 (Qacr0)
Section 8 Caches 8.2.2 Queue Address Control Register 0 (QACR0) QACR0 specifies the area maped which store queue 0 (SQ0) is mapped when the MMU is disabled. Bit: Initial value: R/W: Bit: AREA0 Initial value: R/W: Initial Bit Name Value Description ...
Page 254: Queue Address Control Register 1 (Qacr1)
Section 8 Caches 8.2.3 Queue Address Control Register 1 (QACR1) QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled. Bit: Initial value: R/W: Bit: AREA1 Initial value: R/W: Initial Bit Name Value Description ...
Page 255: On-Chip Memory Control Register (Ramcr)
Section 8 Caches 8.2.4 On-Chip Memory Control Register (RAMCR) RAMCR controls the number of ways in the IC and OC. RAMCR modifications must only be made by a program in the non-cacheable P2 area. After RAMCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area or the L memory area is performed.
Page 256 Section 8 Caches Initial Bit Name Value Description  31 to 10 All 0 Reserved These bits are always read as 0. The write value should always be 0. On-Chip Memory Access Mode Bit For details, see section 9.4, L Memory Protective Functions.
Page 257: Operand Cache Operation
Section 8 Caches Operand Cache Operation 8.3.1 Read Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is read from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 258: Prefetch Operation
Section 8 Caches 5. Cache miss (with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address.
Page 259: Write Operation
Section 8 Caches 5. Cache miss (with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address.
Page 260 Section 8 Caches 5. Cache miss (copy-back, no write-back) A data write in accordance with the access size is performed for the data of the data field on the hit way which is indexed by virtual address bits [4:0]. Then, the data, excluding the cache- missed data which is written already, is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address.
Page 261: Write-Back Buffer
Section 8 Caches 8.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, this LSI has a write- back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss.
Page 262: Instruction Cache Operation
Section 8 Caches Instruction Cache Operation 8.4.1 Read Operation When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, U bit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 263: Prefetch Operation
Section 8 Caches 8.4.2 Prefetch Operation When the IC is enabled (ICE = 1 in CCR) and instruction prefetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, Ubit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 264: Cache Operation Instruction
Section 8 Caches Cache Operation Instruction 8.5.1 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In this LSI, the following six instructions are supported for cache operations. Details of these instructions are given in the Software Manual.
Page 265: Prefetch Operation
Section 8 Caches PURGE transaction: When the operand cache is enabled, the PURGE transaction checks the operand cache and invalidates the hit entry. If the invalidated entry is dirty, the data is written back to the external memory. If the transaction is not hit to the cache, it is no-operation. FLUSH transaction: When the operand cache is enabled, the FLUSH transaction checks the operand cache and if the hit line is dirty, then the data is written back to the external memory.
Page 266: Memory-Mapped Cache Configuration
Section 8 Caches Memory-Mapped Cache Configuration To enable the IC and OC to be managed by software, the IC contents can be read from or written to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area.
Page 267: Ic Address Array
Section 8 Caches 8.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 268: Figure 8.5 Memory-Mapped Ic Address Array
Section 8 Caches 5 4 3 2 1 0 Address field 1 1 1 1 0 0 0 0 Entry * * * * * * * * * 10 9 Data field : Validity bit : Association bit : Reserved bits (write value should be 0 and read value is undefined ) : Don't care Figure 8.5 Memory-Mapped IC Address Array Rev.1.00 Dec.
Page 269: Ic Data Array
Section 8 Caches 8.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 270: Oc Address Array
Section 8 Caches 8.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 271: Figure 8.7 Memory-Mapped Oc Address Array
Section 8 Caches Note: This function may not be supported in the future SuperH Series. Therefore, it is recommended that the OCBI, OCBP, or OCBWB instruction should be used to operate the OC definitely by reporting data TLB miss exception. 1312 5 4 3 2 1 0 Address field...
Page 272: Oc Data Array
Section 8 Caches 8.6.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 273: Store Queues
Section 8 Caches Store Queues This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. 8.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 8.9. These two store queues can be set independently.
Page 274: Transfer To External Memory
Section 8 Caches 8.7.3 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a transfer from the SQs to external memory.
Page 275: Determination Of Sq Access Exception
Section 8 Caches 8.7.4 Determination of SQ Access Exception Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is enabled or disabled. If an exception occurs during a write to an SQ, the SQ contents before the write are retained.
Page 276: Notes On Using 32-Bit Address Extended Mode
Section 8 Caches Notes on Using 32-Bit Address Extended Mode In 32-bit address extended mode, the items described in this section are extended as follows. 1. The tag bits [28:10] (19 bits) in the IC and OC are extended to bits [31:10] (22 bits). 2.
Page 277: Section 9 L Memory
Section 9 L Memory Section 9 L Memory This LSI includes on-chip L-memory which stores instructions or data. Features • Capacity • Total L memory capacity is 16 Kbytes. The L memory is divided into two pages (pages 0 and 1). •...
Page 278: Register Descriptions
Section 9 L Memory Register Descriptions The following registers are related to L memory. Table 9.2 Register Configuration Access Register Name Abbreviation P4 Address* Area 7 Address* Size On-chip memory control RAMCR H'FF000074 H'1F000074 register L memory transfer source LSA0 H'FF000050 H'1F000050 address register 0...
Page 279: On-Chip Memory Control Register (Ramcr)
Section 9 L Memory 9.2.1 On-Chip Memory Control Register (RAMCR) RAMCR controls the protective functions in the L memory. Bit : Initial value : R/W: Bit : IC2W OC2W Initial value : R/W: Initial Bit Name Value Description 31to10 — All 0 Reserved These bits are always read as 0.
Page 280: L Memory Transfer Source Address Register 0 (Lsa0)
Section 9 L Memory 9.2.2 L Memory Transfer Source Address Register 0 (LSA0) When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA0 specifies the transfer source physical address for block transfer to page 0 of the L memory. Bit : L0SADR Initial value : R/W:...
Page 281 Section 9 L Memory Initial Bit Name Value Description 5 to 0 L0SSZ Undefined R/W L Memory Page 0 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to the L memory.
Page 282: L Memory Transfer Source Address Register 1 (Lsa1)
Section 9 L Memory 9.2.3 L Memory Transfer Source Address Register 1 (LSA1) When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA1 specifies the transfer source physical address for block transfer to page 1 in the L memory. Bit : L1DADR Initial value : R/W:...
Page 283 Section 9 L Memory Initial Bit Name Value Description 5 to 0 L1SSZ Undefined R/W L Memory Page 1 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 1 in the L memory.
Page 284: L Memory Transfer Destination Address Register 0 (Lda0)
Section 9 L Memory 9.2.4 L Memory Transfer Destination Address Register 0 (LDA0) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifies the transfer destination physical address for block transfer to page 0 of the L memory. Bit : L0SADR Initial value : R/W:...
Page 285 Section 9 L Memory Initial Bit Name Value Description 5 to 0 L0DSZ Undefined R/W L Memory Page 0 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 0 in the L memory.
Page 286: L Memory Transfer Destination Address Register 1 (Lda1)
Section 9 L Memory 9.2.5 L Memory Transfer Destination Address Register 1 (LDA1) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifies the transfer destination physical address for block transfer to page 1 in the L memory. Bit : L1SADR Initial value : R/W:...
Page 287 Section 9 L Memory Initial Bit Name Value Description 5 to 0 L1DSZ Undefined R/W L Memory Page 1 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 1 in the L memory.
Page 288: Operation
Section 9 L Memory Operation 9.3.1 Access from the CPU and FPU L memory access from the CPU and FPU is direct via the instruction bus and operand bus by means of the virtual address. As long as there is no conflict on the page, the L memory is accessed in one cycle.
Page 289 Section 9 L Memory When the PREF instruction is issued to the L memory area, address conversion is performed in order to generate the physical address bits [28:10] in accordance with the SZ bit specification. The physical address bits [9:5] are generated from the virtual address prior to address conversion. The physical address bits [4:0] are fixed to 0.
Page 290: L Memory Protective Functions
Section 9 L Memory L Memory Protective Functions This LSI implements the following protective functions to the L memory by using the on-chip memory access mode bit (RMD) and the on-chip memory protection enable bit (RP) in the on-chip memory control register (RAMCR). •...
Page 291: Usage Notes
Section 9 L Memory Usage Notes 9.5.1 Page Conflict In the event of simultaneous access to the same page from different buses, page conflict occurs. Although each access is completed correctly, this kind of conflict tends to lower L memory accessibility.
Page 292 Section 9 L Memory Rev.1.00 Dec. 13, 2005 Page 242 of 1286 REJ09B0158-0100...
Page 293: Section 10 Interrupt Controller (Intc)
Section 10 Interrupt Controller (INTC) Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) determines the priority of interrupt sources and controls the flow of interrupt requests to the CPU (SH-4A). The INTC has registers for setting the priority of each of the interrupts and processing of interrupt requests follows the priority order set in these registers by the user.
Page 294: Figure 10.1 Block Diagram Of Intc
Section 10 Interrupt Controller (INTC) CPU Exception IRQOUT Output control Handling Input control Interrupt (noise canseler, IRQ/IRL7 to acceptance detection) IRQ/IRL0 Priority determination USERIMASK.UIMASK IRQ/IRL7 and GPIO SR.IMASK Port E6 are multiplexed INTPRI GPIO Port Bus interface E6 to E0 ICR0, ICR1 H1, H0 K5, K4...
Page 295: Interrupt Method
Section 10 Interrupt Controller (INTC) 10.1.1 Interrupt Method The basic flow of exception handling for interrupts is as follows. In interrupt exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the interrupt exception handling routine at the corresponding vector address.
Page 296: Interrupt Types In Intc
Section 10 Interrupt Controller (INTC) 10.1.2 Interrupt Types in INTC Table 10.1 shows an example of the interrupt types. The INTC supports both external interrupts and on-chip module interrupts. External interrupts refer to the interrupts input through the external NMI, IRL, and IRQ pins. The IRQ and IRL interrupts are assigned to the same pins in the SH7780.
Page 297 Section 10 Interrupt Controller (INTC) Number of Sources Source (Max.) Priority INTEVT Remarks IRL[7:4] pin = H'9 External Inverse of values on the input H'320 High interrupts interrupt* pins (because the signals are IRL[3:0] pin = H'9 active low) IRL[7:4] pin = H'A H'340 For example IRL[3:0] pin = H'A...
Page 298 Section 10 Interrupt Controller (INTC) Number of Sources Source (Max.) Priority INTEVT Remarks On-chip DMAC(0) 7(5/7) Values set in INT2PRI0 to H'640 DMINT0* module INT2PRI7 H'660 DMINT1* interrupts H'680 DMINT2* H'6A0 DMINT3* H'6C0 DMAE* SCIF-ch0 4 H'700 ERI0* H'720 RXI0* H'740 BRI0* H'760...
Page 299 Section 10 Interrupt Controller (INTC) Number of Sources Source (Max.) Priority INTEVT Remarks On-chip MMCIF Values set in INT2PRI0 to H'D00 FSTAT module INT2PRI7 H'D20 TRAN interrupts H'D40 H'D60 FRDY DMAC(1) 6 (4/6) H'D80 DMINT8* H'DA0 DMINT9* H'DC0 DMINT10* H'DE0 DMINT11* TMU-ch3 1 H'E00...
Page 300: Input/Output Pins
Section 10 Interrupt Controller (INTC) FLTRQ0: FLCTL data FIFO transfer request interrupt FLTRQ1: FLCTL control code FIFO transfer request interrupt 10.2 Input/Output Pins Table 10.2 shows the pin configuration. Table 10.2 INTC Pin Configuration Pin Name Function Description Nonmaskable interrupt Input Nonmaskable interrupt request signal input pin...
Page 301: Register Descriptions
Section 10 Interrupt Controller (INTC) 10.3 Register Descriptions Table 10.3 shows the INTC register configuration. Table 10.4 shows the register states in each operating mode. Table 10.3 INTC Register Configuration Access Sync. Name Abbreviation P4 Address Area 7 Address Size Clock Interrupt control register 0 ICR0...
Page 302 Section 10 Interrupt Controller (INTC) Access Sync. Name Abbreviation P4 Address Area 7 Address Size Clock Interrupt source register INT2A1 H'FFD4 0034 H'1FD4 0034 (affected by the mask state) Interrupt mask register INT2MSKR H'FFD4 0038 H'1FD4 0038 Interrupt mask clear register INT2MSKCR H'FFD4 003C H'1FD4 003C...
Page 303: Table 10.4 Register States In Each Operating Mode
Section 10 Interrupt Controller (INTC) Table 10.4 Register States in Each Operating Mode Power-on Reset Manual Reset by by PRESET WDT/Multiple Sleep by SLEEP Name Abbreviation Pin/WDT/H-UDI Exception Instruction Interrupt control register 0 ICR0 H'x000 0000* H'x000 0000* Retained Interrupt control register 1 ICR1 H'0000 0000 H'0000 0000...
Page 304 Section 10 Interrupt Controller (INTC) Power-on Reset Manual Reset by by PRESET WDT/Multiple Sleep by SLEEP Name Abbreviation Pin/WDT/H-UDI Exception Instruction On-chip module interrupt INT2B0 H'xxxx xxxx H'xxxx xxxx Retained source registers INT2B1 H'xxxx xxxx H'xxxx xxxx Retained INT2B2 H'xxxx xxxx H'xxxx xxxx Retained INT2B3...
Page 305: Interrupt Control Register 0 (Icr0)
Section 10 Interrupt Controller (INTC) 10.3.1 Interrupt Control Register 0 (ICR0) ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode for the external interrupt input pins (IRQ/IRL [7:0]) and NMI pin, and indicates the level being input on the NMI pin.
Page 306 Section 10 Interrupt Controller (INTC) Initial Name Value Description NMIB NMI Block Mode Selects whether an NMI interrupt is held until the BL bit in SR is cleared to 0 or detected immediately when the BL bit in SR of the CPU is set to 1. 0: An NMI interrupt is held when the BL bit in SR is set to 1 (initial value) 1: An NMI interrupt is not held when the BL bit in SR is...
Page 307 Section 10 Interrupt Controller (INTC) Initial Name Value Description IRLM1 IRL Pin Mode 1 Selects whether IRQ/IRL7 to IRQ/IRL4 are used as 4- bit level-encoded interrupt requests or as four independent interrupts. 0: IRQ/IRL7 to IRQ/IRL4 are used as the 4-bit level- encoded interrupt requests (IRL [7:4] interrupt;...
Page 308: Interrupt Control Register 1 (Icr1)
Section 10 Interrupt Controller (INTC) 10.3.2 Interrupt Control Register 1 (ICR1) ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection modes of external interrupt input pins IRQ/IRL7 to IRQ/IRL0. These settings are only valid for pins configured as individual IRQ interrupts; that is, for pins for which the IRLM0 or IRLM1 bit in ICR0 is set to 1.
Page 309: Interrupt Priority Register (Intpri)
Section 10 Interrupt Controller (INTC) Note: When an IRQ pin is set for level input (IRQnS1 = 1), the interrupt source is held until the CPU accepts the interrupt (this is also true for other interrupts). Therefore, even if an interrupt source is disabled before this LSI returns from sleep mode, branching of processing to the interrupt handler when this LSI returns from sleep mode is guaranteed.
Page 310: Interrupt Source Register (Intreq)
Section 10 Interrupt Controller (INTC) 10.3.4 Interrupt Source Register (INTREQ) INTREQ is a 32-bit readable and conditionally writable register that indicates which of the IRQ [n] (n = 0 to 7) interrupts is currently asserting a request for the INTC. Even if an interrupt is masked by the setting in INTPRI or INTMSK0, operation of the corresponding INTREQ bit is not affected.
Page 311: Interrupt Mask Registers (Intmsk0 To Intmsk2)
Section 10 Interrupt Controller (INTC) 10.3.5 Interrupt Mask Registers (INTMSK0 to INTMSK2) INTMSK0 to INTMSK2 are 32-bit readable and conditionally writable registers that control mask settings for the interrupt requests. To clear a mask setting for interrupts, write 1 to the corresponding bit in INTMSKCLR0 to INTMSKCLR2.
Page 312 Section 10 Interrupt Controller (INTC) Initial Name Value Description 23 to 0 All 0 Reserved These bits are always read as 0. The write value should always be 0. Note: When the 4-bit encoded interrupt inputs are to be used, write B'1111 to the IM [03:00] or IM [07:04] bits to mask single-pin interrupts in the ranges IRQ/IRL [3:0] or IRQ/IRL [7:4], respectively.
Page 313 Section 10 Interrupt Controller (INTC) • Interrupt mask register 2 (INTMSK2) INTMSK2 settings are valid for particular IRL interrupt codes generated by the pattern of input signals on pins IRL7 to IRL4 or IRL3 to IRL0 and when all IRL interrupts from the corresponding set of pins are not masked by the setting in INTMSK1.
Page 314 Section 10 Interrupt Controller (INTC) Initial Name Value Description IM007 Sets masking of interrupt- [When reading] request generation by IRL3 0: The interrupt is to IRL0 = HLLL (H'8). acceptable. IM006 Sets masking of interrupt- 1: The interrupt is request generation by IRL3 masked.
Page 315 Section 10 Interrupt Controller (INTC) Initial Name Value Description IM111 Sets masking of interrupt- [When reading] request generation by IRL7 0: The interrupt is to IRL4 = LHLL (H'4). acceptable. IM110 Sets masking of interrupt- 1: The interrupt is request generation by IRL7 masked.
Page 316: Interrupt Mask Clear Registers (Intmskclr0 To Intmskclr2)
Section 10 Interrupt Controller (INTC) 10.3.6 Interrupt Mask Clear Registers (INTMSKCLR0 to INTMSKCLR2) INTMSKCLR0 to INTMSKCLR2 are 32-bit write-only registers that clear the mask settings for each interrupt request. Values read are undefined. • Interrupt mask clear register 0 (INTMSKCLR0) Bit: ...
Page 317 Section 10 Interrupt Controller (INTC) • Interrupt mask clear register 1 (INTMSKCLR1) Bit:               IC10 IC11 Initial value: R/W: Bit:        ...
Page 318 Section 10 Interrupt Controller (INTC) • Interrupt mask clear register 2 (INTMSKCLR2) Bit:  IC015 IC014 IC009 IC008 IC007 IC006 IC013 IC012 IC011 IC010 IC005 IC004 IC003 IC002 IC001 Initial value: R/W: Bit:  IC115 IC114 IC113 IC112 IC111 IC110 IC109 IC108 IC107...
Page 319 Section 10 Interrupt Controller (INTC) Initial Name Value Description IC006 Clears masking of interrupt- [When reading] request generation by IRL3 Values read are to IRL0 = HLLH (H'9). undefined. IC005 Clears masking of interrupt- [When writing] request generation by IRL3 to IRL0 = HLHL (H'A).
Page 320 Section 10 Interrupt Controller (INTC) Initial Name Value Description IC110 Clears masking of interrupt- [When reading] request generation by IRL7 Values read are to IRL4 = LHLH (H'5). undefined. IC109 Clears masking of interrupt- [When writing] request generation by IRL7 to IRL4 = LHHL (H'6).
Page 321: Nmi Flag Control Register (Nmifcr)
Section 10 Interrupt Controller (INTC) 10.3.7 NMI Flag Control Register (NMIFCR) NMIFCR is a 32-bit readable and conditionally writable register that has an NMI flag (NMIFL bit) which can be read or cleared by software. The NMIFL bit is automatically set to 1 by hardware when an NMI interrupt is detected by the INTC.
Page 322 Section 10 Interrupt Controller (INTC) Initial Name Value Description NMIFL R/(W) NMI Interrupt Request Signal Detection Indicates whether an NMI interrupt request signal has been detected. This bit is automatically set to 1 when the INTC detects an NMI interrupt request. Write 0 to clear the bit.
Page 323: User Interrupt Mask Level Register (Userimask)
Section 10 Interrupt Controller (INTC) 10.3.8 User Interrupt Mask Level Register (USERIMASK) USERIMASK is a 32-bit readable and conditionally writable register that sets the acceptable interrupt level. When addresses in area 7 are accessed by using the MMU’s address translation function, USERIMASK can be accessed in user mode.
Page 324 Section 10 Interrupt Controller (INTC) Initial Name Value Description 31 to 24 WKEY H'00 When writing a value to bits 7 to 4, always write H'A5 here. These bits are always read as 0. 23 to 8 — All 0 Reserved These bits are always read as 0.
Page 325 Section 10 Interrupt Controller (INTC) 4. Set the UIMASK bits so that B-type interrupts are masked during execution of the device driver that is operating in user mode. 5. Process interrupts with a high priority in the device driver. 6. Clear the UIMASK bits to 0 to return from processing in the device driver. Rev.1.00 Dec.
Page 326: On-Chip Module Interrupt Priority Registers (Int2Pri0 To Int2Pri7)
Section 10 Interrupt Controller (INTC) 10.3.9 On-chip Module Interrupt Priority Registers (INT2PRI0 to INT2PRI7) INT2PRI0 to INT2PRI7 are 32-bit readable/writable registers used to set priorities (levels 31 to 0) for the on-chip module interrupts. INT2PRI0 to INT2PRI7 are initialized to H'0000 0000 by a reset.
Page 327: Interrupt Source Register (Int2A0: Not Affected By Mask States)
Section 10 Interrupt Controller (INTC) 10.3.10 Interrupt Source Register (INT2A0: Not affected by Mask States) INT2A0 is a 32-bit read-only register that indicates interrupt states of interrupt source modules regardless of the corresponding mask states. Even if interrupt masking is set in the interrupt mask register, corresponding bits in INT2A0 indicate source modules for which interrupt conditions have been satisfied (the corresponding interrupt is not generated).
Page 328 Section 10 Interrupt Controller (INTC) Initial Value R/W Source Function Description — PCIC (5) Indicates PCIERR and Indicates interrupt sources for PCIPWD3 to PCIPWD0 the individual peripheral interrupt sources modules (INT2A0 is not affected by the state of the — PCIC (4) Indicates PCIINTD interrupt mask register).
Page 329 Section 10 Interrupt Controller (INTC) Initial Value R/W Source Function Description — Indicates RTC interrupt Indicates interrupt sources for source the individual peripheral modules (INT2A0 is not — TMU channels 3 Indicates the TMU channel affected by the state of the to 5 3 to 5 interrupt sources interrupt mask register).
Page 330: Interrupt Source Register (Int2A1: Affected By Mask States)
Section 10 Interrupt Controller (INTC) 10.3.11 Interrupt Source Register (INT2A1: Affected by Mask States) INT2A is a 32-bit read-only register that indicates interrupt states of interrupt source modules for which the interrupts are not masked. Note that if an interrupt mask is set in the interrupt mask register, INT2A1 does not indicate the interrupt state of the source module in the corresponding bit.
Page 331 Section 10 Interrupt Controller (INTC) Initial Value R/W Source Function Description PCIC (5) Indicates PCIERR and Indicates interrupt sources for the PCIPWD3 to PCIPWD0 individual peripheral modules interrupt sources (INT2A1 is affected by the state of the interrupt mask register). PCIC (4) Indicates PCIINTD interrupt source...
Page 332: Interrupt Mask Register (Int2Mskr)
Section 10 Interrupt Controller (INTC) Initial Value R/W Source Function Description Indicates the RTC interrupt Indicates interrupt sources for the source individual peripheral modules (INT2A1 is affected by the state of Indicates the TMU channel 3 the interrupt mask register). channels to 5 interrupt source 3 to 5...
Page 333: Table 10.8 Correspondence Between Bits In Int2Mskr And Interrupt Masking
Section 10 Interrupt Controller (INTC) Table 10.8 Correspondence between Bits in INT2MSKR and Interrupt Masking Initial Value R/W Target Function Description Masks interrupts for 31 to All 1 (Reserved) These bits are always read as 1. individual modules. The write value should always be 1. [When reading] R/W GPIO Masks the GPIO interrupt...
Page 334 Section 10 Interrupt Controller (INTC) Initial Value R/W Target Function Description R/W RTC Masks the RTC interrupt Masks interrupts for individual modules. R/W TMU channels Masks TMU channels 3 to 5 [When reading] 3 to 5 interrupts 0: No masking R/W TMU channels Masks TMU channels 0 to 2 0 to 2...
Page 335: Interrupt Mask Clear Register (Int2Mskcr)
Section 10 Interrupt Controller (INTC) 10.3.13 Interrupt Mask Clear Register (INT2MSKCR) INT2MSKCR is a 32-bit write-only register used to clear mask settings in the interrupt mask register. Setting a bit in this register to 1 clears the masking of the corresponding interrupt source. The bits of this register are always read as 0.
Page 336 Section 10 Interrupt Controller (INTC) Initial Value R/W Target Function Description R/W PCIC (2) Clears the PCIINTB interrupt Clears interrupt masking masking for each peripheral module. R/W PCIC (1) Clears the PCIINTA interrupt [When reading] masking Always 0 R/W PCIC (0) Clears the PCISERR interrupt masking [When writing]...
Page 337: On-Chip Module Interrupt Source Registers (Int2B0 To Int2B7)
Section 10 Interrupt Controller (INTC) 10.3.14 On-chip Module Interrupt Source Registers (INT2B0 to INT2B7) INT2B0 to INT2B7 are 32-bit read-only registers that indicate more details on sources within interrupt source modules for which the interrupt state is indicated in the interrupt source register. INT2B0 to INT2B7 are not affected by the state of masking in the interrupt mask register.
Page 338 Section 10 Interrupt Controller (INTC) INT2B1: Indicates detailed interrupt sources for the RTC. Module Name Detailed Source Description  31 to 3 (Reserved) Indicates RTC interrupt sources. This register indicates the RTC These bits are always interrupt sources even if the mask read as 0.
Page 339 Section 10 Interrupt Controller (INTC) INT2B3: Indicates detailed interrupt sources for the DMAC. Module Name Detailed Source Description  DMAC 31 to 14 (Reserved) Indicates DMAC interrupt sources. This register indicates These bits are always read DMAC interrupt sources even if as 0.
Page 340 Section 10 Interrupt Controller (INTC) INT2B4: Indicates detailed interrupt sources for the PCIC. Module Name Detailed Source Description  PCIC 31 to 10 (Reserved) Indicates PCIC interrupt sources. This register indicates the PCIC These bits are always interrupt sources even if a mask read as 0.
Page 341 Section 10 Interrupt Controller (INTC) INT2B5: Indicates detailed interrupt sources for the MMC. Module Name Detailed Source Description  MMCIF 31 to 4 (Reserved) Indicates MMC interrupt sources. This register indicates MMC interrupt These bits are always sources even if the mask setting for read as 0.
Page 342 Section 10 Interrupt Controller (INTC) INT2B6: Indicates detailed interrupt sources for the FLCTL. Module Name Detailed Source Description  FLCTL 31 to 4 (Reserved) Indicates FLCTL interrupt sources. This register indicates FLCTL These bits are always interrupt sources even if the mask read as 0.
Page 343 Section 10 Interrupt Controller (INTC) INT2B7: Indicates detailed interrupt sources for the GPIO. Description Module Name Detailed Source 31 to 26  GPIO (Reserved) Indicates GPIO interrupt sources. This register indicates the states of PORTE6I GPIO interrupt from port E GPIO interrupt sources even if pin 6.
Page 344: Gpio Interrupt Set Register (Int2Gpic)
Section 10 Interrupt Controller (INTC) 10.3.15 GPIO Interrupt Set Register (INT2GPIC) INT2GPIC enables interrupt requests input from the following pins: pins 0 to 6 of port E, pins 0 and 1 of port H, pin 0 of port J, and pins 4 and 5 of port J. A GPIO interrupt is an active low level-sensed signal.
Page 345: Table 10.10 Correspondence Between Interrupt Input Pins And Bits In Int2Gpic
Section 10 Interrupt Controller (INTC) Table 10.10 shows the correspondence between the interrupt input pins and bits in INT2GPIC. Table 10.10 Correspondence between Interrupt Input Pins and Bits in INT2GPIC Initial Value R/W Name Function Description 31 to All 0 R/W (Reserved) These bits are always read Enables a GPIO interrupt...
Page 346: Interrupt Sources
Section 10 Interrupt Controller (INTC) 10.4 Interrupt Sources There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip modules. Each interrupt has a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored.
Page 347: Irl Interrupts
Section 10 Interrupt Controller (INTC) upward compatibility with the “level-sense IRQ mode” of current SH-4 products (here, too, the detection of high or low levels is selectable). Note: When high-or low-level detection is selected, once the interrupt request has been detected, the INTC holds the interrupt request as an interrupt source in INTREQ even if the level on the IRQ interrupt pin has been changed and canceled.
Page 348: Table 10.11 Irl[3:0], Irl[7:4] Pins And Interrupt Levels
Section 10 Interrupt Controller (INTC) Table 10.11 IRL[3:0], IRL[7:4] Pins and Interrupt Levels IRL3 or IRL2 or IRL1 or IRL0 or Interrupt IRL7 IRL6 IRL5 IRL4 Priority Level Interrupt Request Level 15 interrupt request High Level 14 interrupt request High Level 13 interrupt request High High...
Page 349: On-Chip Module Interrupts
Section 10 Interrupt Controller (INTC) Note: There is no interrupt source register for IRL interrupt requests. When the holding function is in use, however, operation is as follows. If, after detection of an IRL interrupt, the levels on the IRL pins are changed or withdraw the interrupt before it has been accepted by the CPU, the detection circuit retains the highest detected priority level for IRL interrupts until the CPU accepts any interrupt request (IRL or not) or the corresponding mask bit has been set to 1.
Page 350: Interrupt Priority Levels Of On-Chip Module Interrupts
Section 10 Interrupt Controller (INTC) interrupt request within this LSI. Processing can be continued without any problem after the execution of an RTE instruction. 10.4.5 Interrupt Priority Levels of On-chip Module Interrupts When any interrupt is generated, the INTC outputs the corresponding interrupt exception code (INTEVT code) to the CPU.
Page 351: Interrupt Exception Handling And Priority
Section 10 Interrupt Controller (INTC) INTC distinguishes between priority levels of H'1A and H'1B, Priority level H'01 acts as an interrupt request mask. although both become the same level after rounding off for the CPU. INTC INTC Priority level: higher (H'1B) lower (H'1A) Priority level: H'01 Priority level:...
Page 352: Table 10.12 Interrupt Exception Handling And Priority
Section 10 Interrupt Controller (INTC) priority level-setting registers, or clear the corresponding interrupt mask. This will secure the necessary timing internally. Table 10.12 Interrupt Exception Handling and Priority Priority Interrupt Detail within Source Source Sets of INTEVT Interrupt Mask/Clear Default Interrupt Source Code Priority...
Page 353 Section 10 Interrupt Controller (INTC) Priority Interrupt Detail within INTEVT Interrupt Mask/Clear Source Source Sets of Default Interrupt Source Code Priority Register & Bit Register Register Sources Priority IRL[7:4] = LHHH (H'7)   H'2E0 INTMSK2[8] High INTMSKCLR2[8] L: Low IRL[3:0] = LHHH (H'7) ...
Page 354 Section 10 Interrupt Controller (INTC) Priority Interrupt Detail within INTEVT Interrupt Mask/Clear Source Source Sets of Default Interrupt Source Code Priority Register & Bit Register Register Sources Priority  IRQ[0] H'240 INTPRI INTMSK0[31] INTREQ High High [31:28] INTMSKCLR0 [31] [31] ...
Page 355 Section 10 Interrupt Controller (INTC) Priority Interrupt Detail within INTEVT Interrupt Mask/Clear Source Source Sets of Default Interrupt Source Code Priority Register & Bit Register Register Sources Priority  H-UDI H-UDII H'600 INT2PRI3 INT2MSKR[7] INT2A0[7] High [28:24] INT2MSKCR[7] INT2A1[7] DMAC(0) DMINT0* H'640 INT2PRI3 INT2MSKR[8]...
Page 356 Section 10 Interrupt Controller (INTC) Priority Interrupt Detail within INTEVT Interrupt Mask/Clear Source Source Sets of Default Interrupt Source Code Priority Register & Bit Register Register Sources Priority PCIC(5) PCIERR H'AA0 INT2PRI5 INT2MSKR[19] INT2A0[19] INT2B4[5] High High [4:0] INT2MSKCR[19] INT2A1[19] PCIPWD3 H'AC0 INT2B4[6]...
Page 357 Section 10 Interrupt Controller (INTC) Priority Interrupt Detail within INTEVT Interrupt Mask/Clear Source Source Sets of Default Interrupt Source Code Priority Register & Bit Register Register Sources Priority FLCTL FLSTE* H'F00 INT2PRI7 INT2MSKR[24] INT2A0[24] INT2B6[0] High High [28:24] INT2MSKCR[24] INT2A1[24] FLTEND* H'F20 INT2B6[1]...
Page 358: Operation
Section 10 Interrupt Controller (INTC) 10.5 Operation 10.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 10.4 is the flowchart of the operations. 1. Interrupt request sources send interrupt request signals to the INTC. 2. The INTC selects the interrupt with the highest-priority among the interrupts that have been sent, according to the priority levels set in INTPRI and INT2PRI0 to INT2PRI7.
Page 359: Figure 10.4 Interrupt Operation Flowchart
Section 10 Interrupt Controller (INTC) Program execution state ICR0.MAI = 1? Is NMI input low? Interrupt generated? SR.BL = 0 or sleep mode? ICR0.NMIB = 1? NMI? NMI? Level 15 interrupt? Level 14 interrupt? Is SR.IMASK level Level 1 14 or less interrupt? Is SR.IMASK level 13 or less...
Page 360: Multiple Interrupts
Section 10 Interrupt Controller (INTC) 10.5.2 Multiple Interrupts When multiple interrupts must be handled, the interrupt handling routine should include the following procedure: 1. Identify the interrupt source by using the INTEVT code as an offset in branching to the corresponding interrupt handling routine.
Page 361: Interrupt Response Time
Section 10 Interrupt Controller (INTC) 10.6 Interrupt Response Time Table 10.13 shows the components of the interrupt response time for the five classes of interrupt in terms of response time. The response time is the interval from generation of an interrupt request until the start of interrupt exception handling;...
Page 362: Usage Notes
Section 10 Interrupt Controller (INTC) 10.7 Usage Notes 10.7.1 To Clear Interrupt Request When Holding Function Selected When an IRQ level-sense interrupt request or IRL level-encoded interrupt request (IRQ/IRL level interrupt request) is generated and the holding function is in use, the interrupt request must be cleared in the interrupt handling routine after it has been accepted.
Page 363: Notes On Setting Irq/Irl[7:0] Pin Function
Section 10 Interrupt Controller (INTC) 10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function When switching between individual interrupt and level-encoded interrupt functions on the IRQ/IRL[7:0] pins, the INTC may wind up holding an interrupt that was generated by mistake. Therefore, to prevent the detection of such unintentional interrupts, mask all IRQ and IRL interrupts before switching between IRQ/IRL[7:0] pin functions.
Page 364 Section 10 Interrupt Controller (INTC) IRQ interrupt requests held in the detection circuit are not cleared even if a 0 is written to the corresponding bit in INTPRI. The IRQ interrupt sources detected by the INTC (which will be cleared when they are accepted by the CPU) can be confirmed by reading INTREQ. When not using holding function (ICR0.LSH = 1), the interrupt request is not held but the interrupt source is set to the corresponding bit in INTREQ that is to be cleared when the CPU accepts it.
Page 365: Section 11 Local Bus State Controller (Lbsc)
Section 11 Local Bus State Controller (LBSC) Section 11 Local Bus State Controller (LBSC) The local bus state controller (LBSC) divides the external memory space and outputs control signals corresponding to the specifications of various types of memory and bus interfaces. The LBSC enables the connection of SRAM or ROM, etc., to this LSI.
Page 366 Section 11 Local Bus State Controller (LBSC) • MPX interface  Address/data multiplexing Connectable areas: 0 to 2 and 4 to 6 Settable bus width: 32 bits • Byte control SRAM interface  SRAM interface with byte control Connectable areas: 1 and 4 Settable bus widths: 32 and 16 bits •...
Page 367: Figure 11.1 Lbsc Block Diagram
Section 11 Local Bus State Controller (LBSC) Bus interface Wait CSnWCR control unit CS0 to CS2 Area CS4 to CS6 CSnBCR control CE2A, CE2B unit A25 to A0 BACK, BS RD/FRAME WE3/IOWR Memory CSnPCR WE2/IORD control WE1, WE0/REG unit D31 to D0 BREQ, IOIS16 MODE5 to MODE3 LBSC...
Page 368: Input/Output Pins
Section 11 Local Bus State Controller (LBSC) 11.2 Input/Output Pins Table 11.1 shows the LBSC pin configuration. Table 11.1 Pin Configuration Pin Name Function Description A25 to A0 Address Bus Output Address output D31 to D0* Data Bus Data input/output Bus Cycle Start Output Signal that indicates the start of a bus cycle.
Page 369 Section 11 Local Bus State Controller (LBSC) Pin Name Function Description IOIS16* 16-Bit I/O Input 16-bit I/O signal when setting PCMCIA interface. Valid only in little endian mode BREQ* Bus Release Input Bus release request signal Request BACK Bus Request Output Bus release acknowledge signal Acknowledge...
Page 370: Area Overview
Section 11 Local Bus State Controller (LBSC) 11.3 Area Overview 11.3.1 Space Divisions The architecture of this LSI provides a 32-bit address space. The virtual address space is divided into five areas (P0 to P4 areas) according to the upper address value. This LSI supports both a 29-bit and a 32-bit physical address space, and the LBSC supports a 29- bit physical address space.
Page 371: Figure 11.2 Correspondence Between Virtual Address Space And External Memory Space Of Lbsc
Section 11 Local Bus State Controller (LBSC) H'0000 0000 H'0000 0000 Area 0 H'0400 0000 Area 1 H'0800 0000 P0 and P0 and Area 2 U0 areas U0 areas H'0C00 0000 (Area 3) H'1000 0000 Area 4 H'1400 0000 Area 5 H'8000 0000 H'1800 0000 P1 area...
Page 372: Table 11.2 Lbsc External Memory Space Map
Section 11 Local Bus State Controller (LBSC) Table 11.2 LBSC External Memory Space Map Specifiable Bus Width External Area addresses Size Connectable Memory (bits) Access Size* H'0000 0000 to 64 Mbytes SRAM 8, 16, 32* 8/16/32 bits and H'03FF FFFF 32 bytes Burst ROM 8, 16, 32*...
Page 373: Figure 11.3 External Memory Space Allocation (29-Bit Address Mode)
Section 11 Local Bus State Controller (LBSC) Specifiable External Bus Width Area addresses Size Connectable Memory (bits) Access Size*   H'1C00 0000 to 64 Mbytes — H'1FFF FFFF Notes: 1. The memory bus width is specified by external pins (MODE3 and MODE4). 2.
Page 374: Memory Bus Width
Section 11 Local Bus State Controller (LBSC) 11.3.2 Memory Bus Width The memory bus width of the LBSC can be set independently for each area. For area 0, a bus width of 8, 16, or 32 bits is set according to the external pin settings at a power-on reset by the PRESET pin.
Page 375: Data Alignment
Section 11 Local Bus State Controller (LBSC) 11.3.3 Data Alignment This LSI supports the big endian and little endian methods of data alignment. The data alignment method is specified using the external pin (MODE5) at a power-on reset. Table 11.4 Correspondence Between External Pin (MODE5) and Endian Mode 5 Endian Big endian...
Page 376: Table 11.6 Pcmcia Support Interface
Section 11 Local Bus State Controller (LBSC) Table 11.6 PCMCIA Support Interface IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name* I/O* Function Name* I/O* Function Pin of this LSI  Ground Ground Data Data Data Data Data Data Data Data...
Page 377 Section 11 Local Bus State Controller (LBSC) IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name* I/O* Function Name* I/O* Function Pin of this LSI Data Data Data Data Data Data IOIS16 IOIS16 Write protect 16-bit I/O port ...
Page 378 Section 11 Local Bus State Controller (LBSC) IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name* I/O* Function Name* I/O* Function Pin of this LSI RESET Reset RESET Reset Output from port WAIT WAIT RDY* Wait request Wait request INPACK Input acknowledge ...
Page 379: Register Descriptions
Section 11 Local Bus State Controller (LBSC) 11.4 Register Descriptions Table 11.7 shows the LBSC register configuration. Table 11.8 shows the register state in each processing mode. Table 11.7 Register Configuration Area 7 Access Register Name Abbrev. P4 Address Address Size* Memory Address Map Select Register MMSELR H'FF40 0020...
Page 380: Table 11.8 Register State In Each Processing Mode
Section 11 Local Bus State Controller (LBSC) Table 11.8 Register State in Each Processing Mode Register Name Abbrev. Power-On Reset Manual Reset Sleep Memory Address Map Select Register MMSELR H'0000 0000 H'0000 0000 Retained Bus Control Register H'x000 0000 Retained Retained CS0 Bus Control Register CS0BCR...
Page 381: Memory Address Map Select Register (Mmselr)
Section 11 Local Bus State Controller (LBSC) 11.4.1 Memory Address Map Select Register (MMSELR) MMSELR is a 32-bit register that selects memory address maps for areas 2 to 5. This register should be accessed at the address H'FF40 0020 in longword. Writing is accepted only when the upper 16-bit data is H'A5A5 to prevent unintentional writing.
Page 382 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 2 to 0 AREASEL DDRIF/PCIC Memory Space Select 000: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the DDRIF space and other areas as the LBSC space 001: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the DDRIF space, area 4 (H'1000 0000 to H'13FF FFFF) as the PCI memory space, and other areas as the LBSC space...
Page 383: Bus Control Register (Bcr)
Section 11 Local Bus State Controller (LBSC) The instruction to modify the value of the MMSELR should be allocated non-cacheable P2 area and an address that will not be affected by an address map change. Write to MMSELR before enabling the Instruction cache, Operand cache, and MMU address translation, and then do not write to it again until after power-on reset or manual reset.
Page 384 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description DPUP Data Pin Pull-Up Resistor Control Specifies the pull-up resistor state of the data pins (D31 to D0). This bit is initialized by a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the pull-up resistor is 0: Cycles in which the pull-up resistors of the data pins (D31 to D0) are turned on are inserted before and...
Page 385 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  19, 18 All 0 Reserved These bits are always read as 0. The write value should always be 0. BREQ Enable BREQEN Indicates whether or not an external bus request can be accepted.
Page 386: Csn Bus Control Register (Csnbcr)
Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 6 to 0 All 0 Asynchronous Input ASYNC[6:0] Enable asynchronous input to the corresponding pins. 0: Input signals to the corresponding pins must be synchronized with CLKOUT 1: Input signals to the corresponding pins can be asynchronous to CLKOUT ASYNC[6]: DREQ3 ASYNC[5]: DREQ2...
Page 387 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 30 to 28 IWW Idle Cycles between Write-Read/Write-Write Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed.
Page 388 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 22 to 20 IWRWS Idle Cycles between Read-Write to Same Space Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed.
Page 389 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IWRRS Idle Cycles between Read-Read to Same Space Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed.
Page 390 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 9, 8 R/W* Bus Width Specify the bus width. Set to 11 for the MPX interface, and set to 10 or 11 for the byte control SRAM interface. In CS0BCR, the external pins (MODE3 and MODE4) are sampled at a power-on reset.
Page 391 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description R/W* MPX Interface Setting Selects the type of MPX interface 0: Interface that is specified by TYPE bits 1: MPX interface selected Note: * The MPX bit in CS0BCR is read-only. 2 to 0 TYPE Memory Type Setting...
Page 392: Csn Wait Control Register (Csnwcr)
Section 11 Local Bus State Controller (LBSC) 11.4.4 CSn Wait Control Register (CSnWCR) CSnWCR (n = 0 to 2, 4 to 6) are 32-bit readable/writable registers that specify the number of wait cycles to be inserted, the pitch of data access for burst memory accesses, and the number of cycles to be inserted for the address setup time to the read/write strobe assertion or for the data hold time from the write strobe negation.
Page 393 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 26 to 24 ADH Address Hold Cycle Specify the number of cycles to be inserted to ensure the address hold time to the CSn negation.
Page 394 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. RD Hold Cycle (RD Negation–CSn Negation Delay 18 to 16 RDH Cycle) Specify the number of cycles to be inserted from RD negation to CSn negation.
Page 395 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. WE Hold Cycle (WE Negation–CSn Negation Delay 10 to 8 Cycle) Specify the number of cycles to be inserted from WE negation to CSn negation.
Page 396 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 3 to 0 IW[3:0] 1111 Insert Wait Cycle Specify the number of wait cycles to be inserted. • When the SRAM interface, byte control SRAM interface, burst ROM interface (first data cycle only), or PCMCIA interface is selected, the following cycles are inserted.
Page 397: Csn Pcmcia Control Register (Csnpcr)
Section 11 Local Bus State Controller (LBSC) 11.4.5 CSn PCMCIA Control Register (CSnPCR) CSnPCR is a 32-bit readable/writable register that specifies the timing for the PCMCIA interface connected to area n (n = 5 or 6), the space property, and the assert/negate timing for the OE (RD) and WE signals.
Page 398 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 26 to 24 SAB Space Property B Specify the space property of PCMCIA connected to second half of area n (n = 5 and 6).
Page 399 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 19 to 16 PCIW 0000 PCMCIA Insert Wait Cycle B Specify the number of wait cycles to be inserted. These bits are valid, when the access area of PCMCIA interface is second half of area n (n = 5 and 6).
Page 400 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description OE/WE Assert Delay A 14 to 12 TEDA These bits set the delay time from address output to OE/WE assertion for the access of first half area of PCMCIA interface (area n, n = 5 and 6).
Page 401 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description OE/WE Negation-Address Delay A 6 to 4 TEHA These bits set the delay time from OE/WE negation to address hold for the access of first half area of PCMCIA interface (area n, n = 5 and 6).
Page 402: Operation
Section 11 Local Bus State Controller (LBSC) 11.5 Operation 11.5.1 Endian/Access Size and Data Alignment This LSI supports both big-endian mode, in which the upper byte in a string of byte data is at address 0, and little-endian mode, in which the lower byte in a string of byte data is at address 0. The mode is specified by the external pin (MODE5 pin) at a power-on reset through the RESET pin.
Page 403: Table 11.9 32-Bit External Device/Big-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.9 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 404: Table 11.11 8-Bit External Device/Big-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.11 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 405: Table 11.12 32-Bit External Device/Little-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.12 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 406: Table 11.14 8-Bit External Device/Little-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.14 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 407: Areas
Section 11 Local Bus State Controller (LBSC) 11.5.2 Areas Area 0 For area 0, physical address bits 28 to 26 are 000. The interfaces that can be set for this area are the SRAM, burst ROM and MPX interfaces. A bus width of 8, 16, or 32 bits is selectable with external pins MODE4 and MODE3 at a power- on reset.
Page 408 Section 11 Local Bus State Controller (LBSC) In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. For the number of bus cycles, 0 to 25 wait cycles inserted by CS1WCR can be selected. When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable with bits BW2 to BW0 in CS1BCR.
Page 409 Section 11 Local Bus State Controller (LBSC) Area 3 For area 3, physical address bits 28 to 26 are 011. This area is used only for the DDR-SDRAM interface. For details, see section 12, DDR-SDRAM Interface (DDRIF). Area 4 For area 4, physical address bits 28 to 26 are 100. The interfaces that can be set for this area are the SRAM, burst ROM, MPX , byte control SRAM, DDR-SDRAM and PCI local bus interfaces.
Page 410 Section 11 Local Bus State Controller (LBSC) When the SRAM or burst ROM interface is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ in CS5BCR. When the MPX interface is used, a bus width of 32 bits should be selected through bits SZ in CS5BCR.
Page 411: Sram Interface
Section 11 Local Bus State Controller (LBSC) When area 6 is accessed, the CS6 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. While the PCMCIA interface is used, the CE1B and CE2B signals, the RD signal (which can be used as OE), and the WE0, WE1, WE2, and WE3 signals (which can be used as REG, WE, IORD, and IOWR, respectively) are asserted.
Page 412: Figure 11.4 Basic Timing Of Sram Interface
Section 11 Local Bus State Controller (LBSC) accesses are performed in wraparound method according to the set bus width. The bus is not released during this transfer. CLKOUT A25 to A0 D31 to D0 (read) D31 to D0 (write) DACK Figure 11.4 Basic Timing of SRAM Interface Rev.1.00 Dec.
Page 413: Figure 11.5 Example Of 32-Bit Data-Width Sram Connection
Section 11 Local Bus State Controller (LBSC) Figures 11.5 to 11.7 show examples of the connection to SRAM with data width of 32, 16, and 8 bits. 128 K × 8-bit SH7780 SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 11.5 Example of 32-Bit Data-Width SRAM Connection Rev.1.00 Dec.
Page 414: Figure 11.6 Example Of 16-Bit Data-Width Sram Connection
Section 11 Local Bus State Controller (LBSC) 128 K × 8-bit SH7780 SRAM I/O7 I/O0 I/O7 I/O0 Figure 11.6 Example of 16-Bit Data-Width SRAM Connection Rev.1.00 Dec. 13, 2005 Page 364 of 1286 REJ09B0158-0100...
Page 415: Figure 11.7 Example Of 8-Bit Data-Width Sram Connection
Section 11 Local Bus State Controller (LBSC) 128 K × 8-bit SH7780 SRAM I/O7 I/O0 Figure 11.7 Example of 8-Bit Data-Width SRAM Connection Rev.1.00 Dec. 13, 2005 Page 365 of 1286 REJ09B0158-0100...
Page 416: Figure 11.8 Sram Interface Wait Timing (Software Wait Only)
Section 11 Local Bus State Controller (LBSC) Wait Cycle Control Wait cycle insertion for the SRAM interface can be controlled by CSnWCR. If the IW bits for each area in CSnWCR is not 0, a software wait is inserted in accordance with the wait-control bits. For details, see section 11.4.4, CSn Wait Control Register (CSnWCR).
Page 417: Figure 11.9 Sram Interface Wait Timing (Wait Cycle Insertion By Rdy Signal, Rdy Signal Is Synchronous Input)
Section 11 Local Bus State Controller (LBSC) When software wait insertion is specified by CSnWCR, the external wait input signal (RDY) is also sampled. The RDY signal sampling timing is shown in figure 11.9, where a single wait cycle is specified as a software wait. The RDY signal is sampled at the transition from the Tw state to the T2 state.
Page 418 Section 11 Local Bus State Controller (LBSC) Read-Strobe Negate Timing When the SRAM interface is used, the negation timing of the strobe signal during a read operation can be specified through the RDSPL bit in CSnBCR. For details of settings, see section 11.4.3, CSn Bus Control Register (CSnBCR).
Page 419: Figure 11.10 Sram Interface Wait Timing (Read-Strobe Negate Timing Setting)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 (read) D31 to D0 (read) TS1: TH1,TH2: CSn assertion-RD assertion RD Negation-CSn Negation delay cycle (RD Setup cycle) delay cycle (RD Hold cycle) CSnWCR.RDS (0 to 7 cycles) CSnWCR.RDH (0 to 7 cycles) TAH1: TAS1: Address Hold cycle...
Page 420: Burst Rom (Clock Asynchronous) Interface
Section 11 Local Bus State Controller (LBSC) 11.5.4 Burst ROM (Clock Asynchronous) Interface Setting the TYPE bit in CSnBCR (n = 0 to 2 and 4 to 6) to 010 allows a burst ROM (clock asynchronous memory) to be connected to areas 0 to 2 and 4 to 6. The burst ROM interface provides high-speed access to ROM that has a burst access function.
Page 421: Figure 11.11 Burst Rom Basic Timing
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A5 A4 to A0 D31 to D0 (read) Figure 11.11 Burst ROM Basic Timing CLKOUT A25 to A5 A4 to A0 D31 to D0 (read) Figure 11.12 Burst ROM Wait Timing Rev.1.00 Dec.
Page 422: Pcmcia Interface
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A5 A4 to A0 D31 to D0 (read) DACKn Note: When CSnBCR RDSPL is set to 1. Figure 11.13 Burst ROM Wait Timing 11.5.5 PCMCIA Interface Areas 5 and 6 can be set to the IC memory card interface or I/O card interface, which is stipulated in JEIDA specification version 4.2 (PCMCIA 2.1), by setting the TYPE bits in CS5BCR and CS6BCR.
Page 423 Section 11 Local Bus State Controller (LBSC) Bits PCWA/B1 and PCWA/B0 can be used to set the number of wait cycles to be inserted in a low-speed bus cycle as 0, 15, 30, or 50. This value is added to the number of inserted wait cycles specified by IW bit in CSnWCR or PCIW bit in CSnPCR.
Page 424: Figure 11.14 Cexx And Dack Output Of Ata Complement Mode In Dma Transfer
Section 11 Local Bus State Controller (LBSC) (a) IO Card Interface DACKBST Invalid CExx DACK (b) ATA Complement Mode DACKBST Valid CExx DACK Note: Number of DMA transfer times: 4, DMA transfer size: word (16-bit) xx = 1A, 1B, 2A, 2B Figure 11.14 CExx and DACK Output of ATA Complement Mode in DMA Transfer Figure 11.15 shows an example of PCMCIA card connection to this LSI.
Page 425: Table 11.15 Relationship Between Address And Ce When Using Pcmcia Interface
Section 11 Local Bus State Controller (LBSC) Table 11.15 Relationship between Address and CE When Using PCMCIA Interface Read/ Access Odd/ IOIS16 Bus (Bits) Write (bits)* Even Access D15 to D8 D7 to D0 ×  Read Even Invalid Read data ×...
Page 426 Section 11 Local Bus State Controller (LBSC) Read/ Access Odd/ IOIS16 Bus (Bits) Write (bits)* Even Access D15 to D8 D7 to D0  Dynamic Write Even Invalid Write data First Invalid Write data Sizing* Second Invalid Write data Even First Upper write data Lower write data Even...
Page 427: Figure 11.15 Example Of Pcmcia Interface
Section 11 Local Bus State Controller (LBSC) A25 to A0 A25 to A0 D15 to D0 D7 to D0 CE1B/(CS6) D15 to D0 CE1A/(CS5) CE2B PC card CE2A D15 to D8 (Memory, I/O) SH7780 WE/PGM IORD (IORD) (IOWR) IOWR WAIT IOIS16 (IOIS16) Card...
Page 428: Figure 11.16 Basic Timing For Pcmcia Memory Card Interface
Section 11 Local Bus State Controller (LBSC) Memory Card Interface Basic Timing Figure 11.16 shows the basic timing for the PCMCIA memory card interface, and figure 11.17 shows the wait timing for the PCMCIA memory card interface. pcm1 pcm2 CLKOUT A25 to A0 CExx REG (WE0)
Page 429: Figure 11.17 Wait Timing For Pcmcia Memory Card Interface
Section 11 Local Bus State Controller (LBSC) pcm0 pcm0w pcm1 pcm1w pcm1we pcm2 pcm2w CLKOUT A25 to A0 CExx REG (WE0) (read) D15 to D0 (read) (write) D15 to D0 (write) DACK Figure 11.17 Wait Timing for PCMCIA Memory Card Interface Rev.1.00 Dec.
Page 430: Figure 11.18 Basic Timing For Pcmcia I/O Card Interface
Section 11 Local Bus State Controller (LBSC) I/O Card Interface Timing Figures 11.18 and 11.19 show the timing for the PCMCIA I/O card interface. When accessing a PCMCIA card via the I/O card interface, it is possible to perform dynamic sizing of the I/O bus width using the IOIS16 pin.
Page 431: Figure 11.19 Wait Timing For Pcmcia I/O Card Interface
Section 11 Local Bus State Controller (LBSC) pci0 pci0w pci1 pci1w pci1we pci2 pci2w CLKOUT A25 to A0 CExx REG (WE0) IORD (read) D15–D0 (read) IOWR (write) D15 to D0 (write) IOIS16 DACK Figure 11.19 Wait Timing for PCMCIA I/O Card Interface Rev.1.00 Dec.
Page 432: Figure 11.20 Dynamic Bus Sizing Timing For Pcmcia I/O Card Interface
Section 11 Local Bus State Controller (LBSC) pci2 pci2w pci0 pci1w pci2 pci2w pci0 pci1w CLKOUT A25 to A1 CExx REG (WE0) IORD (WE2) (read) D15 to D0 (read) IOWR (WE3) (write) D15 to D0 (write) IOIS16 DACK Figure 11.20 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.1.00 Dec.
Page 433: Mpx Interface
Section 11 Local Bus State Controller (LBSC) 11.5.6 MPX Interface When both the MODE4 and MODE3 pins are set to 0 at a power-on reset by the PRESET pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1, 2, and 4 to 6 by the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR.
Page 434: Figure 11.21 Example Of 32-Bit Data Width Mpx Connection
Section 11 Local Bus State Controller (LBSC) SH7780 MPX device CLKOUT RD/FRAME FRAME D31 to D0 I/O31 to I/O0 Figure 11.21 Example of 32-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1, 2, and 4 to 6, a bus size of 32 bits should be specified by CSnBCR.
Page 435: Figure 11.23 Mpx Interface Timing 2 (Single Read, Iw = 0, One External Wait Inserted)
Section 11 Local Bus State Controller (LBSC) md1w md1we CLKOUT RD/FRAME D31 to D0 DACK Figure 11.23 MPX Interface Timing 2 (Single Read, IW = 0, One External Wait Inserted) CLKOUT RD/FRAME D31 to D0 DACK Figure 11.24 MPX Interface Timing 3 (Single Write Cycle, IW = 0, No External Wait) Rev.1.00 Dec.
Page 436: Figure 11.25 Mpx Interface Timing
Section 11 Local Bus State Controller (LBSC) md1w md1we CLKOUT RD/FRAME D31 to D0 DACK Figure 11.25 MPX Interface Timing 4 (Single Write Cycle, IW = 1, One External Wait Inserted) T m1 T md1w T md1 T md2 T md3 T md4 T md5 T md6...
Page 437: Figure 11.27 Mpx Interface Timing 6
Section 11 Local Bus State Controller (LBSC) T m1 T md1w T md1 T md2we T md2 T md3 T md7 T md8we T md8 CLKOUT FRAME D31 to D0 DACK Figure 11.27 MPX Interface Timing 6 (Burst Read Cycle, IW = 0, External Wait Control, 32-Byte Data Transfer) T m1 T md1 T md2...
Page 438: Figure 11.29 Mpx Interface Timing 8
Section 11 Local Bus State Controller (LBSC) T m1 T md1w T md1 T md2we T md2 T md3 T md7 T md8we T md8 CLKOUT FRAME D31 to D0 DACK Figure 11.29 MPX Interface Timing 8 (Burst Write Cycle, IW = 1, External Wait Control, 32-Byte Data Transfer) Rev.1.00 Dec.
Page 439: Byte Control Sram Interface
Section 11 Local Bus State Controller (LBSC) 11.5.7 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte-select strobe (WE) in both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM having an upper byte select strobe and lower select strobe functions, such as UB and LB.
Page 440: Figure 11.31 Byte-Control Sram Basic Read Cycle (No Wait)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 D31 to D0 (read) DACK Figure 11.31 Byte-Control SRAM Basic Read Cycle (No Wait) Rev.1.00 Dec. 13, 2005 Page 390 of 1286 REJ09B0158-0100...
Page 441: Figure 11.32 Byte-Control Sram Basic Read Cycle (One Internal Wait Cycle)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 D31 to D0 (read) DACK Figure 11.32 Byte-Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev.1.00 Dec. 13, 2005 Page 391 of 1286 REJ09B0158-0100...
Page 442: Figure 11.33 Byte-Control Sram Basic Read Cycle (One Internal Wait + One External Wait)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 D31 to D0 (read) DACK Figure 11.33 Byte-Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev.1.00 Dec. 13, 2005 Page 392 of 1286 REJ09B0158-0100...
Page 443: Wait Cycles Between Accesses
Section 11 Local Bus State Controller (LBSC) 11.5.8 Wait Cycles between Accesses A problem associated with higher operating frequencies for external memory buses is that the data buffer turn-off after completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and resulting in lower reliability or malfunctions.
Page 444: Figure 11.34 Wait Cycles Between Access Cycles
Section 11 Local Bus State Controller (LBSC) wait wait CLKOUT A25 to A0 D31 to D0 IWRRD IWRWS Area m space read Area n space read Area n space write Area m - n access wait specification Area n inter-access wait specification m ≠...
Page 445: Bus Arbitration
Section 11 Local Bus State Controller (LBSC) 11.5.9 Bus Arbitration The LBSC is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. In normal operation, the bus is held by the LBSC (bus master), and is released to another device in response to a bus request.
Page 446: Figure 11.35 Arbitration Sequence
Section 11 Local Bus State Controller (LBSC) CLKOUT BREQ Asserted for Negated least 2 cycles within 2 cycles BACK A25 to A0 D31 to D0 (write) Master access Slave access Master access Figure 11.35 Arbitration Sequence Rev.1.00 Dec. 13, 2005 Page 396 of 1286 REJ09B0158-0100...
Page 447: 11.5.10 Bus Release And Acquire Sequence
Section 11 Local Bus State Controller (LBSC) 11.5.10 Bus Release and Acquire Sequence The LBSC holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the LBSC releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends.
Page 448: Figure 11.36 Example Of The Bus Release Restraint By The Dmac Chcr Lckn Bit
Section 11 Local Bus State Controller (LBSC) If a DMA transfer is executed for the space that the source address is in the LBSC space and the destination address is out of the LBSC space and the LCKN bit in CHCR is cleared to 0, the bus is not released after the DMA write access is ended even if the bus release signal (BREQ) is asserted.
Page 449: 11.5.11 Cooperation Between Master And Slave
Section 11 Local Bus State Controller (LBSC) 11.5.11 Cooperation between Master and Slave To enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. When designing an application system that includes the SH7780, all control, including initialization, and low power consumption control, are supposed to be carried out by the SH7780.
Page 450 Section 11 Local Bus State Controller (LBSC) Rev.1.00 Dec. 13, 2005 Page 400 of 1286 REJ09B0158-0100...
Page 451: Section 12 Ddr-Sdram Interface (Ddrif)
Section 12 DDR-SDRAM Interface (DDRIF) Section 12 DDR-SDRAM Interface (DDRIF) The DDR-SDRAM interface (DDRIF) is an interface for the control of DDR-SDRAM. The DDRIF supports DDR320- and DDR266-SDRAM. 12.1 Features • The data bus width of the DDRIF is 32 bits •...
Page 452: Figure 12.1 Ddrif Block Diagram
Section 12 DDR-SDRAM Interface (DDRIF) Figure 12.1 shows a block diagram of the DDRIF. DDRIF (DDR-SDRAM Interface) SuperHyway bus interface DDR controller DDR-VREF Synchronizing for BKPRST internal process Control register synchronizer SuperHyway SuperHyway Command/write data output request request and control register MRAS receiver buffer...
Page 453: Input/Output Pins
Section 12 DDR-SDRAM Interface (DDRIF) 12.2 Input/Output Pins Table 12.1 shows the DDRIF pin configuration. For details on connection with the DDR-SDRAM, see the DDR-SDRAM pin information. Table 12.1 Pin Configuration Pin Name Function Description MCLK DDR-SDRAM clock Output Clock output for DDR-SDRAM MCLK DDR-SDRAM clock Output...
Page 454: Address Space, Bus Width, And Data Alignment
Section 12 DDR-SDRAM Interface (DDRIF) 12.3 Address Space, Bus Width, and Data Alignment 12.3.1 Address Space of the DDRIF This LSI supports both 29-bit and 32-bit physical address spaces (29-bit address mode and 32-bit address extended mode), and the address space is selectable from among five kinds of map by setting Memory Address Map Select Register (MMSELR) of the LBSC.
Page 455: Memory Data Bus Width
Section 12 DDR-SDRAM Interface (DDRIF) MMSELR. AREASEL[2:0]* B'000 B'001 B'010 B'011 B'100 H'0000 0000 Area 0 (LBSC) LBSC LBSC LBSC LBSC LBSC H'0400 0000 Area 1 (LBSC) LBSC LBSC LBSC LBSC LBSC H'0800 0000 Area 2 (LBSC/DDRIF) LBSC LBSC DDRIF-0 DDRIF-0 DDRIF-0 29-bit physical...
Page 456: Data Alignment
Section 12 DDR-SDRAM Interface (DDRIF) 12.3.3 Data Alignment The DDRIF supports both big endian mode, where the address of the highest order byte is 0, and little endian mode, where the address of the lowest order byte is 0. These modes can be switched by changing the level on an external pin (MODE5) and then generating a power-on reset.
Page 457 Section 12 DDR-SDRAM Interface (DDRIF) MD31 to MD24 MD23 to MD16 MD15 to MD8 MD7 to MD0 32-byte access at address 0 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 (first round: from address 4) 32-byte access at address 0 Bit 31 to 24 Bit 23 to 16...
Page 458: Table 12.3 Access And Data Alignment In Big Endian Mode
Section 12 DDR-SDRAM Interface (DDRIF) Table 12.3 Access and Data Alignment in Big Endian Mode MD31 to MD24 MD23 to MD16 MD15 to MD8 MD7 to MD0 Byte access at address 0 Bit 7 to 0 Byte access at address 1 Bit 7 to 0 Byte access at address 2 Bit 7 to 0...
Page 459: Figure 12.3 Data Alignment In Ddr-Sdram And Ddrif
Section 12 DDR-SDRAM Interface (DDRIF) MD31 to MD24 MD23 to MD16 MD15 to MD8 MD7 to MD0 32-byte access at address 0 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 (first round: from address 0) 32-byte access at address 0 Bit 31 to 24 Bit 23 to 16...
Page 460: Register Descriptions
Section 12 DDR-SDRAM Interface (DDRIF) 12.4 Register Descriptions Table 12.4 shows the DDRIF register configuration. Table 12.5 shows the register states in each processing mode. These registers should only be set while access to the DDR-SDRAM from a module is not in progress.
Page 461: Table 12.5 Register States In Each Operating Mode
Section 12 DDR-SDRAM Interface (DDRIF) Table 12.5 Register States in Each Operating Mode Register Name Abbreviation Power-On Reset Manual Reset Sleep Memory interface mode register MIM H'0000 0000 H'0000 0000 Retained 0C34 xx00* 0C34 xx00* DDR-SDRAM control register H'0000 0000 H'0000 0000 Retained 0000 0000...
Page 462: Memory Interface Mode Register (Mim)
Section 12 DDR-SDRAM Interface (DDRIF) 12.4.1 Memory Interface Mode Register (MIM) Bit:                 Initial value: R/W: Bit:         ...
Page 463 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. PCKE Power Down This bit controls a low power consumption mode in which the CKE pin is set low to place the DDR-SDRAM in “power-down mode”...
Page 464 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 28 to 16 DRI H'0C34 DRAM Refresh Interval When refreshing is valid (the DRE bit in MIM is set to 1), these bits specify the maximum refresh interval (auto-refresh). The unit for counting is the cycle of the MCLK.
Page 465 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description ENDIAN Undefined* R Endian Identifier Indicates whether big endian or little endian mode is selected for the external data bus. 0: Little endian mode 1: Big endian mode Bus Width Specifies the DDR-SDRAM bus width.
Page 466: Sdram Control Register (Scr)
Section 12 DDR-SDRAM Interface (DDRIF) 12.4.2 SDRAM Control Register (SCR) Bit:                 Initial value: R/W: Bit:          ...
Page 467 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description  63 to 3 All 0 Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 SDRAM Mode Select These bits initialize the DDR-SDRAM when power is supplied and after release of the reset signal.
Page 468: Sdram Timing Register (Str)
Section 12 DDR-SDRAM Interface (DDRIF) 12.4.3 SDRAM Timing Register (STR) STR specifies various timing parameters for the DDR-SDRAM. Bit:                 Initial value: R/W: Bit:  ...
Page 469 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 17, 16 Minimum Number of Cycles from Read Command to Write Command These bits specify the minimum number of cycles required by the SRAM from the issuing of a READ command to the issuing of a subsequent WRITE command.
Page 470 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 10 to 8 SRAS Minimum Number of Cycles between ACT and PRE Commands These bits specify the minimum number of cycles until a PRE command is issued after an ACT command has been issued (the corresponding time is tRAS) for the same bank.
Page 471: Sdram Row Attribute Register (Sdr)
Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description SRCD Numbers of Cycles between RAS and CAS Commands Specifies the number of cycles from an RAS (ACT) command to a subsequent CAS (READ/READA, WRITE/WRITEA) command (the corresponding time is tRCD).
Page 472: Sdram Mode Register (Sdmr)
Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 63 to 12  All 0 Reserved These bits are always read as 0. The write value should always be 0. 11 to 8 SPLIT 0001 DDR-SDRAM Memory Configuration These bits specify the row/column configuration of the DDR-SDRAM.
Page 473: Figure 12.4 Relationship Between Write Values In Sdmr And Output Signals To Memory Pins
Section 12 DDR-SDRAM Interface (DDRIF) Address Bit Correspondence BA1 and MA13 to MA9 to MA10 Bits 14 Bits 18 to Bits 12 to and 13 Figure 12.4 shows the relationship between write values in SDMR and output signals to the memory pins.
Page 474: Ddr-Sdram Back-Up Register (Dbk)
Section 12 DDR-SDRAM Interface (DDRIF) To output the above control signals, write access to address H'FEC0 0308 in SDMR is made in longwords. Then the above control signals are output to the SDRAM pins. Write data to SDMR is Don't care. 12.4.6 DDR-SDRAM Back-up Register (DBK) This register indicates the DDR-SDRAM back-up status.
Page 475: Operation
Section 12 DDR-SDRAM Interface (DDRIF) 12.5 Operation 12.5.1 DDR-SDRAM Access The DDR-SDRAM is accessed with a burst length of 2. Read or write commands for the same page can be issued consecutively and the data is read or written continuously. 12.5.2 DDR-SDRAM Initialization Sequence Since the internal state of the SDRAM is undefined immediately after power is initially supplied,...
Page 476: Supported Sdram Commands
Section 12 DDR-SDRAM Interface (DDRIF) 12. Use SDMR to issue the MRS command, release the DLL reset (MA8 = low), and determine the operating mode. In this case, use the settings for burst length, etc. that were specified in step 10. 13.
Page 477: Sdram Access Mode
Section 12 DDR-SDRAM Interface (DDRIF) Valid data The DESELECT command in table 12.6 is automatically issued whenever the SDRAM is not being accessed by any module. The DESELECT command therefore cannot be explicitly issued by the user. 12.5.4 SDRAM Access Mode The DDRIF supports the following two SDRAM access modes.
Page 478 Section 12 DDR-SDRAM Interface (DDRIF) 3. The STR settings do not establish a relationship between the timing of the PREALL and REFA commands that are issued by using SCR. A period of waiting that is suitable for the memory unit must be inserted. 4.
Page 479: Address Multiplexing
Section 12 DDR-SDRAM Interface (DDRIF) 12.5.6 Address Multiplexing Address multiplexing is performed in line with the settings of the SPLIT bits in SDR so that connecting the SDRAM does not require an external address-multiplexing circuit. Table 12.7 shows the relationship between the settings of SPLIT bits and address multiplexing. The number of ROW or COL line is the addresses (bit) that are output to the address pins according to the setting of the SPLIT bits.
Page 480: Ddr-Sdram Basic Timing
Section 12 DDR-SDRAM Interface (DDRIF) 12.6 DDR-SDRAM Basic Timing Figures 12.5 to 12.14 show basic timing of the DDRIF. In each timing chart, the DDR-SRAM has been idle at T0. The settings in the SDRAM timing register (STR) must set up timing that is within the specifications of the DDR-SDRAM.
Page 481: Figure 12.6 Ddrif Basic Timing (1-/2-/4-/8-Byte Single Burst Write Without Auto Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command WRITE (SRCD = 1) MA9-0 Col 0 MA13-11 MA10 Bank Bank Bank BA1-0 MRAS MCAS Hi-Z MDQS Hi-Z D0 D1 MDQM Figure 12.6 DDRIF Basic Timing (1-/2-/4-/8-Byte Single Burst Write without Auto Precharge) Rev.1.00 Dec.
Page 482: Figure 12.7 Ddrif Basic Timing (1-/2-/4-/8-Byte Single Burst Read With Auto Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command READA (SRC = 011) (SRCD = 1) (SRP = 0) (SRAS = 000) MA9-0 Col 0 MA13-11 MA10 BA1-0 Bank Bank Bank MRAS MCAS Hi-Z MDQS CL = 2.5 Hi-Z D0 D1 MDQM Figure 12.7 DDRIF Basic Timing (1-/2-/4-/8-Byte Single Burst Read with Auto Precharge)
Page 483: Figure 12.8 Ddrif Basic Timing (1-/2-/4-/8-Byte Single Burst Write With Auto Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command WRITEA (SRC = 101) (SRCD = 1) (SWR = 0) (SRP = 0) (SRAS = 010) MA9-0 Col 0 MA13-11 MA10 BA1-0 Bank Bank Bank MRAS MCAS Hi-Z MDQS Hi-Z D0 D1 MDQM Figure 12.8 DDRIF Basic Timing (1-/2-/4-/8-Byte Single Burst Write with Auto Precharge)
Page 484: Figure 12.9 Ddrif Basic Timing (4 Burst Read: 32-Byte Without Auto Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command READ READ READ READ (SRCD = 1) MA9-0 Col 0 Col 2 Col 4 Col 6 MA13-11 MA10 BA1-0 Bank Bank Bank Bank Bank Bank MRAS MCAS Hi-Z MDQS Hi-Z CL = 2.5 D0 D1 D2 D3 D4 D5 D6 D7 MDQM Figure 12.9 DDRIF Basic Timing...
Page 485: Figure 12.10 Ddrif Basic Timing (4 Burst Write: 32-Byte Without Auto Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command WRITE WRITE WRITE WRITE (SRCD = 1) MA9-0 Col 0 Col 2 Col 4 Col 6 MA13-11 MA10 Bank Bank Bank Bank Bank Bank BA1-0 MRAS MCAS Hi-Z MDQS Hi-Z D1 D2 D3 D4 D5 D6 D7 MDQM Figure 12.10 DDRIF Basic Timing (4 Burst Write: 32-byte without Auto Precharge)
Page 486: Figure 12.11 Ddrif Basic Timing (From Precharging All Banks To Bank Activation)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command PREALL (SRP = 1) MA9-0 MA13-11 MA10 BA1-0 Bank MRAS MCAS Hi-Z MDQS Hi-Z MDQM Figure 12.11 DDRIF Basic Timing (from Precharging All Banks to Bank Activation) Rev.1.00 Dec. 13, 2005 Page 436 of 1286 REJ09B0158-0100...
Page 487: Figure 12.12 Ddrif Basic Timing (Mode Register Setting)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command MA9-0 MA13-11 MA10 BA1-0 MRAS MCAS Hi-Z MDQS Hi-Z MDQM Notes: 1. Operating mode or other setting 2. Mode register setting: BA1 = Low, BA0 = Low Extended mode register setting: BA1 = Low, BA0 = High Figure 12.12 DDRIF Basic Timing (Mode Register Setting) Rev.1.00 Dec.
Page 488: Figure 12.13 Ddrif Basic Timing (Enter Auto-Refresh/Exit To Bank Activation)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command REFA REFA = 11 to 15 cycles = 11 to 15 cycles MA9-0 MA13-11 MA10 BA1-0 Bank MRAS MCAS Auto refresh Figure 12.13 DDRIF Basic Timing (Enter Auto-Refresh/Exit to Bank Activation) Rev.1.00 Dec. 13, 2005 Page 438 of 1286 REJ09B0158-0100...
Page 489: Figure 12.14 Ddrif Basic Timing (Enter Self-Refresh/Exit To Command Issuing)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command REFS REFSX Command XSNR XSRD MA9-0 MA13-11 MA10 BA1-0 MRAS MCAS Self refresh Notes: 1. The time where the CKE signal rises should satisfy the refresh interval conditions of the SDRAM in use. 2.
Page 490: Usage Notes
Section 12 DDR-SDRAM Interface (DDRIF) 12.7 Usage Notes 12.7.1 Operating Frequency The DDRIF supports ratios of 5:4 (DDR320) and 1:1 (DDR266) between the frequencies of the SuperHyway clock (SHck) and DDR clock (DDRck). For details, see section 15, Clock Pulse Generator (CPG).
Page 491: Setting Auto-Refresh Interval
Section 12 DDR-SDRAM Interface (DDRIF) 12.7.5 Setting Auto-Refresh Interval The auto-refresh interval is specified by the DRI bits in MIM. If the DRE bit is set to 1 at the same time as the DRI bits are set, the time until the first auto-refresh is that selected by the value of the DRI bits before the new setting was made.
Page 492 Section 12 DDR-SDRAM Interface (DDRIF) Rev.1.00 Dec. 13, 2005 Page 442 of 1286 REJ09B0158-0100...
Page 493: Section 13 Pci Controller (Pcic)
Section 13 PCI Controller (PCIC) Section 13 PCI Controller (PCIC) The PCI controller (PCIC) controls the PCI bus for data transfers between memory connected to an external bus and a PCI device connected to the PCI bus. The ability to connect PCI devices facilitates the design of systems using the PCI bus and enables more compact systems capable of faster data transfer.
Page 494 Section 13 PCI Controller (PCIC) • Exclusive access (target only)  Once locked, only accessible from the device that accessed the LOCK signal  The SuperHyway bus in not locked during lock transfer • Can support cache coherency between a device connected to the PCI bus and system memory (PCI target) although device performance may become suboptimal •...
Page 495: Figure 13.1 Pcic Block Diagram
Section 13 PCI Controller (PCIC) Figure 13.1 is a block diagram of the PCIC. PCIRESET PCICLK (PCI bus clock) PCI local bus PCI standard signal PCIC SuperHyway bus PCI bus Interface MODE6 Interface (PCI bus access control) Host/normal SuperHyway bus Data FIFO Target control 32-Byte ×...
Page 496: Input/Output Pins
Section 13 PCI Controller (PCIC) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the PCIC. Table 13.1 Input/Output Pins PCI standard Pin Name signal name Description AD31 to AD0* AD[31:0] PCI Address/Data Bus (TRI) Address and data buses are multiplexed. Each bus transaction consists of an address phase followed by one or more data phases.
Page 497 Section 13 PCI Controller (PCIC) PCI standard Pin Name signal name Description IDSEL IDSEL Input PCI Configuration Device Select This signal is input to the PCI device to select configuration cycles (only for normal mode). DEVSEL DEVSEL PCI Device Select (STRI) Indicates the device driving this signal has decoded its address as the target.
Page 498 Section 13 PCI Controller (PCIC) [Legend] TRI: Tri-state STRI: Sustained tri-state O/D: Open Drain Notes: 1. These pins are multiplexed with the GPIO pins (port A to D). 2. This pin is multiplexed with the SCIF channel 0 and GPIO pins. 3.
Page 499: Register Descriptions
Section 13 PCI Controller (PCIC) 13.3 Register Descriptions Table 13.2 shows the PCIC register configuration. Table 13.3 shows the register states in each operating mode. The PCI configuration register address and its offset are used for little endian operation. Table 13.2 List of PCIC Registers PCI* Access Name...
Page 500 Section 13 PCI Controller (PCIC) PCI* Access Name Abbreviation P4 address Area 7 address Size* PCI minimum grant register PCIMINGNT H'FE04 003E H'1E04 003E PCI maximum latency register PCIMAXLAT H'FE04 003F H'1E04 003F PCI capability ID register PCICID H'FE04 0040 H'1E04 0040 PCI next item pointer register PCINIP...
Page 501 Section 13 PCI Controller (PCIC) PCI* Access Name Abbreviation P4 address Area 7 address Size* PCI memory bank register 0 PCIMBR0 — H'FE04 01E0 H'1E04 01E0 PCI memory bank mask register 0 PCIMBMR0 — H'FE04 01E4 H'1E04 01E4 PCI memory bank register 1 PCIMBR1 —...
Page 502: Table 13.3 Register States In Each Operating Mode
Section 13 PCI Controller (PCIC) Table 13.3 Register States in Each Operating Mode Name Abbreviation Power-On Reset Manual Reset Sleep Mode Control register space PCIC enable control register PCIECR H'0000 0000 Retained Retained PCI configuration register space PCI vendor ID register PCIVID H'1912 Retained...
Page 503 Section 13 PCI Controller (PCIC) Name Abbreviation Power-On Reset Manual Reset Sleep Mode PCI power management capability PCIPMC H'000A Retained Retained register PCI power management PCIPMCSR H'0000 Retained Retained control/status register PCI PMCSR bridge support H'00 Retained Retained PCIPMCSR extension register PCI power consumption/dissipation PCIPCDD H'00...
Page 504 Section 13 PCI Controller (PCIC) Name Abbreviation Power-On Reset Manual Reset Sleep Mode PCI memory bank register 2 PCIMBR2 H'0000 0000 Retained Retained PCI memory bank mask register 2 PCIMBMR2 H'0000 0000 Retained Retained PCI I/O bank register PCIIOBR H'0000 0000 Retained Retained PCI I/O bank master register...
Page 505: Pcic Enable Control Register (Pciecr)
Section 13 PCI Controller (PCIC) 13.3.1 PCIC Enable Control Register (PCIECR) Bit:                 Initial value: R/W: Bit:         ...
Page 506: Configuration Registers
PCI Vender ID PCI: R Indicates the PCI device manufacture identifier (vender ID) that is allocated by PCI-SIG. Renesas Technology’s vendor ID is H'1912. PCI Device ID Register (PCIDID) This register uniquely identifies this LSI amongst PCI devices manufactured by the vendor.
Page 507 Section 13 PCI Controller (PCIC) PCI Command Register (PCICMD) The PCI command register provides coarse control over a device's ability to generate and respond to PCI cycles. When 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses except configuration accesses.
Page 508 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/W Parity Error PCI: R/W Controls the device's response when the PCIC detects a parity error or receives a parity error. When this bit is set to 1, the PERR signal is asserted. 0: No response parity error 1: Response parity error VGAPS...
Page 509 Section 13 PCI Controller (PCIC) PCI Status Register (PCISTATUS) This status register is used to record status information for PCI bus related events. The definition of each of the bits is given in the table below. A device may not need to implement all the bits, depending on device functionality.
Page 510 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/WC Master Abort Receive Status PCI: R/WC Indicates that the PCIC has terminated a transaction with a master abort when the PCIC is a master. 0: PCIC has not terminated a transaction with a master abort 1: PCIC has terminated a transaction with a master abort...
Page 511 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description FBBC SH: R Fast Back-to-Back Status PCI: R Indicates whether or not the PCIC is capable of accepting fast back-to-back transactions when the transactions are not to the same agent if the PCIC functions as a target.
Page 512 Section 13 PCI Controller (PCIC) PCI Revision ID Register (PCIRID) This register specifies a device specific revision identifier. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 H'00 SH: R Revision ID PCI: R Indicates the PCIC revision.The initial value is H'00.RID value varies according to the logic version of the PCIC and it may be changed in the future.
Page 513 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description  6 to 4 All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R/W PCI Programmable Indicator (Secondary) PCI: R When the CFINIT bit in PCICR is 0, this bit is writable.
Page 514 Section 13 PCI Controller (PCIC) PCI Sub Class Code Register (PCISUB) This register identifies the sub class code. For details of the class code, refer to “PCI Local Bus Specification Revision 2.2 Appendix D.” Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value...
Page 515 Section 13 PCI Controller (PCIC) PCI Cacheline Size Register (PCICLS) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 H'20 SH: R Cache Line Size: Not supported PCI: R A memory target does not support a cache. SDON and SBO are ignored.
Page 516 Section 13 PCI Controller (PCIC) (11) PCI Header Type Register (PCIHDR) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description SH: R Multiple Function Enable PCI: R 0: Single function 1: Multiple (from two to eight) functions (not supported) 6 to 0 H'00...
Page 517 Section 13 PCI Controller (PCIC) (13) PCI I/O Base Address Register (PCIIBAR) This register packages the I/O space base address register of the PCI configuration register that is prescribed with PCI local bus specification. Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: IOB (upper) Initial value:...
Page 518 Section 13 PCI Controller (PCIC) (14) PCI Memory Base Address Register 0 (PCIMBAR0) This register packages the memory space base address register of the PCI configuration register that is prescribed with PCI local bus specification. Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: MBA (upper) MBA (lower)
Page 519 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 2, 1 SH: R Memory Type PCI: R Indicates the memory type of local address space 0. 00: 32-bit base address and 32-bit space 01: 32-bit base address and 1-Mbyte space (Not supported) 10: 64-bit base address (Not supported) 11: Reserved...
Page 520 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 31 to 20 MBA H'000 SH: R/W PCI Memory Space 1 Base Address (upper 12 bits) (upper) PCI: R/W Specifies the upper 12 bits of PCI memory base address that corresponds the base address of local address space 1 (SuperHyway bus address space of this LSI).
Page 521 Section 13 PCI Controller (PCIC) (16) PCI Subsystem vender ID Register (PCISVID) Refer to miscellaneous registers section of PCI local bus specification Revision 2.2. Bit: SVID Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 15 to 0 SVID H'0000 SH: R/W Subsystem Vendor ID...
Page 522 Section 13 PCI Controller (PCIC) (18) PCI Capability Pointer Register (PCICP) This register is the expansion function pointer register of the PCI configuration register that is prescribed in the PCI power management specification. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value...
Page 523 Section 13 PCI Controller (PCIC) (20) PCI Interrupt Pin Register (PCIINTPIN) Bit: INTPIN Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 INTPIN H'01 SH: R/W Interrupt Pin Select PCI: R Specifies which interrupt pin is used for connection when the PCIC outputs interrupt request.
Page 524 Section 13 PCI Controller (PCIC) (22) PCI Maximum Latency Register (PCIMAXLAT) This register is not programmable. Bit: MAXLAT Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 MAXLAT H'00 SH: R Maximum Latency PCI: R Specify the worst time from the bus request by the PCI master device to the bus acquisition (not supported).
Page 525 Section 13 PCI Controller (PCIC) (24) PCI Next Item Pointer Register (PCINIP) PCINIP gives the location of the next item in the function's capability list. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 H'00 SH: R Next Item Pointer...
Page 526 Section 13 PCI Controller (PCIC) (25) PCI Power Management Capability Register (PCIPMC) PCIPMCS is a 16-bit register that provides information on the capabilities of the power management related functions. For details, refer to “PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface”. This register must be set during initializing the PCIC registers (PCICR.CFINIT = 0).
Page 527 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description  8 to 6 All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R PCI: R Specifies whether or not the device requires the specific initialization.
Page 528 Section 13 PCI Controller (PCIC) (26) PCI Power Management Control/Status Register (PCIPMCSR) This 16-bit register is used to manage the PCI function's power management status as well as to enable/monitor PMEs. For details, refer to “PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface”.
Page 529 Section 13 PCI Controller (PCIC) (27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE) This register supports PCI bridge specific functionality and is required for all PCI-to-PCI bridges. Bit: — — — — — — B2B3N Initial value: SH R/W: PCI R/W: Initial Bit Name Value...
Page 530 Section 13 PCI Controller (PCIC) (28) PCI Power Consumption/Radiation Register (PCIPCDD) The data register is an 8-bit register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. For details, refer to “PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface”.
Page 531: Local Register
Section 13 PCI Controller (PCIC) 13.3.3 Local Register PCI Control Register (PCICR) PCICR is a 32-bit register which specifies the operation of the PCIC. The register is write protected; only writes in which the upper eight bits (that is, bits 31 to 24) have the value H'A5 are performed.
Page 532 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/W Byte Swap PCI: R Specifies whether or not byte data is swapped when accessing to the PCI local bus. 0: No swap 1: Byte data is swapped For details, see section 13.4.3 (5), Endian or section 13.4.4 (6), Endian.
Page 533 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description PCIRESET Output RSTCTL SH: R/W Controls the PCIRESET output by software. This bit is PCI: R valid when the PCIC operates in host bus bridge mode. 0: Negates PCIRESET output (high level output) 1: Asserts PCIRESET output (low level output) Note: The PCIRESET is also asserted during power- on reset.
Page 534 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 31 to 29  All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. 28 to 20 LSR 0 0000 SH: R/W Size of Local Address Space 0 (9 bits) 0000...
Page 535 Section 13 PCI Controller (PCIC) PCI Local Space Register 1 (PCILSR1) Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: — — — — — — — Initial value: SH R/W: PCI R/W: Bit: — — — — —...
Page 536 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description MBARE SH: R/W PCI Memory Base Address Register 1 Enable PCI: R The local address space 1 can be accessed by setting this bit to 1. 0: PCIMBAR1 disabled 1: PCIMBAR1 enabled PCI Local Address Register 0 (PCILAR0) Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Page 537 Section 13 PCI Controller (PCIC) PCI Local Address Register 1 (PCILAR1) Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: — — — — Initial value: SH R/W: PCI R/W: Bit: — — — — — — — —...
Page 538 Section 13 PCI Controller (PCIC) PCI Interrupt Register (PCIIR) PCIIR records the source of an interrupt. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, the source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs.
Page 539 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 13 to 10  All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. TMTOI SH: R/WC Target Memory Read Retry Timeout Interrupt PCI: R When the PCIC functions as a target, the master did not attempt a retry within the prescribed number of...
Page 540 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description APEDI SH: R/WC Address Parity Error Detection Interrupt PCI: R Indicates an address parity error has been detected. When both the PER and SERRE bits in the PCI command register are set to 1, an address parity error is detected.
Page 541 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description Data Parity Error Interrupt for Target PERR PEDITR SH: R/WC Indicates that the PERR signal has been received PCI: R during a target read access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a target.
Page 542 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description Master Write PERR Detection Interrupt MWPDI SH: R/WC Indicates that the PERR signal has been received PCI: R during a master write access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a master.
Page 543 Section 13 PCI Controller (PCIC) PCI Interrupt Mask Register (PCIIMR) This register is the mask register for PCIIR. Bit: — — — — — — — — — — — — — — — — Initial value: SH R/W: PCI R/W: Bit: DPEI DPEI...
Page 544 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SERR Detection Interrupt Mask SEDIM SH: R/W PCI: R 0: PCIIR.SEDI disabled (masked) 1: PCIIR.SEDI enabled (not masked) DPEITWM 0 SH: R/W Data Parity Error Interrupt Mask for Target Write PCI: R 0: PCIIR.DPEITW disabled (masked) 1: PCIIR.DPEITW enabled (not masked)
Page 545 Section 13 PCI Controller (PCIC) PCI Error Address Information Register (PCIAIR) This register records PCI address information when an error is detected. Bit: Initial value: — — — — — — — — — — — — — — — —...
Page 546 Section 13 PCI Controller (PCIC) PCI Error Command Information Register (PCICIR) This register records the PCI command information when an error is detected. Bit: MTEM — — — — — — — — — — — — — — Initial value: —...
Page 547 Section 13 PCI Controller (PCIC) (10) PCI Arbiter Interrupt Register (PCIAINT) In host bus bridge mode, this register records source of an interrupt. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs.
Page 548 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description TBTOI SH: R/WC Target Bus Time-Out Interrupt An interrupt is detected when the TRDY or STOP PCI: R signal is not asserted within 16 clock cycles on the first data transfer. An interrupt is detected when the TRDY or STOP signal is not asserted within eight clock cycles during the data transfer subsequent to the 2nd.
Page 549 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/WC Target-Abort Interrupt PCI: R Indicates that a transaction is terminated with a target-abort when a device other than the PCIC functions as a bus master. 0: Target-abort interrupt does not occur [Clear condition] Write 1 to this bit (write clear).
Page 550 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description WDPEI SH: R/WC Write Parity Error Interrupt The PERR assertion is detected during a data write PCI: R when a device other than the PCIC functions as a bus master. 0: Write parity error interrupt does not occur [Clear condition] Write 1 to this bit (write clear).
Page 551 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description MBIM SH: R/WC Master-Broken Interrupt Mask PCI: R 0: PCIAINT.MBI disabled (masked) 1: PCIAINT.MBI enabled (not masked) TBTOIM SH: R/WC Target Bus Time-Out Interrupt Mask PCI: R 0: PCIAINT.TBTOI disabled (masked) 1: PCIAINT.TBTOI enabled (not masked) MBTOIM SH: R/WC...
Page 552 Section 13 PCI Controller (PCIC) (12) PCI Arbiter Bus Master Information Register (PCIBMIR) In host bridge mode, this register records when the interrupt is invoked by PCIAINT. When multiple interrupts occur, only the first source is registered. When an interrupt is masked, the source is registered in corresponding bit (set to 1), however, an interrupt occurs.
Page 553 Section 13 PCI Controller (PCIC) (13) PCI PIO Address Register (PCIPAR) This register is configuration address register. Refer to Section 13.4.5 (2), Configuration Space Access. Bit: CCIE — — — — — — — Initial value: — — — — —...
Page 554 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 15 to 11 DN Undefined SH: R/W Device Number PCI:  Specify the device number for a configuration access. Device numbers ranging from 0 to 31 are represented in five bits. A single bit of bits 31 to 16 of the AD signals is driven to high level instead of the IDSEL assertion.
Page 555 Section 13 PCI Controller (PCIC) (14) PCI Power Management Interrupt Register (PCIPINT) This register controls the power management interrupt. Bit: — — — — — — — — — — — — — — — — Initial value: SH R/W: PCI R/W: —...
Page 556 Section 13 PCI Controller (PCIC) (15) PCI Power Management Interrupt Mask Register (PCIPINTM) This is the mask register for PCIPINT. Bit: — — — — — — — — — — — — — — — — Initial value: SH R/W: PCI R/W: —...
Page 557 Section 13 PCI Controller (PCIC) (16) PCI Memory Bank Register 0 (PCIMBR0) This register specifies the upper 14-bit address of the PCI memory space 0 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: PMSBA0 —...
Page 558 Section 13 PCI Controller (PCIC) (17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register specifies the size of the PCI memory space 0. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — — — — —...
Page 559 Section 13 PCI Controller (PCIC) (18) PCI Memory Bank Register 1 (PCIMBR1) This register specifies the upper 14-bit address of the PCI memory space 1 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: PMSBA1 —...
Page 560 Section 13 PCI Controller (PCIC) (19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register specifies the size of the PCI memory space 1. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — — — — MSBAM1 —...
Page 561 Section 13 PCI Controller (PCIC) (20) PCI Memory Bank Register 2 (PCIMBR2) This register specifies the upper 14-bit address of the PCI memory space 2 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: PMSBA2 —...
Page 562 Section 13 PCI Controller (PCIC) (21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register specifies the size of the PCI memory space 2. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — MSBAM2 — — Initial value: SH R/W: PCI R/W:...
Page 563 Section 13 PCI Controller (PCIC) (22) PCI I/O Bank Register (PCIIOBR) This register specifies the upper 14-bit address of the PCI I/O space (address bits 31 to 18). Refer to Section 13.4.3 (3), Accessing PCI I/O Space. Bit: PIOSBA — —...
Page 564 Section 13 PCI Controller (PCIC) (23) PCI I/O Bank Mask Register (PCIIOBMR) This register specifies the size of the PCI I/O space. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — — — — — — —...
Page 565 Section 13 PCI Controller (PCIC) (24) PCI Cache Snoop Control Register 0 (PCICSCR0) An external device can access local memory of this LSI via the PCIC. When an external PCI device accesses cacheable areas of this LSI, the PCIC can support cache snoop function to the on- chip caches.
Page 566 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 1, 0 SNPMD All 0 SH: R/W Snoop Mode for PCICSAR0 PCI: — Specify if PCICSAR0 is compared with address requested by an external device. Also, specify how snoop function is executed when PCICSAR0 is compared.
Page 567 Section 13 PCI Controller (PCIC) (25) PCI Cache Snoop Control Register 1 (PCICSCR1) An external device can access local memory of this LSI via the PCIC. When an external PCI device accesses cacheable areas of this LSI, the PCIC can support cache snoop function to the on- chip caches.
Page 568 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 1, 0 SNPMD All 0 SH: R/W Snoop Mode for PCICSAR1 PCI: — Specify if PCICSAR1 is compared with address requested by an external device. Also, specify how snoop function is executed when PCICSAR1 is compared.
Page 569 Section 13 PCI Controller (PCIC) (26) PCI Cache Snoop Address Register 0 (PCICSAR0) PCICSAR0 specifies the address to be compared with the PCI address requested by an external device. Refer to section 13.4.4 (7), Cache Coherency. Bit: CADR Initial value: SH R/W: PCI R/W: —...
Page 570 Section 13 PCI Controller (PCIC) (27) PCI Cache Snoop Address Register 1 (PCICSAR1) PCICSAR1 specifies the address to be compared with the PCI address requested by an external device. Refer to section 13.4.4 (7), Cache Coherency. Bit: CADR Initial value: SH R/W: PCI R/W: —...
Page 571 Section 13 PCI Controller (PCIC) (28) PCI PIO Data Register (PCIPDR) When accessed, this register will cause the generation of a configuration cycle on the PCI bus. Refer to section 13.4.5 (2), Configuration Space Access. Bit: Initial value: — — —...
Page 572: Operation
Section 13 PCI Controller (PCIC) 13.4 Operation 13.4.1 Supported PCI Commands Table 13.4 Supported Bus Commands CBE[3:0] Command Type PCI Master PCI Target  0000 Interrupt acknowledge cycle  0001 Special cycle Yes* 0010 I/O read Yes* 0011 I/O write Yes* ...
Page 573: Pcic Initialization
Section 13 PCI Controller (PCIC) 13.4.2 PCIC Initialization After a power-on reset, the PCIC enable bit (ENBL) of the PCIC enable control register (PCIECR) and the internal register initialization bit (CFINIT) of the PCI control register (PCICR) is cleared. At this point, if the PCIC is operating as the PCI bus host (host bus bridge mode), the bus privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI bus.
Page 574: Master Access
Section 13 PCI Controller (PCIC) 13.4.3 Master Access This section describes how the PCIC is accessed by software in this LSI and the restrictions on usage, such as buffering and synchronization with other devices, when the PCIC is used in both the host bus bridge and normal modes.
Page 575: Figure 13.2 Superhyway Bus To Pci Local Bus Access
Section 13 PCI Controller (PCIC) Accessing PCI Memory Space Figure 13.2 shows the method for accessing the PCI bus allocated to the PCI memory space from the SuperHyway bus. SuperHyway bus PCI local bus address space (4GB) address space (4GB) H'0000 0000 16 Mbytes H'1000 0000...
Page 576: Figure 13.3 Superhyway Bus To Pci Local Bus Address Translation (Pci Memory Space 0)
Section 13 PCI Controller (PCIC) For PCI memory space 0 accesses, bits 23 to 18 of a SuperHyway bus address are controlled by PCI memory bank mask register 0 (PCIMBMR0). Note: In the following items and figures, “SH” means the SuperHyway bus of this LSI and “PCI”...
Page 577: Figure 13.4 Superhyway Bus To Pci Local Bus Address Translation (Pci Memory Space 1)
Section 13 PCI Controller (PCIC) 26 25 18 17 26 25 18 17 SH address PCI address mask 26 25 18 17 26 25 18 17 PCIMBMR1 PCIMBR1 MSBAM1 PMSBA1 Figure 13.4 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 1) For PCI memory space 2 accesses, bits 28 to 18 of a SuperHyway address are controlled by the PCI memory bank mask register 2 (PCIMBMR2).
Page 578: Figure 13.6 Superhyway Bus To Pci Local Bus Address Translation (Pci I/O)
Section 13 PCI Controller (PCIC) Accessing PCI I/O Space Access within the size of 4-byte. Burst I/O transfers are not supported. The PCI I/O address space is allocated from H'FD20 0000 to H'FE3F FFFF (2 Mbytes). Address translation from SuperHyway bus to PCI local bus The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation.
Page 579 Section 13 PCI Controller (PCIC) Accessing Internal Registers of this LSI All internal registers, that is, PCIECR, PCI configuration registers, and PCI local registers are accessible from the CPU. 4-byte, 2-byte, and byte transmission are supported. Endian The PCIC of this LSI supports both the big endian and little endian formats. Since PCI local bus is inherently little endian, the PCIC supports both byte swapping and non-byte swapping.
Page 580: Figure 13.7 Endian Conversion From Superhyway Bus To Pci Local Bus (Non-Byte Swapping: Tbs = 0)
Section 13 PCI Controller (PCIC) 1. Little Endian MSByte LSByte SH data C' D' A Buffer data C' D' A PCI Address[2] = 1 PCI Address[2] = 0 PCI data 2. Big Endian MSByte LSByte SH data C' D' Buffer data C' D' PCI Address[2] = 0 PCI Address[2] = 1...
Page 581: Figure 13.8 Endian Conversion From Superhyway Bus To Pci Local Bus (Byte Swapping: Tbs = 1)
Section 13 PCI Controller (PCIC) 1. Little Endian MSByte LSByte SH data C' D' A Buffer data C' D' A PCI Address[2] = 1 PCI Address[2] = 0 PCI data 2. Big Endian MSByte LSByte SH data D' C' B' Buffer data C' D' PCI Address[2] = 1...
Page 582: Target Access
Section 13 PCI Controller (PCIC) 13.4.4 Target Access This section describes how the PCIC of this LSI is accessed by an external PCI local bus master when the PCIC is used in both the host bus bridge and normal modes. Accessing This LSI Address Space Accesses to the address space of this LSI by an external PCI bus master are described here.
Page 583 Section 13 PCI Controller (PCIC) To access the address space of this LSI, use the PCI memory base address register (PCIMBAR0/1), PCI local space register (PCILSR0/1), and PCI local address register (PCILAR0/1). The address spaces are mapped by software. The PCIC includes two memory mapping registers.
Page 584: Figure 13.10 Pci Local Bus To Superhyway Bus Address Translation (Local Address Space 0/1)
Section 13 PCI Controller (PCIC) 2928 20 19 2928 2019 SH address PCI address compare 29 28 2019 2928 2019 PCIMBAR0/1 PCILAR0/1 MBA (upper) 2928 2019 PCILSR0/1 0 0 0 0 0 1 1 0 0 Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation (Local Address Space 0/1) When all the MBARE bits in PCILSR0/1 are 0, the PCI local bus address is sent to the SuperHyway bus without translation.
Page 585: Figure 13.11 Pci Local Bus To Superhyway Bus Address Translation (Pcic I/O Space)
Section 13 PCI Controller (PCIC) SH address H'FE04 01 PCI Address compare IOB (upper) PCIIBAR Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) Accessing PCIC Registers Configuration Registers: Access the configuration registers using an offset from the PCI configuration register space base address with the configuration read or write command.
Page 586 Section 13 PCI Controller (PCIC) Exclusive Access The lock access on the PCI bus is supported. When the PCI local bus is locked, the PCIC is accessible from the device that activates the LOCK signal. SuperHyway bus resource lock does not occur. (Another on-chip module can access the PCIC during a lock transfer.) Endian This LSI supports both the big and little endian formats.
Page 587: Figure 13.12 Endian Conversion From Pci Local Bus To Superhyway Bus (Non-Byte Swapping: Tbs = 0)
Section 13 PCI Controller (PCIC) 1. Little Endian PCI data PCI Address[2] = 0 PCI Address[2] = 1 Buffer data C' D' A MSByte LSByte SH data C' D' A 2. Big Endian PCI data PCI Address[2] = 1 PCI Address[2] = 0 Buffer data C' D' MSByte...
Page 588: Figure 13.13 Endian Conversion From Pci Local Bus To Superhyway Bus (Non-Byte Swapping: Tbs = 1)
Section 13 PCI Controller (PCIC) 1. Little Endian PCI data PCI Address[2] = 0 PCI Address[2] = 1 Buffer data C' D' D MSByte LSByte SH data C' D' A 2. Big Endian PCI data PCI Address[2] = 1 PCI Address[2] = 0 Buffer data D' C' B' MSByte...
Page 589 Section 13 PCI Controller (PCIC) Cache Coherency The PCIC supports cache snoop function. When the PCIC functions as a target device, cache coherency is guaranteed for accesses from a master device connected to a PCI bus in both the host bus bridge mode and normal mode. When accessing this LSI cacheable area, set the cache snoop registers: the PCI cache snoop control registers (PCICSCR0 and PCICSCR1) and PCI cache snoop address register (PCICSAR0 and PCICSAR1).
Page 590: Figure 13.14 Cache Flush/Purge Execution Flow For Pci Local Bus To Superhyway Bus
Section 13 PCI Controller (PCIC) PCI address Cache snoop control register SuperHyway address Cache snoop address register compare No hit issue the flush/purge Issue the read/write issue the read/write Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus Rev.1.00 Dec.
Page 591: Host Bus Bridge Mode
Section 13 PCI Controller (PCIC) 13.4.5 Host Bus Bridge Mode PCI Host bus bridge Mode Operation The PCIC supports a subset of the PCI Local Bus Specification Revision 2.2 and can be connected to a device with a PCI bus interface. While the PCIC is set in host bus bridge mode, or while set in normal mode, operation differs according to whether or not bus parking is performed, and whether or not the PCI bus arbiter function is enabled or not.
Page 592: Figure 13.15 Address Generation For Type 0 Configuration Access
Section 13 PCI Controller (PCIC) 31 30 24 23 16 15 11 10 Configuration Reserved address register (PCIPAR) CCIE PCI local bus Only one '1' 00000 address (AD31 to AD0) 16 15 11 10 Figure 13.15 Address Generation for Type 0 Configuration Access In configuration accesses, a PCI master abort (no device connected) will not cause an interrupt.
Page 593: Table 13.6 Interrupt Priority
Section 13 PCI Controller (PCIC) After device 1 has claimed and granted the bus, and transferred data, the priority is as follows: PCIC > device 0 > device 2 > device 3 > device 1 Then, after the PCIC has claimed and granted the bus, and transferred data, the priority is changed Device 0 >...
Page 594: Normal Mode
Section 13 PCI Controller (PCIC) The PCIC can store the error information on the PCI bus. If an error occurs, the error address is stored in the PCI error address information register (PCIAIR), the types of transfer and command information are stored in the PCI error command information register. And then if the PCIC operates host bus bridge mode, the bus master information is stored in the PCI error bus master information register.
Page 595: Pci Local Bus Basic Interface
Section 13 PCI Controller (PCIC) (normal) (clock stop) (bus idle) (power down) Figure 13.16 PCI Local Bus Power Down State Transition The PCIC detects when the power state (PS) bit of the PCI power management control/status register changes (when it is written to from an external PCI device), and issues a power management interrupt.
Page 596: Figure 13.17 Master Write Cycle In Host Bus Bridge Mode (Single)
Section 13 PCI Controller (PCIC) Master Read/Write Cycle Timing Figures13.17 is an example of a single-write cycle in host bus bridge mode. Figure 13.18 is an example of a single read cycle in host bus bridge mode. Figure 13.19 is an example of a burst write cycle in normal mode.
Page 597: Figure 13.18 Master Read Cycle In Host Bus Bridge Mode (Single)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single) Rev.1.00 Dec.
Page 598: Figure 13.19 Master Write Cycle In Normal Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.19 Master Write Cycle in Normal Mode (Burst) Rev.1.00 Dec.
Page 599: Figure 13.20 Master Read Cycle In Normal Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.20 Master Read Cycle in Normal Mode (Burst) Rev.1.00 Dec.
Page 600 Section 13 PCI Controller (PCIC) Target Read/Write Cycle Timing The PCIC responds to target memory burst read accesses from an external master by retries until 8 longword (32-bit) data are prepared in the PCIC's internal FIFO. That is, it always responds to the first target burst read with a retry.
Page 601: Figure 13.21 Target Read Cycle In Normal Mode (Single)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL At configuration access REQOUT GNTIN [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.21 Target Read Cycle in Normal Mode (Single) Rev.1.00 Dec.
Page 602: Figure 13.22 Target Write Cycle In Normal Mode (Single)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL At configuration access REQOUT GNTIN [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.22 Target Write Cycle in Normal Mode (Single) Rev.1.00 Dec.
Page 603: Figure 13.23 Target Memory Read Cycle In Host Bus Bridge Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst) Rev.1.00 Dec.
Page 604: Figure 13.24 Target Memory Write Cycle In Host Bus Bridge Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst) Rev.1.00 Dec.
Page 605: Figure 13.25 Master Write Cycle In Host Bus Bridge Mode (Burst, With Stepping)
Section 13 PCI Controller (PCIC) Address/Data Stepping Timing By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the PCIC drives the AD bus over 2 clocks. This function can be used when there is a heavy load on the PCI bus and the AD bus does not achieve the stipulated logic level in one clock.
Page 606: Figure 13.26 Target Memory Read Cycle In Host Bus Bridge Mode (Burst, With Stepping)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping) Rev.1.00 Dec.
Page 607: Section 14 Direct Memory Access Controller (Dmac)
Section 14 Direct Memory Access Controller (DMAC) Section 14 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (DMA transfer end notification), external memory, on-chip memory, memory-mapped external devices, and peripheral modules.
Page 608: Figure 14.1 Block Diagram Of Dmac
Section 14 Direct Memory Access Controller (DMAC) Figure 14.1 shows the block diagram of the DMAC. DMAC channels 0 to 5 SARm On-chip memory Iteration control DARm Peripheral Peripheral bus bridge module Register TCRm Peripheral control CHCRm Start-up control DMAOR0 DMA transfer request signal DMARS0-2 DMA transfer acknowledge signal...
Page 609: Input/Output Pins
Section 14 Direct Memory Access Controller (DMAC) 14.2 Input/Output Pins The external pins for the DMAC are described below. Table 14.1 lists the configuration of the pins that are connected to external device. The DMAC has pins for four channels (channel 0 to 3) for external bus use.
Page 610 Section 14 Direct Memory Access Controller (DMAC) Channel Pin Name Function Description DREQ3* DMA transfer request Input DMA transfer request input from external device to channel 3 DRAK3* DREQ3 acceptance Output Notifies acceptance of DMA transfer confirmation request and start of execution from channel 3 to external device DACK3* DMA transfer end...
Page 611: Register Descriptions
Section 14 Direct Memory Access Controller (DMAC) 14.3 Register Descriptions Table 14.2 shows the configuration of registers of the DMAC. Table 14.3 shows the register states in each processing mode. Table 14.2 Register Configuration of DMAC Access Channel Name Abbrev. P4 Address Area 7 Address Size*...
Page 612 Section 14 Direct Memory Access Controller (DMAC) Access Channel Name Abbrev. P4 Address Area 7 Address Size* DMA source address register B0 SARB0 H'FC80 8120 H'1C80 8120 DMA destination address register B0 DARB0 H'FC80 8124 H'1C80 8124 DMA transfer count register B0 TCRB0 H'FC80 8128 H'1C80 8128...
Page 613 Section 14 Direct Memory Access Controller (DMAC) Access Channel Name Abbrev. P4 Address Area 7 Address Size* 6 to 11 DMA operation register 1 DMAOR1 R/W* H'FC81 8060 H'1C81 8060 DMA source address register 10 SAR10 H'FC81 8070 H'1C81 8070 DMA destination address register 10 DAR10 H'FC81 8074 H'1C81 8074...
Page 614: Table 14.3 Register States In Each Processing Mode
Section 14 Direct Memory Access Controller (DMAC) Table 14.3 Register States in Each Processing Mode Power-on Reset Manual Reset by by PRESET/WDT/ WDT/Multiple Sleep by SLEEP Module Channel Name Abbrev. H-UDI Exceptions Instruction Standby DMA source address register 0 SAR0 Undefined Undefined Retained...
Page 615 Section 14 Direct Memory Access Controller (DMAC) Power-on Reset Manual Reset by by PRESET/WDT/ WDT/Multiple Sleep by SLEEP Module Channel Name Abbrev. H-UDI Exceptions Instruction Standby DMA source address register SARB0 Undefined Undefined Retained Retained DMA destination address DARB0 Undefined Undefined Retained Retained...
Page 616 Section 14 Direct Memory Access Controller (DMAC) Power-on Reset Manual Reset by by PRESET/WDT/ WDT/Multiple Sleep by SLEEP Module Channel Name Abbrev. H-UDI Exceptions Instruction Standby DMA transfer count register 7 TCR7 Undefined Undefined Retained Retained DMA channel control register 7 CHCR7 H'4000 0000 H'4000 0000 Retained...
Page 617: Dma Source Address Registers 0 To 11 (Sar0 To Sar11)
Section 14 Direct Memory Access Controller (DMAC) Power-on Reset Manual Reset by by PRESET/WDT/ WDT/Multiple Sleep by SLEEP Module Channel Name Abbrev. H-UDI Exceptions Instruction Standby DMA source address register SARB7 Undefined Undefined Retained Retained DMA destination address DARB7 Undefined Undefined Retained Retained...
Page 618: Dma Source Address Registers B0 To B3, B6 To B9
Section 14 Direct Memory Access Controller (DMAC) 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9) SARB are 32-bit readable/writable registers that specify the source address of a DMA transfer that is set in SAR again in repeat/reload mode. Data to be written from the CPU to SAR is also written to SARB.
Page 619: Dma Destination Address Registers B0 To B3, B6 To B9
Section 14 Direct Memory Access Controller (DMAC) 14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3, DARB6 to DARB9) DARB are 32-bit readable/writable registers that specify the destination address of a DMA transfer that is set in DAR again in repeat/reload mode. Data to be written from the CPU to DAR is also written to DARB.
Page 620: Dma Transfer Count Registers 0 To 11 (Tcr0 To Tcr11)
Section 14 Direct Memory Access Controller (DMAC) 14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11) TCR are 32-bit readable/writable registers that specify the DMA transfer count. The number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set.
Page 621: Dma Transfer Count Registers B0 To B3, B6 To B9
Section 14 Direct Memory Access Controller (DMAC) 14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to TCRB9) TCRB are 32-bit readable/writable registers. Data to be written from the CPU to TCR is also written to TCRB.
Page 622: Dma Channel Control Registers 0 To 11 (Chcr0 To Chcr11)
Section 14 Direct Memory Access Controller (DMAC) 14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) CHCR are 32-bit readable/writable registers that control the DMA transfer mode. Bit: LCKN RPT[2:0] Initial value: R/W: R/W R/(W)* R/W Bit: DM[1:0] SM[1:0] RS[3:0] TS[1:0]...
Page 623 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions 27 to 25 RPT[2:0] DMA Setting Renewal Specify These bits are enabled in CHCR0 to CHCR3 and CHCR6 to CHCR9. 000: Normal mode (DMAC operation) 001: Repeat mode SAR/DAR/TCR used as repeat area 010: Repeat mode DAR/TCR used as repeat area...
Page 624 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions DMA Transfer Size Specify With TS1 and TS0 (bits 4 and 3), this bit specifies the DMA transfer size. When the transfer source or transfer destination is a register of an peripheral module that access size is designated, the transfer size for the register should be the same value of its access size.
Page 625 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions R/(W)* Half End Flag After HIE (bit 18) is set to 1 and the number of transfers become half of TCR (1 bit shift to right) which is set before transfer starts, HE becomes 1.
Page 626 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions Half End Interrupt Enable Specifies whether an interrupt request is generated to the CPU when the number of transfers is decreased to half of the TCR value (a read transfer cycle end) set preceding the transfer.
Page 627 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions 15, 14 DM[1:0] Destination Address Mode 1, 0 Specify whether the DMA destination address is incremented, decremented, or left fixed. 00: Fixed destination address 01: Destination address is incremented +1 in byte units transfer +2 in word units transfer +4 in longword units transfer...
Page 628 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions 11 to 8 RS[3:0] 0000 Resource Select 3 to 0 Specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state that the DMA enable bit (DE) is cleared to 0.
Page 629 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the final DMA transfer. Setting this bit to 1 generates an interrupt request (DMINT) to the CPU when the TE bit is set to 1 and the final DMA transfer of read cycle ended.
Page 630 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions DMA Enable Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF, and AE in DMAOR must be 0.
Page 631: Dma Operation Register 0, 1 (Dmaor0 And Dmaor1)
Section 14 Direct Memory Access Controller (DMAC) 14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1) DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. DMAOR 0 is for channel 0 to 5, and DMAOR1 is for channel 6 to11.
Page 632 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions 9, 8 PR[1:0] Priority Mode 1, 0 Select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 (DMAOR0) CH6 >...
Page 633 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions NMIF R/(W)* NMI Flag Indicates that an NMI interrupt occurred. If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. When the NMI is input, the DMA transfer in progress can be done in at least one transfer unit.
Page 634: Dma Extended Resource Selectors (Dmars0 To Dmars2)
Section 14 Direct Memory Access Controller (DMAC) 14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2) DMARS are 16-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3, and DMARS2 specifies for channels 4 and 5.
Page 635 Section 14 Direct Memory Access Controller (DMAC) • DMARS1 Bit: C3MID[5:0] C3RID[1:0] C2MID[5:0] C2RID[1:0] Initial value: R/W: Initial Bit Name Value Descriptions 15 to 10 C3MID[5:0] 000000 Transfer request module ID5 to ID0 for DMA channel 3 (MID) See table 14.4. 9, 8 C3RID[1:0] 00 Transfer request register ID1 and ID0 for DMA channel...
Page 636 Section 14 Direct Memory Access Controller (DMAC) • DMARS2 Bit: C5MID[5:0] C5RID[1:0] C4MID[5:0] C4RID[1:0] Initial value: R/W: Initial Bit Name Value Descriptions 15 to 10 C5MID[5:0] 000000 Transfer request module ID5 to ID0 for DMA channel 5 (MID) See table 14.4. 9, 8 C5RID[1:0] 00 Transfer request register ID1 and ID0 for DMA channel...
Page 637: Table 14.4 Transfer Request Sources
Section 14 Direct Memory Access Controller (DMAC) Table 14.4 Transfer Request Sources Peripheral Setting Value for One Module Channel (MID and RID fields) MID[5:0] RID[1:0] Function SCIF0 H'21 B'001000 B'01 Transmit H'22 B'10 Receive SCIF1 H'29 B'001010 B'01 Transmit H'2A B'10 Receive H'41...
Page 638: Operation
Section 14 Direct Memory Access Controller (DMAC) 14.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and peripheral module request.
Page 639: Table 14.5 Selecting External Request Detection With Dl, Ds Bits
Section 14 Direct Memory Access Controller (DMAC) Table 14.5 Selecting External Request Detection with DL, DS Bits CHCRn (n = 0 to 3) Detection of External Request Low level detection (initial value; DREQ) Falling edge detection High level detection Rising edge detection When DREQ is accepted, the DREQ pin becomes request accept disabled state.
Page 640 Section 14 Direct Memory Access Controller (DMAC) When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive data register.
Page 641: Table 14.7 Peripheral Module Request Modes
Section 14 Direct Memory Access Controller (DMAC) Table 14.7 Peripheral Module Request Modes DMA Transfer DMARS DMA Transfer Request Source Request Signal Source Destination Mode 001000 SCI F0 TXI (transmit FIFO data SCFTDR0 Cycle transmitter empty interrupt) steal SCIF0 RXI (receive FIFO data SCFRDR0 Cycle receiver...
Page 642: Channel Priority
Section 14 Direct Memory Access Controller (DMAC) 14.4.2 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it transfers data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are selected by the bits PR[1:0] in DMAOR0 for channels 0 to 5 and DMAOR1 for channels 6 to 11. If the DMAC receives simultaneous transfer requests from both any channels 0 to 5 and 6 to 11 respectively, then executes each channels 0 to 5 or 6 to 11 request alternately (initial state: channel 0 to 5 is higher priority).
Page 643: Figure 14.2 Round-Robin Mode (Example Of Channel 0 To 5)
Section 14 Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Channel 0 becomes bottom priority Priority order CH1 > CH2 > CH3 > CH4 > CH5 > CH0 after transfer (2) When channel 1 transfers Channel 1 becomes bottom...
Page 644: Figure 14.3 Changes In Channel Priority In Round-Robin Mode (Example Of Channel 0 To 5)
Section 14 Direct Memory Access Controller (DMAC) Figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1.
Page 645: Dma Transfer Types
Section 14 Direct Memory Access Controller (DMAC) 14.4.3 DMA Transfer Types DMA transfer type is dual address mode transfer. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. Dual Address Modes: In dual address mode, both the transfer source and destination are accessed by an address. The source and destination can be located externally or internally.
Page 646: Figure 14.5 Example Of Dma Transfer Timing In Dual Address Mode (Source: Ordinary Memory, Destination: Ordinary Memory)
Section 14 Direct Memory Access Controller (DMAC) Auto request, external request, and peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. CHCR can specify whether the DACK is output in read cycle or write cycle. Figure 14.5 shows an example of DMA transfer timing in dual address mode.
Page 647: Figure 14.6 Dma Transfer Timing Example In Cycle-Steal Normal Mode 1
Section 14 Direct Memory Access Controller (DMAC) Bus Modes: There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB and LCKN bits in CHCR. Moreover, cycle steal mode has normal and intermittent modes that are specified by the CMS bits in DMAOR.
Page 648: Figure 14.7 Dma Transfer Timing Example In Cycle-Steal Normal Mode 2
Section 14 Direct Memory Access Controller (DMAC) DREQ Bus mastership retured to CPU once SuperHyway DMAC DMAC DMAC DMAC bus cycle Read Write Read Write Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2 (DREQ Low Level Detection) ...
Page 649: Figure 14.9 Dma Transfer Timing Example In Burst Mode (Dreq Low Level Detection)
Section 14 Direct Memory Access Controller (DMAC) • Burst Mode (LCKN = 0, TB = 1) In burst mode, once the DMAC obtains the SuperHyway bus mastership, the transfer is performed continuously without releasing the bus mastership until the transfer end condition is satisfied.
Page 650: Table 14.9 Dma Transfer Matrix In External Request Mode (Only Channels 0 To 3)
Section 14 Direct Memory Access Controller (DMAC) Table 14.9 DMA Transfer Matrix in External Request Mode (only channels 0 to 3) Transfer Destination L RAM, Peripheral SuperHyway Transfer Source LBSC space DDRIF space PCIC space module* LBSC space Yes* Yes* DDRIF space Yes* Yes*...
Page 651: Table 14.10 Dma Transfer Matrix In Peripheral Module Request Mode
Section 14 Direct Memory Access Controller (DMAC) Table 14.10 DMA Transfer Matrix in Peripheral module Request Mode Transfer Destination L RAM, Peripheral SuperHyway Transfer Source LBSC space DDRIF space PCIC space module* LBSC space DDRIF space PCIC space Peripheral module* L RAM, SuperHyway RAM No [Legend] Yes:...
Page 652: Dma Transfer Flow
Section 14 Direct Memory Access Controller (DMAC) SuperHyway DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1 bus cycle DMA CH0 and CH1 DMA CH1 DMA CH1 Burst mode Burst mode Burst mode CH0 transfer source CH1 transfer source...
Page 653: Figure 14.11 Dma Transfer Flowchart
Section 14 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR, SARB, DARB, TCRB, DMARS) DE, DME = 1 and TE, AE, NMIF = 0? Transfer request occurs? Bus mode, DREQ detection system, transfer request mode Transfer (1 transfer unit);...
Page 654: Repeat Mode Transfer
Section 14 Direct Memory Access Controller (DMAC) 14.4.5 Repeat Mode Transfer In a repeat mode transfer, a DMA transfer is repeated without specifying the transfer settings every time before executing a transfer. Using a repeat mode transfer with the half end function allows a double buffer transfer executed virtually.
Page 655: Reload Mode Transfer
Section 14 Direct Memory Access Controller (DMAC) not cleared in the procedure 4, then the transfer is stopped according to the condition of both the HE and the TE bits are set to 1. As explained above, a repeat mode transfer enables sequential voice compression by changing buffer for storing data received consequentially and a data buffer for processing signals alternately.
Page 656: Dreq Pin Sampling Timing
Section 14 Direct Memory Access Controller (DMAC) 14.4.7 DREQ Pin Sampling Timing Figures 14.13 to 14.16 show the sample timing of the DREQ input in each bus mode, respectively. CKOUT DMAC Bus cycle DREQ (Falling edge) 1st acceptance 2nd acceptance DRAK (Low-active) DACK...
Page 657: Figure 14.15 Example Of Dreq Input Detection In Burst Mode Edge Detection
Section 14 Direct Memory Access Controller (DMAC) CLKOUT Bus cycle DMAC DMAC Burst acceptance DREQ (Falling edge) DRAK (Low-active) DACK (Low-active) : Non-sensitive period Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection CLKOUT Bus cycle DMAC DREQ (Overrun 0, Low-level)
Page 658: Usage Notes
Section 14 Direct Memory Access Controller (DMAC) 14.5 Usage Notes Pay attentions to the following notes when the DMAC is used. 14.5.1 Module Stop While the DMAC is in operation, modules should not be stopped by setting MSTPCR (transition to the module standby state) .When modules are stopped, transfer contents cannot be guaranteed. 14.5.2 Address Error When a DMA address error is occurred, after execute the following procedure, and then start a...
Page 659: Dack Output Division
Section 14 Direct Memory Access Controller (DMAC) 14.5.4 DACK output division The DACK output is divided to align the data unit like the CSn output when a DMA transfer unit is divided with multiple bus cycles, for example when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units, and the CSn output is negated between these bus cycles.
Page 660 Section 14 Direct Memory Access Controller (DMAC) The transfer destination is the LBSC space and the DACK is output during the write cycle: (1) Set B'001 to B'111 (i.e., other than 000) to the IWW bits in CSnBCR Note: * The transfer source is the LBSC space and the DACK is output during the read cycle or the transfer destination is the LBSC space and the DACK is output during the write cycle.
Page 661: Table14.11 Register Settings For Sram, Burst Rom, Byte Control Sram Interface
Section 14 Direct Memory Access Controller (DMAC) Table14.11 Register Settings for SRAM, Burst ROM, Byte Control SRAM Interface Register Settings of CSn is not negated Bus Width DMA Transfer Bus Cycle CSnBCR.IWRRD, [bit] Access Size Number IWRRS or IWW CSnWCR.ADS and ADH Byte Word B'000...
Page 662: Table14.12 Register Settings For Pcmcia Interface
Section 14 Direct Memory Access Controller (DMAC) Table14.12 Register Settings for PCMCIA Interface Register Settings of CSn is not negated Bus Width DMA Transfer Bus Cycle [bit] Access Size Number CSnBCR.IWRRD,IWRRS or IWW Byte Word Longword 16-Byte B'000 32-Byte Byte Word Longword 16-Byte...
Page 663: Section 15 Clock Pulse Generator (Cpg)
Section 15 Clock Pulse Generator (CPG) Section 15 Clock Pulse Generator (CPG) The CPG generates clocks provided to both the inside and outside of the SH7780, and controls the power-down mode function. The CPG comprises a crystal oscillator circuit, PLLs, and a divider. 15.1 Features The CPG has the following features.
Page 664: Figure 15.1 Block Diagram Of Cpg
Section 15 Clock Pulse Generator (CPG) Figure 15.1 is a block diagram of the CPG. PLL circuit 2 CLKOUT (× 1) Divider Bus clock (Bck) (× 1/2) CPU clock Oscillator (× 1/4) (Ick) XTAL (× 1/5) PLL circuit 1 (× 1/6) SuperHyway (×...
Page 665 Section 15 Clock Pulse Generator (CPG) The function of each block is described below. • PLL circuit 1 PLL circuit 1 multiplies the frequency of the external crystal oscillator and the clock input on the EXTAL pin by 24. • PLL circuit 2 PLL circuit 2 coordinates the phases of the bus clock (Bck) and the clock signal output from the CLKOUT pin that is used as the external peripheral interface clock.
Page 666: Input/Output Pins
Section 15 Clock Pulse Generator (CPG) 15.2 Input/Output Pins Table 15.1 lists the CPG pin configuration. Table 15.1 CPG Pin Configuration Pin Name Function Description MODE0, MODE1, Mode Control Input Select the clock operating mode of after power-on MODE2, and Pins 0,1,2,7 reset.
Page 667: Clock Operating Modes
Section 15 Clock Pulse Generator (CPG) 15.3 Clock Operating Modes The correspondence between settings of the mode control pins (MODE7 and MODE2 to MODE0) and clock operating modes after power-on reset is shown in table 15.2. Table 15.2 Clock Operating Modes Frequency Multiplication Ratio Clock Mode Control Pin Setting...
Page 668: Register Descriptions
Section 15 Clock Pulse Generator (CPG) 15.4 Register Descriptions Table 15.3 shows the CPG register configuration. Table 15.4 shows the register states in each processing mode. Table 15.3 Register configuration Access Sync Area 7 Register Name Abbreviation R/W P4 Address Address Size clock...
Page 669: Frequency Control Register (Frqcr)
Section 15 Clock Pulse Generator (CPG) 15.4.1 Frequency Control Register (FRQCR) FRQCR is a 32-bit readable/writable register that selects the frequency division ratio of the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck) and the bus clock (Bck).
Page 670 Section 15 Clock Pulse Generator (CPG) Initial Bit Name Value R/W Description BFC3 Bus Clock (B ) Frequency Division Ratio Setting 0011: ×3 BFC2 Undefined 0100: ×2 BFC1 Undefined 0101: ×3/2 BFC0 Undefined 0110: ×1 Other than above: Setting prohibited The initial value of this field after power-on reset depends on the mode pin setting (see table 15.2).
Page 671: Pll Control Register (Pllcr)
Section 15 Clock Pulse Generator (CPG) 15.4.2 PLL Control Register (PLLCR) PLLCR is a 32-bit readable/writable register that controls the clock output on the CLKOUT pin. This register can only be accessed in longwords. BIt:      ...
Page 672: Notes On Board Design
Section 15 Clock Pulse Generator (CPG) 15.5 Notes on Board Design When Using Crystal Resonator: Place the crystal resonator and capacitors close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins. Crystal Resonator Recommended values CL1 = CL2 = 0 to 33 pF...
Page 673: Figure 15.3 Points For Attention When Using Pll And Dll Circuit
Section 15 Clock Pulse Generator (CPG) RCB1 VDD-PLL1 Recommended values 4.7Ω CPB11 CPB12 RCB1 = RCB2 = RCB3 = 4.7Ω CPB11 = CPB21 = CPB31 = 0.1µF 0.1µF 1µF CPB12 = CPB22 = CPB32 = 1µF VSS-PLL1 RD1 = RD2 = 20Ω CD11 = CD21 = 0.1µF RCB2 CD12 = CD22 = 1µF...
Page 674 Section 15 Clock Pulse Generator (CPG) Rev.1.00 Dec. 13, 2005 Page 624 of 1286 REJ09B0158-0100...
Page 675: Section 16 Watchdog Timer And Reset
Section 16 Watchdog Timer and Reset Section 16 Watchdog Timer and Reset The reset and watchdog timer (WDT) control circuit comprises the reset control unit and WDT control unit which control the power-on reset sequence and a reset for on-chip peripheral modules and external devices.
Page 676: Figure 16.1 Block Diagram Of Wdt
Section 16 Watchdog Timer and Reset Figure 16.1 shows a block diagram of the WDT. MRESETOUT Watchdog timer and Reset Reset control PRESET circuit Internal reset request STATUS[1:0] Interrupt INTC control circuit Internal reset request WDTCSR Count-up signal WDTCNT WDTBCNT Peripheral clock Comparator Overflow...
Page 677: Input/Output Pins
Section 16 Watchdog Timer and Reset 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the reset control unit. Table 16.1 Pin Configuration Pin name Function Description PRESET Reset Input Power-on reset MRESETOUT* Manual reset output Output Low level output during manual reset execution STATUS1* Processing state 1...
Page 678: Register Descriptions
Section 16 Watchdog Timer and Reset 16.3 Register Descriptions Table 16.2 shows the registers of the reset and watchdog timer. Table 16.3 shows the register states in each processing mode. Table 16.2 Register Configuration Area 7 Access Sync Register Name Abbreviation R/W P4 Address Address...
Page 679: Watchdog Timer Stop Time Register (Wdtst)
Section 16 Watchdog Timer and Reset 16.3.1 Watchdog Timer Stop Time Register (WDTST) WDTST is a readable/writable 32-bit register that specifies the time until a watchdog timer overflows. The time until WDTCNT overflows becomes the minimum value when set H'001 to the bits 11 to 0, and the maximum value when set H'000 to the bits 11 to 0.
Page 680: Watchdog Timer Control/Status Register (Wdtcsr)
Section 16 Watchdog Timer and Reset 16.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a readable/writable 32-bit register that comprises the timer mode-selecting bit and overflow flags. Use a longword access to write to the WDTCSR, with H'A5 in the bits 31 to 24. The reading value of bits 31 to 24 is always H'00.
Page 681: Watchdog Timer Base Stop Time Register (Wdtbst)
Section 16 Watchdog Timer and Reset Initial Bit Name Value Description RSTS Reset Select Specifies the kind of reset to be performed when WDTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. 0: Power-on reset 1: Manual reset WOVF Watchdog Timer Overflow Flag...
Page 682: Watchdog Timer Counter (Wdtcnt)
Section 16 Watchdog Timer and Reset 16.3.4 Watchdog Timer Counter (WDTCNT) WDTCNT is a 32-bit read-only register that comprises 12-bit watchdog timer counter and counts up on the WDTBCNT overflow signal. When WDTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt is generated in interval timer mode. Writing to WDTCNT is invalid.
Page 683: Operation
Section 16 Watchdog Timer and Reset 16.4 Operation 16.4.1 Reset request Power-on reset and manual reset are available. These sources are follows. Power-on reset • Input low level via PRESET pin. • The WDTCNT overflows when the WT/IT bit in the WTCSR is 1, and the RSTS bit is 0. •...
Page 684: Using Watchdog Timer Mode
Section 16 Watchdog Timer and Reset Manual_reset() EXPEVT = H'0000 0020; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A000 0000; 16.4.2 Using watchdog timer mode 1.
Page 685: Time For Wdt Overflow
Section 16 Watchdog Timer and Reset Figure 16.2 shows a WDT counting up operation. WDT mode: Interval timer mode: Clear counter after WDTCNT Clear counter when overflowed value reset operation Setting value of WDTST Counting up with overflow signal of WDTBCNT H'0000 0000 Time WDTBCNT...
Page 686: Clearing Wdt Counter
Section 16 Watchdog Timer and Reset And the time until WDTCNT overflows becomes the minimum value when H'001 is set to × WDTST. The minimum overflow time is approximately 5.243 ms (= 2^1 [bit] 5.243 [ms]). 16.4.5 Clearing WDT Counter Writing H'55 to WDTBST with longword access clears WDTBCNT and writing the overflow setting value to WDTST clears WDTCNT.
Page 687: Figure 16.3 Status Output During Power-On
Section 16 Watchdog Timer and Reset XTAL (oscillator) CLKOUT output PRESET input TRST input STATUS[1:0] HH (reset) LL (normal) output XTAL (oscillator) Reset holding stabilization time synchronization time settling time Figure 16.3 STATUS Output during Power-on PRESET input during normal operation It is necessary to ensure the PLL synchronization settling time when the PRESET input during normal operation.
Page 688: Power-On Reset By Watchdog Timer Overflow
Section 16 Watchdog Timer and Reset PRESET input during Sleep Mode It is necessary to ensure the PLL oscillation time when power-on reset generates by the PRESET pin low revel input during sleep mode. XTAL (oscillator) CLKOUT output PRESET input STATUS[1:0] HL (sleep) HH (reset)
Page 689: Figure 16.6 Status Output By Watchdog Timer Overflow Power-On Reset During Normal Operation
Section 16 Watchdog Timer and Reset Power-On Reset by Watchdog timer Overflowed in Normal Operation XTAL (oscillator) CLKOUT output WDT overflow signal STATUS[1:0] LL (normal) HH (reset) LL (normal) output WDT reset WDT reset setup time holding time Figure 16.6 STATUS Output by Watchdog timer overflow Power-On Reset during Normal Operation Power-On Reset by Watchdog timer Overflowed in Sleep Mode XTAL...
Page 690: Manual Reset By Watchdog Timer Overflow
Section 16 Watchdog Timer and Reset 16.5.3 Manual Reset by Watchdog Timer Overflow The transition time from watchdog timer overflowed to manual reset state (watchdog timer reset setup time) is 1 clock cycle of the XTAL clock and thereafter equal to or more than 5 clock cycles of the peripheral clock (Pck).
Page 691: Figure 16.9 Status Output By Watchdog Timer Overflow Manual Reset During Sleep Mode
Section 16 Watchdog Timer and Reset Manual Reset by Watchdog timer Overflowed in Sleep Mode XTAL (oscillator) CLKOUT output WDT overflow signal MRESETOUT output STATUS[1:0] HL (sleep) HH (reset) LL (normal) output WDT reset WDT reset setup time holding time Figure 16.9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep Mode Rev.1.00 Dec.
Page 692 Section 16 Watchdog Timer and Reset Rev.1.00 Dec. 13, 2005 Page 642 of 1286 REJ09B0158-0100...
Page 693: Section 17 Power-Down Mode
Section 17 Power-Down Mode Section 17 Power-Down Mode In power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 17.1 Features The SH7780 power-down mode has the following features. • Supports sleep mode and module standby mode •...
Page 694: Table 17.1 Power-Down Modes
Section 17 Power-Down Mode Table 17.1 Power-Down Modes State On-Chip Module On-Chip Power- Transition Memory DDR-SDRAM Down Mode Condition DMAC Others Cancellation Sleep SLEEP Operated Halted Retained Operated Operated Operated Retained Auto-refresh - Interrupt instruction (register or self- - Power-on executed contents refresh*...
Page 695: Input/Output Pins
Section 17 Power-Down Mode 17.2 Input/Output Pins Table 17.2 shows the pin configuration of the Power-Down Modes. Table 17.2 Pin Configuration Pin name Function Description STATUS1 Processing state 1 Output Indicate the processor's operating status STATUS0 Processing state 2 STATUS1 STATUS0 Operating Status High...
Page 696: Standby Control Register (Mstpcr)
Section 17 Power-Down Mode 17.3.1 Standby Control Register (MSTPCR) MSTPCR is a 32-bit readable/writable register that can individually start or stop the module assigned to each bit. MSTPCR can be accessed only in longwords. Bit:      ...
Page 697 Section 17 Power-Down Mode Initial Bit Name Value Description 13 to 8 MSTP[13:8] All 0 Module Stop Bit [13:8] 0: Supplies the clock to the corresponding module 1: Stops the clock supply to the corresponding module [13]: MMCIF, [12]: FLCTL, [11]: RTC, [10]: TMU channels 0 to 2, [9]: TMU channels 3 to 5, [8]: CMT ...
Page 698: Sleep Mode
Section 17 Power-Down Mode 17.4 Sleep Mode 17.4.1 Transition to Sleep mode A transition to the sleep mode is made by executing the SLEEP instruction in the program execution state. Although the CPU stops operating after execution of the SLEEP instruction, the contents of the CPU registers are held.
Page 699: Module Standby State
Section 17 Power-Down Mode 17.5 Module Standby State This LSI supports the module standby state, where the clock supplied to on-chip modules is stopped. 17.5.1 Transition to Module Standby Mode Setting a corresponding bit in the standby control register (MSTPCR) to 1 will stop the clock supply.
Page 700: Ddr-Sdram Power Supply Backup
Section 17 Power-Down Mode 17.6 DDR-SDRAM Power Supply Backup 17.6.1 Self-Refresh and Initialization To preserve the contents of the DDR-SDRAM with battery backup, make sure that the DDR- SDRAM is in the self-refresh mode before turning off the system power supply. When the system power supply is turned on, whether initialization of the DDR-SDRAM and cancellation of the self- refresh mode is needed will depend on whether the DDR-SDRAM has been in self-refresh mode or has not been initialized.
Page 701: Ddr-Sdram Backup Sequence When Turning Off System Power Supply
Section 17 Power-Down Mode 17.6.2 DDR-SDRAM Backup Sequence when Turning Off System Power Supply The sequence when the system power supply is turned off is shown below. Figure 17.1 shows the sequence of a transition to the self-refresh mode to turn off the system power supply.
Page 702: Figure 17.2 Sequence For Turning Off System Power Supply In Self-Refresh Mode
Section 17 Power-Down Mode Time Processing Command SDRAM State Performs auto-refresh at regular intervals High Confirm that traffic to DDRIF by on-chip peripheral modules is completed (REFA/NOP) Set SCR to issue PREALL and REFA commands Enters idle state after refreshing once PREALL REFA...
Page 703: Rtc Power Supply Backup
Section 17 Power-Down Mode 17.7 RTC Power Supply Backup 17.7.1 Transition to RTC Power Supply Backup To turn on the RTC battery backup with the system power supply turned off, assert the XRTCSTBI signal before the voltage of the VDD (1.25V) power supply starts to drop. This function can be used to reduce the VDD current.
Page 704: Figure 17.3 Sequence For Turning System Power Supply On/Off
Section 17 Power-Down Mode System power supply System power supply turned off turned on VDD-RTC RTC power supply backup canceled XRTCSTBI min 1 ms min 1 ms Power-on reset canceled PRESET (1) Power-on oscillation settling time (2) Internal reset delay time to the RTC Figure 17.3 Sequence for Turning System Power Supply On/Off Rev.1.00 Dec.
Page 705: Mode Transitions
Section 17 Power-Down Mode 17.8 Mode Transitions Figure 17.4 shows the mode transitions. Power-off state Multiplication ratio change DDR-SDRAM power supply backup Normal operation Sleep RTC power supply backup Module standby (1) Power-on oscillation settling time Figure 17.4 Mode Transition Diagram Rev.1.00 Dec.
Page 706: Status Pin Change Timing
Section 17 Power-Down Mode 17.9 STATUS Pin Change Timing 17.9.1 In Reset Refer to section 16.5, Status Pin Change Timing during Reset. 17.9.2 In Sleep Figure 17.5 shows the state of output pins in sleep mode. Interrupt request CLKOUT IRQOUT STATUS[1:0] LL (Normal) HL (Sleep)
Page 707: Section 18 Timer Unit (Tmu)
Section 18 Timer Unit (TMU) Section 18 Timer Unit (TMU) This LSI includes an on-chip 32-bit timer unit (TMU), which has six channels (channels 0 to 5). 18.1 Features The TMU has the following features. • Auto-reload type 32-bit down-counter provided for each channel •...
Page 708: Figure 18.1 Block Diagram Of Tmu
Section 18 Timer Unit (TMU) Figure 18.1 shows a block diagram of the TMU. TOCR TSTR0 TCLK Channel 0, 1 TCLK controller Clock controller RTCCLK TCOR Interrupt TUNI0 controller TCNT TUNI1 Channel 2 Clock controller TCOR Interrupt TUNI2 TCNT controller ICPI2 TCPR TSTR1...
Page 709: Input/Output Pins
Section 18 Timer Unit (TMU) 18.2 Input/Output Pins Table 18.1 shows the TMU pin configuration. Table 18.1 Pin Configuration Pin Name Function Description TCLK* Clock input/output Channel 0, 1 and 2 external clock input pin/channel 2 input capture control input pin/RTC output pin (shared with RTC) Note: This pin is multiplexed with the LBSC and GPIO pins.
Page 710: Register Descriptions
Section 18 Timer Unit (TMU) 18.3 Register Descriptions Table 18.2 shows the TMU register configuration. Table 18.3 shows the register states in each processing mode. Table 18.2 Register Configuration Sync Channel Register Name Abbrev. R/W P4 Address Area 7 Address Size Clock 0, 1, 2 Timer output control register...
Page 711: Table 18.3 Register States In Each Processing Mode
Section 18 Timer Unit (TMU) Table 18.3 Register States in Each Processing Mode Power-on Manual Reset Reset by by WDT/ Sleep by PRESET Pin/ Multiple SLEEP Module Channel Register Name Abbrev. WDT/H-UDI Exception Instruction Standby 0, 1, 2 Timer output control register TOCR H'00 H'00 Retained...
Page 712: Timer Output Control Register (Tocr)
Section 18 Timer Unit (TMU) 18.3.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin.
Page 713: Timer Start Register (Tstr0, Tstr1)
Section 18 Timer Unit (TMU) 18.3.2 Timer Start Register (TSTR0, TSTR1) TSTR is an 8-bit readable/writable register that specifies whether TCNT in each channel is operated or stopped. • TSTR0 BIt: — — — — — STR2 STR1 STR0 Initial value: R/W: Initial Bit Name...
Page 714 Section 18 Timer Unit (TMU) • TSTR1 BIt: — — — — — STR5 STR4 STR3 Initial value: R/W: Initial Bit Name Value Description 7 to 3 — All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 715: Timer Constant Register (Tcorn) (N = 0 To 5)
Section 18 Timer Unit (TMU) 18.3.3 Timer Constant Register (TCORn) (n = 0 to 5) The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value.
Page 716: Timer Control Registers (Tcrn) (N = 0 To 5)
Section 18 Timer Unit (TMU) 18.3.5 Timer Control Registers (TCRn) (n = 0 to 5) The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating TCNT underflow is set to 1.
Page 717 Section 18 Timer Unit (TMU) Initial Bit Name Value Description ICPE1* Input Capture Control ICPE0* These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used.
Page 718: Input Capture Register 2 (Tcpr2)
Section 18 Timer Unit (TMU) Initial Bit Name Value Description TPSC2 Timer Prescaler 2 to 0 TPSC1 These bits select the TCNT count clock. TPSC0 000: Counts on Pck/4 001: Counts on Pck/16 010: Counts on Pck/64 011: Counts on Pck/256 100: Counts on Pck/1024 101: Setting prohibited 110: Counts on on-chip RTC output clock...
Page 719: Operation
Section 18 Timer Unit (TMU) 18.4 Operation Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). Each TCNT performs count-down operation. The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function.
Page 720: Figure 18.2 Example Of Count Operation Setting Procedure
Section 18 Timer Unit (TMU) Select operation Select the count clock with the TPSC2 to TPSC0 bits Select count clock in TCR. When the external clock (TCLK) is selected, specify the external clock edge with the CKEG1 and CKEG0 bits in TCR. Underflow interrupt Specify whether an interrupt is to be generated on generation setting...
Page 721: Figure 18.3 Tcnt Auto-Reload Operation
Section 18 Timer Unit (TMU) Auto-Reload Count Operation Figure 18.3 shows the TCNT auto-reload operation. TCNT value TCOR value set in TCNT on underflow TCOR H'0000 0000 Time STR0 to STR5 Figure 18.3 TCNT Auto-Reload Operation TCNT Count Timing • Operating on internal clock Any of five count clocks (Pck/4, Pck/16, Pck/64, Pck/256, or Pck/1024) scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR.
Page 722: Figure 18.5 Count Timing When Operating On External Clock
Section 18 Timer Unit (TMU) • Operating on external clock In channels 0, 1, and 2, the external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR. The detected edge (rising, falling, or both edges) can be selected with the CKEG1 and CKEG0 bits in TCR.
Page 723: Input Capture Function
Section 18 Timer Unit (TMU) 18.4.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use bits TPSC2 to TPSC0 in TCR to set an internal clock as the timer operating clock. 2.
Page 724: Interrupts
Section 18 Timer Unit (TMU) 18.5 Interrupts There are seven TMU interrupt sources: underflow interrupts and the input capture interrupt when the input capture function is used. Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when both the UNF bit and the interrupt enable bit (UNIE) for that channel are set to 1.
Page 725: Usage Notes
Section 18 Timer Unit (TMU) 18.6 Usage Notes 18.6.1 Register Writes When writing to a TMU register, timer count operation must be stopped by clearing the start bit (STR5 to STR0) for the relevant channel in TSTR. Note that TSTR can be written to, and the UNF and ICPF bits in TCR can be cleared while the count is in progress.
Page 726 Section 18 Timer Unit (TMU) Rev.1.00 Dec. 13, 2005 Page 676 of 1286 REJ09B0158-0100...
Page 727: Section 19 Compare Match Timer (Cmt)
Section 19 Compare Match Timer (CMT) Section 19 Compare Match Timer (CMT) This LSI includes the 32-bit compare match timer, which has four channels (channel 0 to 3). There are two mode of operation: one is four channels 32-bit free running timer mode that has common 32-bit free running time base and the other is four channels 16-bit timer/counter mode that operates as four channels timer or counter individually.
Page 728: Figure 19.1 Block Diagram Of Cmt
Section 19 Compare Match Timer (CMT) Figure 19.1 shows a block diagram of the CMT. 32-bit timer Mode CMTCFG controller Clock controller CMTCTL CMTFRT Channel 0, 1 Clock CMTCHn controller CMT_CTR0 controller CMTCHn CMT_CTR1 Prescaler Interrupt CMTCHn detection 32-bit timer To each channel Channel 2, 3 Clock...
Page 729: Input/Output Pins
Section 19 Compare Match Timer (CMT) 19.2 Input/Output Pins Table 19.1 shows the CMT pin configuration. Table 19.1 Pin Configuration Pin Name Function Description CMT_CTR0* Channel 0 timer/counter 32-bit free-running timer or 16-bit input/output timer/counter input capture input, output compare output or external CMT_CTR1* Channel 1 timer/counter trigger input.
Page 730: Table 19.3 Register States Of Cmt In Each Processing Mode
Section 19 Compare Match Timer (CMT) Table 19.3 Register States of CMT in Each Processing Mode Power-on Manual Reset by Reset by PRESET WDT/ Sleep Pin/WDT/ Multiple by SLEEP Module Register Name Abbreviation H-UDI Exception Instruction Standby Common Configuration register CMTCFG H'0000 0000 H'0000 0000...
Page 731: Configuration Register (Cmtcfg)
Section 19 Compare Match Timer (CMT) 19.3.1 Configuration Register (CMTCFG) CMTCFG is a 32-bit readable/writable register. The possible operations for a pin are timer compare, timer input capture, up or down count, and capture input, where one pin is used for capture while the second is used to enable the count.
Page 732 Section 19 Compare Match Timer (CMT) Initial Bit Name Value Description 11, 10 All 0 Channel 1 Pin Active Control [Input capture mode] 00: Setting prohibited* 01: Edge detection on rising edge of CMT_CTR1 pin input 10: Edge detection on falling edge of CMT_CTR1 pin input 11: Edge detection on either edge of CMT_CTR1 pin input...
Page 733 Section 19 Compare Match Timer (CMT) Initial Bit Name Value Description 7, 6 — All 0 Reserved These bits are always read as 0. The write value should always be 0. FRTM Free-Running Timer Mode Determines whether the timer works as a common 32- bit free-running timer or four independent 16-bit timers/counters.
Page 734: Free-Running Timer (Cmtfrt)
Section 19 Compare Match Timer (CMT) 19.3.2 Free-Running Timer (CMTFRT) CMTFRT is a 32-bit read only register that is the common time base of the capture/compare register (channel 0, 1) and compare register (channel 2, 3) in 32-bit free-running timer (FRT) mode.
Page 735 Section 19 Compare Match Timer (CMT) Initial Bit Name Value Description Channel 3 to 0 timer enable Enables the counting of each of the 16-bit counters. If these bits are inactive when operating in timer mode or in counter mode, the counters are reset to 0. In updown-counter mode, channel 1 needs to be disabled (TE1 = 0).
Page 736 Section 19 Compare Match Timer (CMT) Initial Bit Name Value Description 15, 14 All 0 Timer Clock Control Channel 3 These bits specify the clock input for the 16-bit timer in channel 3.* 00: Clock for timer 3 is 1/32 of peripheral clock (Pck) 01: Clock for timer 3 is 1/128 of peripheral clock (Pck) 10: Clock for timer 3 is 1/512 of peripheral clock (Pck) 11: Clock for timer 3 is 1/1024 of peripheral clock (Pck)
Page 737 Section 19 Compare Match Timer (CMT) Initial Bit Name Value Description 9, 8 All 0 Free-Running Timer Clock Control This clock is used for the 32-bit free-running timer (FRT) and also for the 16-bit timer/counter in channel 0.* 00: Clock for FRT and timer 0 is 1/32 of peripheral clock (Pck) 01: Clock for FRT and timer 0 is 1/128 of peripheral clock (Pck)
Page 738: Interrupt Status Register (Cmtirqs)
Section 19 Compare Match Timer (CMT) 19.3.4 Interrupt Status Register (CMTIRQS) CMTIRQS, once set, can only be cleared by a write. Writing 0 to these bits clears the interrupt status bits. These conditions only create an interrupt if the relevant interrupt enable bit is set. Bit: —...
Page 739: Channels 0 To 3 Time Registers (Cmtch0T To Cmtch3T)
Section 19 Compare Match Timer (CMT) 19.3.5 Channels 0 to 3 Time Registers (CMTCH0T to CMTCH3T) In output compare mode, these registers specify the value to be compared with the free-running timer. In input capture mode, this register stores the free-running timer values or the 16-bit timer values on the active edge of the input.
Page 740: Channels 0 To 3 Counters (Cmtch0C To Cmtch3C)
Section 19 Compare Match Timer (CMT) 19.3.7 Channels 0 to 3 Counters (CMTCH0C to CMTCH3C) Each channel register indicates the current value of the timer/counter. Writing to this register, it can be set the timer counter. When reading this register, the timer/counter value is not affected. Bit: —...
Page 741: Figure 19.2 Edge Detection (Example Of Rising Edge)
Section 19 Compare Match Timer (CMT) 19.4 Operation The CMT has two operation modes: one is four channels free-running timer that operates with the common time base of 32-bit free-running timer operating between approximately 1.5MHz (Pck/32 selected at Pck = 50MHz) to 30kHz (Pck/1024 selected at Pck = 33MHz). The other is 16-bit timer/counter that operating as two channels 16-bit timer/counter and two channels 16-bit timer.
Page 742: Figure 19.3 32-Bit Timer Mode: Input Capture (Channel 1 And Channel 0)
Section 19 Compare Match Timer (CMT) 19.4.2 32-Bit Timer: Input Capture When rising edge or falling edge is detected while the timer CMTFRT is operating, the value of CMTFRT is captured in the corresponding CMTCHnT (n = 1, 0). Then the IEn flag in CMTIRQS is set to 1 and the interrupt is generated when the IEEn bit in CMTCTL is set to 1.
Page 743: Table 19.4 32-Bit Timer Mode: Example Of Input Capture Setting
Section 19 Compare Match Timer (CMT) Table 19.4 32-bit Timer Mode: Example of Input Capture Setting Register Settings CMTCFG 31 t o 12 All 0 11 to 8 Arbitrary value (pin setting of each channel) 7, 6 All 0 1 (32-bit free-running timer) 4 to 0 All 0 CMTCTL...
Page 744: Figure 19.5 Cmt_Ctrn Assert Timing (Channel 0 And 1)
Section 19 Compare Match Timer (CMT) CMTFRT value H'FFFF FFFF CMTCHnST + H'8000 0000 CMTCHnST CMTCHnT H'0000 0000 Time Start count-up FRTM bit CMT_CTRn output ICn flag STCn bit Output remains active until the Output remains active for half channel n stop time value the total time of the FRT is reached Figure 19.5 CMT_CTRn Assert Timing (channel 0 and 1)
Page 745: Figure 19.7 32-Bit Timer Mode: Output Compare Operation Timing (Example Of High Output In Active And Not Active By Cmtchnst)
Section 19 Compare Match Timer (CMT) operation clock N + 1 N + 2 CMTFRT CMT_CTRn output CMTCHnT N + 1 CMTCHnST ICn flag Figure 19.7 32-bit Timer Mode: Output Compare Operation Timing (Example of High output in Active and Not Active by CMTCHnST) operation clock N + H'8000 0000 N + H'8000 0001...
Page 746: Table 19.5 32-Bit Timer Mode: Example Of Output Compare Setting
Section 19 Compare Match Timer (CMT) Table 19.5 32-bit Timer Mode: Example of Output Compare Setting Register Settings CMTCFG 31 t o 12 All 0 11 to 8 Arbitrary value (pin setting of each channel) 7, 6 All 0 1 (32-bit free-running timer) 4 to 0 All 0 CMTCTL...
Page 747: Figure 19.9 16-Bit Timer Mode: Input Capture (Channel 1 And Channel 0)
Section 19 Compare Match Timer (CMT) 19.4.4 16-Bit Timer: Input Capture When rising edge or falling edge is detected while the timer CMTCH0C is operating, the value of CMTCHnC (n = 0, 1) is captured in the corresponding CMTCHnT (n = 1, 0). Then the IEn flag in CMTIRQS is set to 1 and the interrupt is generated when the IEEn bit in CMTCTL is set to 1.
Page 748: Figure19.10 16-Bit Timer Mode: Input Capture Operation Timing
Section 19 Compare Match Timer (CMT) CMTCH0T operation clock N − 1 N + 1 CMTCHnC H'0000 CMT_CTRn input CMTCHnT IEn flag Figure19.10 16-Bit Timer Mode: Input Capture Operation Timing Table 19.6 16-bit Timer Mode: Example of Input Capture Setting Register Settings CMTCFG...
Page 749: Figure 19.11 16-Bit Timer Mode: Output Compare (Cmt_Ctr Pins Are Available For Channel 1 And Channel 0)
Section 19 Compare Match Timer (CMT) 19.4.5 16-Bit Timer: Output Compare When the value of CMTCHnC (n = 1, 0) matches the lower 16-bit of CMTCHnT while the timer CMTCH0C is operating, the output is inverted. Then the ICn flag in CMTIRQS is set to 1 and the interrupt is generated when the ICEn bit in CMTCTL is set to 1.
Page 750: Figure19.12 16-Bit Timer Mode: Output Compare Operation Timing
Section 19 Compare Match Timer (CMT) CMTCHnC operation clock N − 1 N + 1 H'0000 CMTCHnC CMT_CTRn output CMTCHnT ICn flag Figure19.12 16-Bit Timer Mode: Output Compare Operation Timing Table 19.7 16-bit Timer Mode: Example of Output Compare Setting Register Settings CMTCFG...
Page 751: Figure 19.13 Up-Counter Mode (Channel 1 And Channel 0)
Section 19 Compare Match Timer (CMT) 19.4.6 Counter: Up-counter When rising edge or falling edge of the CMT_CTR input signal is detected at the rising edge of each channel operation clock, the channel counter CMTCHnC value is captured in the corresponding CMTCHnT (n = 1, 0) and that counter is counted up.
Page 752: Table 19.8 Setting Example Of Up-Counter Mode
Section 19 Compare Match Timer (CMT) Table 19.8 Setting Example of Up-counter Mode Register Settings CMTCFG 31 t o 12 All 0 11 to 8 Arbitrary value (pin setting of each channel) 7, 6 All 0 0 (16-bit timer/counter) 4 to 2 All 0 1, 0 10 (Up-counter mode setting of all channels)
Page 753: Figure 19.15 Updown-Counter Mode (Only Channel 0)
Section 19 Compare Match Timer (CMT) 19.4.7 Counter: Updown-counter Channel 0 can be used as an updown-counter. However, the CMT_CRT1 pin is to connect to the channel 0, the channel 1 timer/counter needs to be disabled. When rising edge or falling edge of the CMT_CTR input signal is detected at the rising edge of the channel 0 operation clock, the channel counter CMTCH0C is counted up or down.
Page 754: Table 19.9 Setting Example Of Updown-Counter Mode
Section 19 Compare Match Timer (CMT) Table 19.9 Setting Example of Updown-counter Mode Register Settings CMTCFG 31 t o 12 All 0 11 to 8 Arbitrary value (pin setting of each channel) 7, 6 All 0 0 (16-bit timer/counter) 4 to 2 All 0 1, 0 11 (Updown-counter mode setting of channel 0)
Page 755: Figure 19.17 Rotary Switch Operation Count-Up Timing
Section 19 Compare Match Timer (CMT) 19.4.8 Counter: Rotary Switch Operation of Updown-counter The Updown-counter can operate as a rotary switch. When the falling edge of the control pin is detected and then the data pin input level is low, the counter is counted up, or the data pin input level is high, the counter is counted down.
Page 756: Table 19.10 Setting Example Of Updown-Counter Mode
Section 19 Compare Match Timer (CMT) Table 19.10 Setting Example of Updown-counter Mode Register Settings CMTCFG 31 t o 17 All 0 All 1 (rotary switch operation setting of channel 0) 15 to 6 All 0 0 (16-bit timer/counter) 4 to 2 All 0 1, 0 11 (Updown-counter mode setting of channel 0)
Page 757: Section 20 Realtime Clock (Rtc)
Section 20 Realtime Clock (RTC) Section 20 Realtime Clock (RTC) The SH7780 includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 20.1 Features The RTC has the following features. • Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years.
Page 758: Figure 20.1 Block Diagram Of Rtc
Section 20 Realtime Clock (RTC) 20.1.1 Block Diagram Figure 20.1 shows a block diagram of the RTC. RTCCLK XTAL2 EXTAL2 16.384 kHz 32.768 kHz crystal oscillator RTC operation Prescaler control unit 128 Hz RCR1 RCR2 Counter unit RCR3 Interrupt R64CNT control unit RSECCNT RMINCNT...
Page 759: Table 20.1 Rtc Pins
Section 20 Realtime Clock (RTC) 20.2 Input/Output Pins Table 20.1 shows the RTC pins. Table 20.1 RTC Pins Pin Name Function Description EXTAL2 RTC oscillator crystal pin Input Connects crystal to RTC oscillator XTAL2 RTC oscillator crystal pin Output Connects crystal to RTC oscillator TCLK* TMU clock input/RTC clock TMU external clock input pin/input capture...
Page 760: Table 20.2 Rtc Registers
Section 20 Realtime Clock (RTC) 20.3 Register Descriptions Table 20.2 shows the RTC registers. Table 20.3 shows the register states in each processing mode. Table 20.2 RTC Registers Access Sync Register Name Abbreviation R/W P4 Address Area 7 Address Size Clock 64 Hz counter R64CNT...
Page 761: Table 20.3 Register States Of Rtc In Each Processing Mode
Section 20 Realtime Clock (RTC) Table 20.3 Register States of RTC in Each Processing Mode Power-on Register Name Abbreviation Initial Value Reset Manual Reset Sleep 64 Hz counter R64CNT Undefined Counts Counts Counts Second counter RSECCNT Undefined Counts Counts Counts Minute counter RMINCNT Undefined...
Page 762: Hz Counter (R64Cnt)
Section 20 Realtime Clock (RTC) 20.3.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 Hz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.
Page 763: Minute Counter (Rmincnt)
Section 20 Realtime Clock (RTC) 20.3.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter.
Page 764: Day-Of-Week Counter (Rwkcnt)
Section 20 Realtime Clock (RTC) 20.3.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter.
Page 765: Day Counter (Rdaycnt)
Section 20 Realtime Clock (RTC) 20.3.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter.
Page 766: Month Counter (Rmoncnt)
Section 20 Realtime Clock (RTC) 20.3.7 Month Counter (RMONCNT) RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded month value in the RTC. It counts on the carry generated once per month by the day counter.
Page 767: Second Alarm Register (Rsecar)
Section 20 Realtime Clock (RTC) 20.3.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value.
Page 768: Hour Alarm Register (Rhrar)
Section 20 Realtime Clock (RTC) 20.3.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value.
Page 769: Day Alarm Register (Rdayar)
Section 20 Realtime Clock (RTC) Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. BIt: — — — — Day-of-week code Initial value: — — —...
Page 770: Month Alarm Register (Rmonar)
Section 20 Realtime Clock (RTC) 20.3.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value.
Page 771: Rtc Control Register 1 (Rcr1)
Section 20 Realtime Clock (RTC) 20.3.16 RTC Control Register 1 (RCR1) RCR1 is an 8-bit readable/writable register containing a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags. The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other than CIE and AIE is undefined.
Page 772 Section 20 Realtime Clock (RTC) Initial Bit Name Value Description Carry Interrupt Enable Flag Enables or disables interrupt generation when the carry flag (CF) is set to 1. 0: Carry interrupt is not generated when CF flag is set to 1 1: Carry interrupt is generated when CF flag is set to 1 Alarm Interrupt Enable Flag Enables or disables interrupt generation when the...
Page 773: Rtc Control Register 2 (Rcr2)
Section 20 Realtime Clock (RTC) Initial Bit Name Value Description Undefined R/W Alarm Flag Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values 0: Alarm registers and counter values do not match (Initial value)
Page 774 Section 20 Realtime Clock (RTC) Initial Bit Name Value Description Undefined R/W Periodic Interrupt Flag Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. 0: Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF...
Page 775 Section 20 Realtime Clock (RTC) Initial Bit Name Value Description 30-Second Adjustment Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute.
Page 776: Rtc Control Register (Rcr3)
Section 20 Realtime Clock (RTC) 20.3.18 RTC Control Register (RCR3) RCR3 is readable/writable register that specifies enable or disable the alarm function of RYRCNT that is the RTC's BCD-coded year-value counter. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value.
Page 777: Operation
Section 20 Realtime Clock (RTC) 20.4 Operation Examples of the use of the RTC are shown below. 20.4.1 Time Setting Procedures Figure 20.2 shows examples of the time setting procedures. Set RCR2.RESET to 1. Stop clock Clear RCR2.START to 0. Reset frequency divider Set second/minute/hour/day/ In any order.
Page 778: Time Reading Procedures
Section 20 Realtime Clock (RTC) 20.4.2 Time Reading Procedures Figure 20.3 shows examples of the time reading procedures. Clear RCR1.CIE to 0. Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag is not cleared).
Page 779: Alarm Function
Section 20 Realtime Clock (RTC) If a carry occurs or being the carry ready period (RCR1.CRF = 1) while the time is being read, the correct time will not be obtained and the read must be repeated. The procedure for reading the time without using interrupts is shown in figure 20.3 (a), and the procedure using carry interrupts in figure 20.3 (b).
Page 780: Interrupts
Section 20 Realtime Clock (RTC) 20.5 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1.
Page 781: Figure 20.5 Example Of Crystal Oscillator Circuit Connection
Section 20 Realtime Clock (RTC) SH7780 EXTAL2 XTAL2 VDD-RTC VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2.
Page 782: Interrupt Source And Request Generating Order
Section 20 Realtime Clock (RTC) 20.6.3 Interrupt source and request generating order If it occurs complex interrupt source of alarm interrupts (ATI), periodic interrupts (PFI), and carry interrupts (CUI) at the same time, the RTC generates interrupt request as shown in figure 20.6. (50MHz) carry, periodical, and alarm interrupt EXTAL2...
Page 783: Section 21 Serial Communication Interface With Fifo (Scif)
Section 21 Serial Communication Interface with FIFO (SCIF) Section 21 Serial Communication Interface with FIFO (SCIF) This LSI is equipped with a 2-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform both asynchronous and clocked synchronous serial communications.
Page 784 Section 21 Serial Communication Interface with FIFO (SCIF) • Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling continuous serial data transmission and reception.
Page 785: Figure 21.1 Block Diagram Of Scif
Section 21 Serial Communication Interface with FIFO (SCIF) Module data bus SCFRDRn SCFTDRn SCSMRn SCBRRn 64-stage 64-stage SCLSRn SCTFDRn SCRFDRn SCIFn_RXD SCRSRn SCTSRn SCFCRn Pck/4 Baud rate generator SCFSRn Pck/16 Pck/64 SCSCRn SCSPTRn SCRERn Transmit/receive control SCIFn_TXD Clock Parity generation Parity check External clock SCIFn_SCK...
Page 786: Figure 21.2 Scif0_Rts Pin (Only In Channel 0)
Section 21 Serial Communication Interface with FIFO (SCIF) Figures 21.2 to 21.6 show block diagrams of the I/O ports in SCIF. Reset RTSIO Peripheral bus SPTRW Reset SCIF0_RTS RTSDT Modem control SPTRW enable signal* SCIF_RTS signal SPTRR SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF0_RTS pin function is designated as modem control by the MCE bit in SCFCR.
Page 787: Figure 21.4 Scifn_Sck Pin (N = 0, 1)
Section 21 Serial Communication Interface with FIFO (SCIF) Reset SCKIO Peripheral bus SPTRW Reset SCIFn_CLK SCKDT SPTRW Clock output enable signal * Serial clock output signal * Serial clock input signal * Serial input enable signal * SPTRR SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIFn_CLK pin function is designated as internal clock output or external clock input by the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Page 788: Figure 21.6 Scifn_Rxd Pin (N = 0, 1)
Section 21 Serial Communication Interface with FIFO (SCIF) SCIFn_RXD Serial receive data Peripheral bus SPTRR SPTRR: Read from SCSPTR Figure 21.6 SCIFn_RXD Pin (n = 0, 1) Rev.1.00 Dec. 13, 2005 Page 738 of 1286 REJ09B0158-0100...
Page 789: Input/Output Pins
Section 21 Serial Communication Interface with FIFO (SCIF) 21.2 Input/Output Pins Table 21.1 shows the SCIF pin configuration. Table 21.1 Pin Configuration Pin Name Function Description SCIF0_SCK Channel 0 serial clock pin Clock input/output SCIF0_RXD Channel 0 receive data pin Input Receive data input SCIF0_TXD...
Page 790: Register Descriptions
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3 Register Descriptions Table 21.2 shows the register configuration. Table 21.3 shows the register states in each processing mode. Table 21.2 Register Configuration Sync Register Name Abbrev. P4 Address Area 7 Address Size Clock Serial mode register 0...
Page 791: Table 21.3 Register States Of Scif In Each Processing Mode
Section 21 Serial Communication Interface with FIFO (SCIF) Table 21.3 Register States of SCIF in Each Processing Mode Power-on Reset Manual Reset by Sleep by by PRESET Pin/ WDT/Multiple SLEEP Module Register Name Abbrev. WDT/H-UDI Exception Instruction Standby Serial mode register 0 SCSMR0 H'0000 H'0000...
Page 792: Receive Shift Register (Scrsr)
Section 21 Serial Communication Interface with FIFO (SCIF) Since the register functions, pin functions, and interrupt requests are the same in each channel except for the modem control, the channel number n (n = 0, 1) is omitted in the description below. 21.3.1 Receive Shift Register (SCRSR) SCRSR is the register used to receive serial data.
Page 793: Transmit Shift Register (Sctsr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.3 Transmit Shift Register (SCTSR) SCTSR is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the SCIF_TXD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission started, automatically.
Page 794: Serial Mode Register (Scsmr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.5 Serial Mode Register (SCSMR) SCSMR is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR can always be read from and written to by the CPU. Bit: ...
Page 795 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Parity Enable In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking is performed in reception. In clocked synchronous mode, parity bit addition and checking is disabled regardless of the PE bit setting.
Page 796 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description STOP Stop Bit Length In asynchronous mode, selects 1 or 2 bits as the stop bit length. The stop bit setting is valid only in asynchronous mode. Since the stop bit is not added in clocked synchronous mode, the STOP bit setting is invalid.
Page 797: Serial Control Register (Scscr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.6 Serial Control Register (SCSCR) SCSCR is a register used to enable/disable transmission/reception by SCIF, serial clock output, interrupt requests, and to select transmission/reception clock source for the SCIF. SCSCR can always be read from and written to by the CPU. Bit: ...
Page 798 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Receive Interrupt Enable Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1.
Page 799 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Receive Enable Enables or disables the start of serial reception by the SCIF. Serial reception is started when a start bit is detected in this state in asynchronous mode or a synchronization clock is input while the RE bit is set to 1.
Page 800 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description CKE1 Clock Enable 1, 0 CKE0 These bits select the SCIF clock source and whether to enable or disable the clock output from the SCIF_SCK pin. The CKE1 and CKE0 bits are used together to specify whether the SCIF_SCK pin functions as a serial clock output pin or a serial clock input pin.
Page 801: Serial Status Register N (Scfsr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.7 Serial Status Register n (SCFSR) SCFSR is a 16-bit register that consists of status flags that indicate the operating status of the SCIF. SCFSR can be read from or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR.
Page 802 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/W* Receive Error Indicates that a framing error or parity error occurred during reception. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0.
Page 803 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description TDFE R/W* Transmit FIFO Data Empty Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in SCFCR, and new transmit data can be written to SCFTDR.
Page 804 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/W* Break Detect Indicates that a receive data break signal has been detected. 0: A break signal has not been received [Clearing conditions] • Power-on reset or manual reset •...
Page 805 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Parity Error In asynchronous mode, indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR. 0: There is no parity error that is to be read from SCFRDR [Clearing conditions] •...
Page 806 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/W* Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR.
Page 807 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/W* Receive Data Ready In asynchronous mode, indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR, and no further data has arrived for at least 15 etu after the stop bit of the last data received.
Page 808: Bit Rate Register N (Scbrr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.8 Bit Rate Register n (SCBRR) SCBRR is an 8-bit register that set the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR. SCBRR can always be read from and written to by the CPU.
Page 809: Fifo Control Register N (Scfcr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.9 FIFO Control Register n (SCFCR) SCFCR performs data count resetting and trigger data number setting for transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can always be read from and written to by the CPU. Bit: ...
Page 810 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description RTRG1 Receive FIFO Data Number Trigger RTRG0 These bits are used to set the number of receive data bytes that sets the RDF flag in SCFSR. The RDF flag is set when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown below.
Page 811 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description TFCL Transmit FIFO Data Count Register Clear Clears the transmit FIFO data count register to 0. 0: Clear operation disabled 1: Clear operation enabled Note: A reset operation is performed in the event of a power-on reset or manual reset.
Page 812: Transmit Fifo Data Count Register N (Sctfdr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.10 Transmit FIFO Data Count Register n (SCTFDR) SCTFDR is a 16-bit register that indicates the number of transmit data bytes stored in SCFTDR. SCTFDR can always be read from the CPU. Bit: ...
Page 813: Receive Fifo Data Count Register N (Scrfdr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.11 Receive FIFO Data Count Register n (SCRFDR) SCRFDR is a 16-bit register that indicates the number of receive data bytes stored in SCFRDR. SCRFDR can always be read from the CPU. Bit: ...
Page 814: Serial Port Register N (Scsptr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.12 Serial Port Register n (SCSPTR) SCSPTR is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins at all times. Input data can be read from the SCIF_RXD pin, output data written to the SCIF_TXD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0.
Page 815 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Serial Port SCIF0_RTS Port Data RTSDT* — Specifies the serial port SCIF0_RTS pin input/output data. Input or output is specified by the RTSIO bit. In output mode, the RTSDT bit value is output to the SCIF0_RTS pin.
Page 816 Section 21 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description SCKDT — Serial Port Clock Port Data Specifies the serial port SCIF_SCK pin input/output data. Input or output is specified by the SCKIO bit. In output mode, the SCKDT bit value is output to the SCIF_SCK pin.
Page 817: Line Status Register N (Sclsr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.13 Line Status Register n (SCLSR) Bit:                ORER Initial value: R/W: R/W* Note: * Only 0 can be written, to clear the flag. Initial Bit Name Value...
Page 818: Serial Error Register N (Screr)
Section 21 Serial Communication Interface with FIFO (SCIF) 21.3.14 Serial Error Register n (SCRER) SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR. SCRER can always be read from the CPU. Bit: ...
Page 819: Operation
Section 21 Serial Communication Interface with FIFO (SCIF) 21.4 Operation 21.4.1 Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character and in synchronous mode, in which synchronization is achieved with clock pulses. For details on asynchronous mode, see section 21.4.2, Operation in Asynchronous Mode.
Page 820: Table 21.5 Scsmr Settings For Serial Transfer Format Selection
Section 21 Serial Communication Interface with FIFO (SCIF) Clocked Synchronous Mode: • Data length: Fixed at 8 bits • LSB first for data transmission/reception • Detection of overrun errors during reception • Choice of internal or external clock input from SCIF_SCK pin as SCIF clock source When internal clock (peripheral clock: Pck) is selected: The SCIF operates on the baud rate generator clock and a serial clock is output to external devices.
Page 821: Table 21.6 Scsmr And Scscr Settings For Scif Clock Source Selection
Section 21 Serial Communication Interface with FIFO (SCIF) Table 21.6 SCSMR and SCSCR Settings for SCIF Clock Source Selection SCSMR SCSCR Settings Bit 7: Bit 1: Bit 0: Clock CKE1 CKE0 Mode Source SCK Pin Function Asynchronous Internal SCIF does not use SCIF_SCK pin mode Outputs clock with frequency of 16 times the bit rate...
Page 822: Operation In Asynchronous Mode
Section 21 Serial Communication Interface with FIFO (SCIF) 21.4.2 Operation in Asynchronous Mode In asynchronous mode, a character that consists of data with a start bit indicating the start of communication and a stop bit indicating the end of communication is transmitted or received. In this mode, serial communication is performed with synchronization achieved character by character.
Page 823: Table 21.7 Serial Transfer Formats (Asynchronous Mode)
Section 21 Serial Communication Interface with FIFO (SCIF) Data Transfer Format Table 21.7 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR settings. Table 21.7 Serial Transfer Formats (Asynchronous Mode) SCSMR Settings Serial Transfer Format and Frame Length CHR PE...
Page 824 Section 21 Serial Communication Interface with FIFO (SCIF) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Page 825: Figure 21.8 Sample Scif Initialization Flowchart
Section 21 Serial Communication Interface with FIFO (SCIF) Figure 21.8 shows a sample SCIF initialization flowchart. Start of initialization Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. Clear TE and RE bits in SCSCR to 0 Set the data transfer format in SCSMR.
Page 826: Figure 21.9 Sample Serial Transmission Flowchart
Section 21 Serial Communication Interface with FIFO (SCIF) Serial Data Transmission (Asynchronous Mode): Figure 21.9 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] SCIF status check and transmit data write: write: Read TDFE flag in SCFSR...
Page 827 Section 21 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR.
Page 828: Figure 21.10 Sample Scif Transmission Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 21 Serial Communication Interface with FIFO (SCIF) Figure 21.10 shows an example of the operation for transmission in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR...
Page 829: Figure 21.12 Sample Serial Reception Flowchart (1)
Section 21 Serial Communication Interface with FIFO (SCIF) Serial Data Reception (Asynchronous Mode) Figure 21.12 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. [1] Receive error handling and Start of reception break detection: Read the DR, ER, and BRK...
Page 830: Figure 21.12 Sample Serial Reception Flowchart (2)
Section 21 Serial Communication Interface with FIFO (SCIF) [1] Whether a framing error or parity error Error handling has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER ORER = 1? bits in SCFSR.
Page 831 Section 21 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3.
Page 832: Figure 21.13 Sample Scif Receive Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 21 Serial Communication Interface with FIFO (SCIF) Start Data Parity Stop Start Data Parity Stop Serial data Detect flaming error RXI interrupt Data read and RDF flag ERI interrupt request request read as 1 then cleared to generated by receive One frame 0 by RXI interrupt handler error...
Page 833: Operation In Clocked Synchronous Mode
Section 21 Serial Communication Interface with FIFO (SCIF) 21.4.3 Operation in Clocked Synchronous Mode Clocked synchronous mode, in which data is transmitted or received in synchronization with clock pulses, is suitable for fast serial communication. Since the transmitter and receiver are independent units in the SCIF, full-duplex communication can be achieved by sharing the clock.
Page 834 Section 21 Serial Communication Interface with FIFO (SCIF) Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 17.5.
Page 835: Figure 21.16 Sample Scif Initialization Flowchart
Section 21 Serial Communication Interface with FIFO (SCIF) Start of initialization Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, Clear TE and RE bits RIE, TE, and RE bits to 0. in SCSCR to 0 Set the CKE1 and CKE0 bits.
Page 836: Figure 21.17 Sample Serial Transmission Flowchart
Section 21 Serial Communication Interface with FIFO (SCIF) Serial Data Transmission (Clocked Synchronous Mode) Figure 21.17 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the...
Page 837: Figure 21.18 Sample Scif Transmission Operation In Clocked Synchronous Mode
Section 21 Serial Communication Interface with FIFO (SCIF) 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set.
Page 838: Figure 21.19 Sample Serial Reception Flowchart (1)
Section 21 Serial Communication Interface with FIFO (SCIF) Serial Data Reception (Clocked Synchronous Mode) Figure 21.19 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching the operating mode from asynchronous mode to clocked synchronous mode without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags are cleared to 0.
Page 839: Figure 21.19 Sample Serial Reception Flowchart (2)
Section 21 Serial Communication Interface with FIFO (SCIF) Error handling ORER = 1? Overrun error handling Clear ORER flag in SCLSR to 0 Figure 21.19 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF is initialized internally in synchronization with the input or output of the synchronization clock.
Page 840: Figure 21.20 Sample Scif Reception Operation In Clocked Synchronous Mode
Section 21 Serial Communication Interface with FIFO (SCIF) Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 ORER RXI interr u pt Data read from BRI interrupt request interrupt SCFRDR and RDF by overrun error flag cleared to 0 by request...
Page 841: Figure 21.21 Sample Simultaneous Serial Transmission And Reception Flowchart
Section 21 Serial Communication Interface with FIFO (SCIF) Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 21.21 shows a sample flowchart for simultaneous serial data transmission and reception. Use the following procedure for simultaneous serial transmission and reception after enabling the SCIF for both transmission and reception.
Page 842: Scif Interrupt Sources And The Dmac
Section 21 Serial Communication Interface with FIFO (SCIF) 21.5 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources in each channel: transmit-FIFO-data-empty interrupt (TXI) request, receive-error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 21.7 shows the interrupt sources and their order of priority.
Page 843: Table 21.8 Scif Interrupt Sources
Section 21 Serial Communication Interface with FIFO (SCIF) Table 21.8 SCIF Interrupt Sources Interrupt DMAC Priority on Source Activation Reset Release Description Interrupt initiated by receive error flag (ER) Not possible High Interrupt initiated by receive FIFO data full flag Possible (RDF) or receive data ready flag (DR)* Interrupt initiated by break flag (BRK) or overrun...
Page 844: Usage Notes
Section 21 Serial Communication Interface with FIFO (SCIF) 21.6 Usage Notes Note the following when using the SCIF. SCFTDR Writing and the TDFE Flag The TDFE flag in SCFSR is set when the number of transmit data bytes written in SCFTDR has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in SCFCR.
Page 845: Figure 21.22 Receive Data Sampling Timing In Asynchronous Mode
Section 21 Serial Communication Interface with FIFO (SCIF) Sending a Break Signal The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and SPB2DT in SCSPTR. This feature can be used to send a break signal. After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission), the SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark state.
Page 846: Figure 21.23 Example Of Synchronization Clock Transfer By Dmac
Section 21 Serial Communication Interface with FIFO (SCIF) Thus, the reception margin in asynchronous mode is given by formula (1). | D - 0.5 | (1 + F) × 100 % ....(1) M= (0.5 - ) - (L - 0.5) F - M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0)
Page 847: Section 22 Serial I/O With Fifo (Siof)
Section 22 Serial I/O with FIFO (SIOF) Section 22 Serial I/O with FIFO (SIOF) This LSI includes a clock-synchronized serial I/O module with FIFO (SIOF). 22.1 Features • Serial transfer 16-stage 32-bit FIFOs (transmission and reception are independent of each other) Supports 8-bit data/16-bit data/16-bit stereo audio input/output MSB first for data transmission Supports a maximum of 48-kHz sampling rate...
Page 848: Figure 22.1 Block Diagram Of Siof
Section 22 Serial I/O with FIFO (SIOF) Figure 22.1 shows a block diagram of the SIOF. SIOF interrupt transfer request request Peripheral bus (SIOFI) Bus interface Transmit Receive Control FIFO FIFO registers (32 bits ×16 (32 bits ×16 stages) stages) Receive control Transmit control data...
Page 849: Input/Output Pins
Section 22 Serial I/O with FIFO (SIOF) 22.2 Input/Output Pins The pin configuration in this module is shown in table 22.1. Table 22.1 Pin Configuration Pin Name Function Description SIOF_MCLK Master clock Input Master clock input pin SIOF_SCK Serial clock Serial clock pin (common to transmission/reception) SIOF_SYNC...
Page 850: Register Descriptions
Section 22 Serial I/O with FIFO (SIOF) 22.3 Register Descriptions Table 22.2 shows the SIOF register configuration. Table 22.3 shows the register states in each processing mode. Table 22.2 Register Configuration of SIOF Access Sync Name Abbreviation R/W P4 Address Area7 Address Size Clock...
Page 851: Table 22.3 Register States Of Siof In Each Processing Mode
Section 22 Serial I/O with FIFO (SIOF) Table 22.3 Register States of SIOF in Each Processing Mode Power-on Reset by Manual PRESET Reset by Sleep by Pin/WDT/ WDT/Multiple SLEEP Module Name Abbreviation H-UDI Exceptions Instruction Standby Mode register SIMDR H'8000 H'8000 Retained Retained...
Page 852: Mode Register (Simdr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.1 Mode Register (SIMDR) SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode. Bit: TRMD[1:0] FL[3:0] — — — — REDG TXDIZ RCIM Initial value: R/W: Initial Bit Name Value Description 15, 14 TRMD[1:0]...
Page 853 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description TXDIZ SIOF_TXD Pin Output when Transmission is Invalid* 0: High output (1 output) when invalid 1: High-impedance state when invalid Note: Invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted.
Page 854: Table 22.4 Operation In Each Transfer Mode
Section 22 Serial I/O with FIFO (SIOF) Table 22.4 shows the operation in each transfer mode. Table 22.4 Operation in Each Transfer Mode Transfer Mode Master/Slave SIOF_SYNC Bit Delay Control Data Method* Slave mode 1 Slave Synchronous pulse SYNCDL bit Slot position Slave mode 2 Slave...
Page 855 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description 12 to 8 BRPS[4:0] 00000 Prescalar Setting Set the master clock division ratio according to the count value of the prescalar of the baud rate generator. The range of settings is from 00000 (× 1/1) to 11111 (×...
Page 856: Control Register (Sictr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.3 Control Register (SICTR) SICTR is a 16-bit readable/writable register that sets the SIOF operating state. Bit: SCKE FSE — — — — — — — — — — TXRST RXRST Initial value: R/W: Initial Bit Name...
Page 857 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description Transmit Enable 0: Disables data transmission from the SIOF_TXD pin 1: Enables data transmission from the SIOF_TXD pin • This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOF_SYNC signal).
Page 858 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description TXRST Transmit Reset 0: Does not reset transmit operation 1: Resets transmit operation • This bit setting becomes valid immediately. For details of transmit reset, refer to table 22.13. •...
Page 859: Transmit Data Register (Sitdr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.4 Transmit Data Register (SITDR) SITDR is a 32-bit write-only register that specifies the SIOF operating status. Bit: SITDL[15:0] Initial value: — — — — — — — — — — — — —...
Page 860: Receive Data Register (Sirdr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.5 Receive Data Register (SIRDR) SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the receive FIFO. Bit: SIRDL[15:0] Initial value: — — — — —...
Page 861: Transmit Control Data Register (Sitcr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.6 Transmit Control Data Register (SITCR) SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. SITCR can be specified only when the FL bits in SIMDR are specified as B'1xxx (x: don't care). SITCR is initialized by the conditions specified in table 22.3, Register State of SIOF in Each Processing Mode, or by a transmit reset caused by the TXRST bit in SICTR.
Page 862: Receive Control Data Register (Sircr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.7 Receive Control Data Register (SIRCR) SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR can be specified only when the FL bits in SIMDR are specified as B'1xxx (x: don't care). Bit: SIRC0[15:0] Initial value:...
Page 863: Status Register (Sistr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.8 Status Register (SISTR) SISTR is a 16-bit readable/writable register that shows the SIOF state. Each bit in this register becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1. Bit: —...
Page 864 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description TDREQ Transmit Data Transfer Request 0: Indicates that the size of empty space in the transmit FIFO does not exceed the size specified by the TFWM bit in SIFCTR. 1: Indicates that the size of empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR.
Page 865 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description RFFUL Receive FIFO Full 0: Receive FIFO not full 1: Receive FIFO full • This bit is valid when the RXE bit in SICTR is 1. • This bit indicates a state; if SIRDR is read, the SIOF clears this bit.
Page 866 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description SAERR Slot Assign Error 0: Indicates that no slot assign error occurs 1: Indicates that a slot assign error occurs A slot assign error occurs when the specifications in SITDAR, SIRDAR, and SICDAR overlap.
Page 867 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description TFOVF Transmit FIFO Overflow 0: No transmit FIFO overflow 1: Transmit FIFO overflow A transmit FIFO overflow means that there has been an attempt to write to SITDR when the transmit FIFO is full. When a transmit FIFO overflow occurs, the SIOF indicates overflow, and writing is invalid.
Page 868 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description RFUDF Receive FIFO Underflow 0: No receive FIFO underflow 1: Receive FIFO underflow A receive FIFO underflow means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive FIFO underflow occurs, the value of data read from SIRDR is not guaranteed.
Page 869: Interrupt Enable Register (Siier)
Section 22 Serial I/O with FIFO (SIOF) 22.3.9 Interrupt Enable Register (SIIER) SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each interrupt enable bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an interrupt.
Page 870 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description RCRDYE Receive Control Data Ready Enable 0: Disables interrupts due to receive control data ready 1: Enables interrupts due to receive control data ready RFFULE Receive FIFO Full Enable 0: Disables interrupts due to receive FIFO full 1: Enables interrupts due to receive FIFO full RDREQE...
Page 871: Fifo Control Register (Sifctr)
Section 22 Serial I/O with FIFO (SIOF) 22.3.10 FIFO Control Register (SIFCTR) SIFCTR is a 16-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer. Bit: TFWM[2:0] TFUA[4:0] RFWM[2:0] RFUA[4:0] Initial value: R/W: Initial Bit Name Value Description 15 to 13 TFWM[2:0] Transmit FIFO Watermark...
Page 872 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description 7 to 5 RFWM[2:0] 000 Receive FIFO Watermark 000: Issue a transfer request when 1 stage or more of the receive FIFO are valid. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 4 or more stages of the receive FIFO are valid.
Page 873: Transmit Data Assign Register (Sitdar)
Section 22 Serial I/O with FIFO (SIOF) 22.3.11 Transmit Data Assign Register (SITDAR) SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a frame. Bit: — — — TDLA[3:0] — — TDRA[3:0] TDLE TDRE TLREP Initial value: R/W:...
Page 874: Receive Data Assign Register (Sirdar)
Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description 5, 4 — All 0 Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 TDRA[3:0] 0000 Transmit Right-Channel Data Assigns 3 to 0 Specify the position of right-channel data in a transmit frame as 0000 (0) to 1110 (14).
Page 875: Control Data Assign Register (Sicdar)
Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description RDRE Receive Right-Channel Data Enable 0: Disables right-channel data reception 1: Enables right-channel data reception 6 to 4 — All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 876 Section 22 Serial I/O with FIFO (SIOF) Initial Bit Name Value Description 11 to 8 CD0A[3:0] 0000 Control Channel 0 Data Assigns 3 to 0 Specify the position of control channel 0 data in a receive or transmit frame as 0000 (0) to 1110 (14). 1111: Setting prohibited •...
Page 877: Figure 22.2 Serial Clock Supply
Section 22 Serial I/O with FIFO (SIOF) 22.4 Operation 22.4.1 Serial Clocks Master/Slave Modes: The following modes are available as the SIOF clock mode. • Slave mode: SIOF_SCK, SIOF_SYNC input • Master mode: SIOF_SCK, SIOF_SYNC output Baud Rate Generator: In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock.
Page 878: Table 22.5 Siof Serial Clock Frequency
Section 22 Serial I/O with FIFO (SIOF) Table 22.5 SIOF Serial Clock Frequency Sampling Rate Frame Length 8 kHz 44.1 kHz 48 kHz 32 bits 256 kHz 1.4112 MHz 1.536 MHz 64 bits 512 kHz 2.8224 MHz 3.072 MHz 128 bits 1.024 MHz 5.6448 MHz 6.144 MHz...
Page 879: Figure 22.3 Serial Data Synchronization Timing
Section 22 Serial I/O with FIFO (SIOF) 22.4.2 Serial Timing SIOF_SYNC: The SIOF_SYNC is a frame synchronous signal. Depending on the transfer mode, it has the following two functions. • Synchronous pulse: 1-bit-width pulse indicating the start of the frame •...
Page 880: Figure 22.4 Siof Transmit/Receive Timing
Section 22 Serial I/O with FIFO (SIOF) Transmit/Receive Timing: The SIOF_TXD transmit timing and SIOF_RXD receive timing relative to the SIOF_SCK can be set as the sampling timing in the following two ways. The transmit/receive timing is set using the REDG bit in SIMDR. •...
Page 881: Table 22.7 Frame Length
Section 22 Serial I/O with FIFO (SIOF) Frame Length: The length of the frame to be transferred by the SIOF is specified by the bits FL[3:0] in SIMDR. Table 22.7 shows the relationship between the bits FL[3:0] settings and frame length.
Page 882: Figure 22.5 Transmit/Receive Data Bit Alignment
Section 22 Serial I/O with FIFO (SIOF) 22.4.4 Register Allocation of Transfer Data Transmit/Receive Data: Writing and reading of transmit/receive data is performed for the following registers. • Transmit data writing: SITDR (32-bit access) • Receive data reading: SIRDR (32-bit access) Figure 22.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
Page 883: Figure 22.6 Control Data Bit Alignment
Section 22 Serial I/O with FIFO (SIOF) Table 22.8 Audio Mode Specification for Transmit Data Mode TDLE TDRE TLREP Monaural Stereo Left and right same audio output Note: x: Don't care Table 22.9 Audio Mode Specification for Receive Data Mode RDLE RDRE Monaural...
Page 884: Figure 22.7 Control Data Interface (Slot Position)
Section 22 Serial I/O with FIFO (SIOF) The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR. Table 22.10 shows the relationship between the number of channels in control data and bit settings. Table 22.10 Setting Number of Channels in Control Data Number of Channels CD0E...
Page 885: Figure 22.8 Control Data Interface (Secondary Fs)
Section 22 Serial I/O with FIFO (SIOF) Control by Secondary FS (Slave Mode 2): The CODEC normally outputs the SIOF_SYNC signal as synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to transmit or receive control data.
Page 886: Table 22.11 Conditions To Issue Transmit Request
Section 22 Serial I/O with FIFO (SIOF) 22.4.6 FIFO Overview: The transmit and receive FIFOs of the SIOF have the following features. • 16-stage 32-bit FIFOs for transmission and reception • The FIFO pointer can be updated in one read or write cycle regardless of access size of the CPU and DMAC.
Page 887 Section 22 Serial I/O with FIFO (SIOF) The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen FIFO stages.
Page 888: Figure 22.9 Example Of Transmit Operation In Master Mode
Section 22 Serial I/O with FIFO (SIOF) 22.4.7 Transmit and Receive Procedures Transmission in Master Mode: Figure 22.9 shows an example of settings and operation for master mode transmission. Flow Chart SIOF Settings SIOF Operation Start Set operating mode, serial clock, slot positions for transmit data, Set SIMDR, SISCR, SITDAR, slot position for control data,...
Page 889: Figure 22.10 Example Of Receive Operation In Master Mode
Section 22 Serial I/O with FIFO (SIOF) Reception in Master Mode: Figure 22.10 shows an example of settings and operation for master mode reception. Flow Chart SIOF Settings SIOF Operation Start Set operating mode, serial clock, slot positions for receive data, Set SIMDR, SISCR, slot position for control data, and SIRDAR, SICDAR, and SIFCTR...
Page 890: Figure 22.11 Example Of Transmit Operation In Slave Mode
Section 22 Serial I/O with FIFO (SIOF) Transmission in Slave Mode: Figure 22.11 shows an example of settings and operation for slave mode transmission. Flow Chart SIOF Operation SIOF Settings Start Set operating mode, serial clock, slot positions for transmit data, slot position for control data, Set SIMDR, SISCR, SITDAR, control data, and FIFO request...
Page 891: Figure 22.12 Example Of Receive Operation In Slave Mode
Section 22 Serial I/O with FIFO (SIOF) Reception in Slave Mode: Figure 22.12 shows an example of settings and operation for slave mode reception. Flow Chart SIOF Settings SIOF Operation Start Set operating mode, serial clock, Set SIMDR, SISCR, SIRDAR, slot positions for receive data, SICDAR, and SIFCTR slot position for control data, and...
Page 892: Table 22.13 Transmit And Receive Reset
Section 22 Serial I/O with FIFO (SIOF) Transmit/Receive Reset: The SIOF can separately reset the transmit and receive units by setting the following bits to 1. • Transmit reset: TXRST bit in SICTR • Receive reset: RXRST bit in SICTR Table 22.13 shows the details of initialization upon transmit or receive reset.
Page 893: Table 22.14 Siof Interrupt Sources
Section 22 Serial I/O with FIFO (SIOF) 22.4.8 Interrupts The SIOF has one type of interrupt. Interrupt Sources: Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR. Table 22.14 lists the SIOF interrupt sources. Table 22.14 SIOF Interrupt Sources No.
Page 894 Section 22 Serial I/O with FIFO (SIOF) Regarding Interrupt Source: The transmit sources and receive sources are signals indicating the SIOF state; after being set, if the state changes, they are automatically cleared by the SIOF. When the DMA transfer is used, a DMA transfer request of the FIFO is disabled for one cycle at the end of that DMA transfer.
Page 895: Figure 22.13 Transmit And Receive Timing (8-Bit Monaural Data (1))
Section 22 Serial I/O with FIFO (SIOF) 22.4.9 Transmit and Receive Timing Examples of the SIOF serial transmission and reception are shown in figure 22.13 to figure 22.19. 8-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, an frame length = 8 bits 1 frame SIOF_SCK...
Page 896: Figure 22.15 Transmit And Receive Timing (16-Bit Monaural Data)
Section 22 Serial I/O with FIFO (SIOF) 16-bit Monaural Data: Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 64 bits 1 frame SIOF_SCK SIOF_SYNC SIOF_TXD L-channel data SIOF_RXD Slot No.0 Slot No.1 Slot No.2 Slot No.3...
Page 897: Figure 22.17 Transmit And Receive Timing (16-Bit Stereo Data (2))
Section 22 Serial I/O with FIFO (SIOF) 16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left-channel transmit data, slot No.1 used for left-channel receive data, slot No.2 used for right-channel transmit data, slot No.3 used for right-channel receive data, and frame length = 64 bits 1 frame SIOF_SCK SIOF_SYNC...
Page 898: Figure 22.19 Transmit And Receive Timing (16-Bit Stereo Data (4))
Section 22 Serial I/O with FIFO (SIOF) 16-bit Stereo Data (4): Synchronous pulse method, falling edge sampling, slot No.0 used for left- channel data, slot No.2 used for right-channel data, slot No.1 used for control data for channel 0 , slot No.3 used for control data for channel 1, and frame length = 128 bits 1 frame SIOF_SCK...
Page 899: Section 23 Serial Protocol Interface (Hspi)
Section 23 Serial Protocol Interface (HSPI) Section 23 Serial Protocol Interface (HSPI) This LSI incorporates one channel of the Serial Protocol Interface (HSPI). 23.1 Features The HSPI has the following features. • Operating mode: Master mode or Slave mode. • The transmit and receive sections within the module are double buffered to allow duplex communication.
Page 900: Figure 23.1 Block Diagram Of Hspi
Section 23 Serial Protocol Interface (HSPI) Figure 23.1 is a block diagram of the HSPI. Bus interface Interrupt (SPII) Register System control SPCR HSPI_CS SPSR SPSCR SPTBR SPRBR HSPI_RX HSPI_TX Shift register Peripheral Clock division clock (Pck) Polarity selection SCK generator HSPI_CLK [Legend] SPCR:...
Page 901: Table 23.1 Pin Configuration
Section 23 Serial Protocol Interface (HSPI) 23.2 Input/Output Pins The input/output pins of the HSPI is shown in table 23.1. Table 23.1 Pin Configuration Pin Name Function Description HSPI_CLK Serial bit clock pin Input/Output Clock input/output HSPI_TX Transmit data pin Output Transmit data output HSPI_RX...
Page 902: Control Register (Spcr)
Section 23 Serial Protocol Interface (HSPI) 23.3.1 Control Register (SPCR) SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and specifies the clock polarity and frequency. Bit: — — — — — — — — —...
Page 903 Section 23 Serial Protocol Interface (HSPI) Initial Bit Name Value Description IDIV Initial Clock Division Ratio 0: The peripheral clock is divided by a factor of 4 initially to create an intermediate frequency, which is further divided to create the serial bit clock when master mode.
Page 904: Status Register (Spsr)
Section 23 Serial Protocol Interface (HSPI) 23.3.2 Status Register (SPSR) SPSR is a 32-bit readable/writable register. The status flag in SPSR can confirm whether the HSPI correctly operates or not. If the ROIE bit in SPSCR is set to 1, an interrupt request is generated due to the occurrence of the receive buffer overrun error or the warning of the receive buffer overrun error.
Page 905 Section 23 Serial Protocol Interface (HSPI) Initial Bit Name Value Description TXEM Transmit FIFO Empty Flag This status flag is enabled only to operation in FIFO mode. The flag is set to 1 when the transmit FIFO is empty of data to transmit. It is cleared to 0 when more data is written to the transmit FIFO.
Page 906 Section 23 Serial Protocol Interface (HSPI) Initial Bit Name Value Description RXOW R/W* Receive Buffer Overrun Warning Flag This status flag is set to 1 when a new serial data transfer starts and the previous received data has not been read from SPRBR. The RXOW remain set to 1 until writing a 0 to its bit position.
Page 907: System Control Register (Spscr)
Section 23 Serial Protocol Interface (HSPI) 23.3.3 System Control Register (SPSCR) SPSCR is a 32-bit readable/writable register that enables or disables interrupts or FIFO mode, selects either LSB first or MSB first in transmitting/receiving date, and master or slave mode. If any of the FFEN, LMSB, CSA or MASL bit values are changed, then the module will undergo the HSPI software reset.
Page 908 Section 23 Serial Protocol Interface (HSPI) Initial Bit Name Value Description FFEN FIFO Mode Enable Enables or disables the FIFO mode. When FIFO mode is enabled two 8-entry deep FIFOs are made available, one for transmit data and one for receive data. These FIFOs are read and written via SPTBR and SPRBR.
Page 909: Transmit Buffer Register (Sptbr)
Section 23 Serial Protocol Interface (HSPI) Initial Bit Name Value Description RXDE Receive DMA Enable 0: Receive DMA transfer request disabled 1: Receive DMA transfer request enabled TXDE Transmit DMA Enable 0: Transmit DMA transfer request disabled 1: Transmit DMA transfer request enabled MASL Master/Slave Select Bit 0: HSPI module configured as a slave...
Page 910: Receive Buffer Register (Sprbr)
Section 23 Serial Protocol Interface (HSPI) 23.3.5 Receive Buffer Register (SPRBR) SPRBR is a 32-bit read-only register that stores the number of received data. Bit: — — — — — — — — — — — — — — — —...
Page 911: Figure 23.2 Operational Flowchart
Section 23 Serial Protocol Interface (HSPI) 23.4 Operation 23.4.1 Operation Overview without DMA (FIFO Mode Disabled) Figure 23.2 shows the flow of a transmit/receive operation procedure. Start Reset the system Select master or slave operation by setting the MASL bit in SPSCR Select required interrupts by setting TFIE and ROIE bits in...
Page 912: Operation Overview With Dma
Section 23 Serial Protocol Interface (HSPI) During the transmit function the slave responds by sending data to the master synchronized with the HSPI_CLK from the master transmitted. Data from the slave is sampled and transferred to the shift register in the module and on completion of the transmit function, is transferred to SPRBR. The HSPI_CS pin is used to select the HSPI module when the HSPI is configured as a slave, and prepare it to receive data from an external master.
Page 913: Figure 23.3 Timing Conditions When Fbs = 0
Section 23 Serial Protocol Interface (HSPI) 6. Disable the module until it is required again. In some applications, an undefined amount of data will received from an external HSPI device. If this is the case, follow the following procedure: 1. Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity etc.) and enable FIFO mode.
Page 914: Figure 23.4 Timing Conditions When Fbs = 1
Section 23 Serial Protocol Interface (HSPI) sck_cycle HSPI_CLK (CLKP = 0) HSPI_CLK (CLKP = 1) HSPI_TX HSPI_RX HSPI_RX Figure 23.4 Timing Conditions when FBS = 1 23.4.5 HSPI Software Reset If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI software reset is generated.
Page 915: Section 24 Multimedia Card Interface (Mmcif)
Section 24 Multimedia Card Interface (MMCIF) Section 24 Multimedia Card Interface (MMCIF) This LSI supports a multimedia card interface (MMCIF). The MMC mode interface can be utilized. The MMCIF is a clock-synchronous serial interface that transmits/receives data that is distinguished in terms of command and response. A number of commands/responses are predefined in the multimedia card.
Page 916: Input/Output Pins
Section 24 Multimedia Card Interface (MMCIF) Figure 24.1 shows a block diagram of the MMCIF. MMCIF MCDAT Data transmission/ FIFO reception control Peripheral bus Command transmission/ MCCMD response reception control Interrupt control FSTAT TRAN MMC mode control FRDY Card clock MCCLK generator Figure 24.1 Block Diagram of MMCIF...
Page 917: Register Descriptions
Section 24 Multimedia Card Interface (MMCIF) 24.3 Register Descriptions Table 24.2 shows the MMCIF register configuration. Table 24.3 shows the register states in each processing mode. Table 24.2 Register Configuration Sync Register Name Abbrev. P4 Address Area 7 Address Size Clock Command register 0 CMDR0...
Page 918 Section 24 Multimedia Card Interface (MMCIF) Sync Register Name Abbrev. P4 Address Area 7 Address Size Clock Response register 5 RSPR5 H'FFE6 0025 H'1FE6 0025 Response register 6 RSPR6 H'FFE6 0026 H'1FE6 0026 Response register 7 RSPR7 H'FFE6 0027 H'1FE6 0027 Response register 8 RSPR8 H'FFE6 0028...
Page 919: Table 24.3 Register States Of Hspi In Each Processing Mode
Section 24 Multimedia Card Interface (MMCIF) Table 24.3 Register States of HSPI in Each Processing Mode Power-on Reset by Manual PRESET Reset by WDT/ Sleep by Module Pin/WDT/ Multiple SLEEP Register Name Abbrev. Standby H-UDI Exception Instruction Command register 0 CMDR0 H'00 H'00...
Page 920 Section 24 Multimedia Card Interface (MMCIF) Power-on Reset by Manual Reset PRESET by WDT/ Sleep by Module Pin/WDT/ Multiple SLEEP Register Name Abbrev. Standby H-UDI Exception Instruction Response register 6 RSPR6 H'00 H'00 Retained Retained Response register 7 RSPR7 H'00 H'00 Retained Retained...
Page 921: Command Registers 0 To 5 (Cmdr0 To Cmdr5)
Section 24 Multimedia Card Interface (MMCIF) 24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5) The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table 24.4, and the command is transmitted when the START bit in CMDSTRT is set to 1. Each command is transmitted in order form the MSB (bit 7) in CMDR0 to the LSB (bit 0) in CMDR5.
Page 922: Command Start Register (Cmdstrt)
Section 24 Multimedia Card Interface (MMCIF) 24.3.2 Command Start Register (CMDSTRT) CMDSTRT is an 8-bit readable/writable register that triggers the start of command transmission, representing the start of a command sequence. The following operations should have been completed before the command sequence starts. •...
Page 923: Operation Control Register (Opcr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.3 Operation Control Register (OPCR) OPCR is an 8-bit readable/writable register that aborts command operation, and suspends or continues data transfer. Bit:      DATAEN CONTI Initial value: R/W: Initial Bit Name Value Description CMDOFF...
Page 924 Section 24 Multimedia Card Interface (MMCIF) Initial Bit Name Value Description DATAEN Data Enable Starts a write data transmission by a command with write data. This bit is cleared automatically when 1 is written and the MMCIF received the DATAEN command.
Page 925: Card Status Register (Cstr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.4 Card Status Register (CSTR) CSTR indicates the MMCIF status during command sequence execution. Bit: FIFO_ FIFO_ DTBUSY — BUSY CWRE DTBUSY FULL EMPTY Initial value: — R/W: Initial Bit Name Value Description BUSY Command Busy Indicates command execution status.
Page 926 Section 24 Multimedia Card Interface (MMCIF) Initial Bit Name Value Description CWRE Command Register Write Enable Indicates whether the CMDR command is being transmitted or has been transmitted. 0: The CMDR command has been transmitted, or the START bit in CMDSTRT has not been set yet, so the new command can be written.
Page 927: Interrupt Control Registers 0 To 2 (Intcr0 To Intcr2)
Section 24 Multimedia Card Interface (MMCIF) 24.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2) The INTCR registers enable or disable interrupts. • INTCR0 Bit: BTIE FEIE FFIE DRPIE DTIE CRPIE CMDIE Initial value: R/W: Initial Bit Name Value Description FEIE FIFO Empty Interrupt Flag Setting Enable...
Page 928 Section 24 Multimedia Card Interface (MMCIF) Initial Bit Name Value Description CMDIE Command Transmit End Interrupt Flag Setting Enable 0: Disables command transmit end interrupt (disables CMDI flag setting). 1: Enables command transmit end interrupt (enables CMDI flag setting). DBSYIE Data Busy End Interrupt Flag Setting Enable 0: Disables data busy end interrupt (disables DBSYI flag setting).
Page 929 Section 24 Multimedia Card Interface (MMCIF) Initial Bit Name Value Description CRCERIE CRC Error Interrupt Flag Setting Enable 0: Disables CRC error interrupt (disables CRCERI flag setting). 1: Enables CRC error interrupt (enables CRCERI flag setting). DTERIE Data Timeout Error Interrupt Flag Setting Enable 0: Disables data timeout error interrupt (disables DTERI flag setting).
Page 930: Interrupt Status Registers 0 To 2 (Intstr0 To Intstr2)
Section 24 Multimedia Card Interface (MMCIF) 24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) The INTSTR registers enable or disable MMCIF interrupts FSTAT, TRAN, ERR and FRDY. • INTSTR0 Bit: DRPI CRPI CMDI DBSYI Initial value: R/W: Initial Interrupt Bit Name Value...
Page 931 Section 24 Multimedia Card Interface (MMCIF) Initial Interrupt Bit Name Value Description output DRPI Data Response Interrupt Flag TRAN 0: No interrupt [Clearing condition] Write 0 after reading DRPI = 1. (Writing 1 is invalid) 1: Interrupt requested [Setting condition] When the CRC status is received while DRPIE = 1.
Page 932 Section 24 Multimedia Card Interface (MMCIF) Initial Interrupt Bit Name Value Description output DBSYI Data Busy End Interrupt Flag TRAN 0: No interrupt [Clearing condition] Write 0 after reading DBSYI = 1. (Writing 1 is invalid) 1: Interrupt requested [Setting condition] When data busy state is canceled while DBSYIE = 1.
Page 933 Section 24 Multimedia Card Interface (MMCIF) • INTSTR1 Bit:      DTERI CTERI Initial value: R/W: Initial Interrupt Bit Name Value Description output 7 to 3 — All 0 Reserved — These bits are always read as 0. The write value should always be 0.
Page 934 Section 24 Multimedia Card Interface (MMCIF) • INTSTR2 Bit: FRDY — — — — — — FRDYI Initial value: — R/W: Initial Interrupt Bit Name Value Description output   7 to 2 All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 935: Transfer Clock Control Register (Clkon)
Section 24 Multimedia Card Interface (MMCIF) 24.3.7 Transfer Clock Control Register (CLKON) CLKON controls the transfer clock frequency and clock ON/OFF. At this time, use a sufficiently slow clock for transfer through open-drain type output in MMC mode. In a command sequence, do not perform clock ON/OFF or frequency modification. Bit: ...
Page 936: Command Timeout Control Register (Ctocr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.8 Command Timeout Control Register (CTOCR) CTOCR specifies the period to generate a timeout for the command response. The counter (CTOUTC), to which the peripheral bus does not have access, counts the transfer clock to monitor the command timeout. The initial value of CTOUTC is 0, and CTOUTC starts counting the transfer clock from the start of command transmission.
Page 937: Transfer Byte Number Count Register (Tbcr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.9 Transfer Byte Number Count Register (TBCR) TBCR is an 8-bit readable/writable register that specifies the number of bytes to be transferred (block size) for each single block transfer command. TBCR specifies the number of data block bytes not including the start bit, end bit, and CRC.
Page 938: Mode Register (Moder)
Section 24 Multimedia Card Interface (MMCIF) 24.3.10 Mode Register (MODER) MODER is an 8-bit readable/writable register that specifies the MMCIF operating mode. The following sequence should be repeated when the MMCIF uses the multimedia card: Send a command, wait for the end of the command sequence and the end of the data busy state, and send a next command.
Page 939: Command Type Register (Cmdtyr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.11 Command Type Register (CMDTYR) CMDTYR is an 8-bit readable/writable register that specifies the command format in conjunction with RSPTYR. Bits TY1 and TY0 specify the existence and direction of transfer data, and bits TY6 to TY2 specify the additional settings.
Page 940: Response Type Register (Rsptyr)
Section 24 Multimedia Card Interface (MMCIF) Initial Bit Name Value Description Type 3 Set this bit to 1 when specifying stream transfer. Bits TY1 and TY0 should be set to 01 or 10. The command sequence of the stream transfer specified by this bit ends when it is aborted by the CMD12 command.
Page 941 Section 24 Multimedia Card Interface (MMCIF) Initial Bit Name Value Description  7, 6 All 0 Reserved This bit is always read as 0. The write value should always be 0. RTY5 Response Type 5 Sets data busy status from the MMC card. 0: A command without data busy 1: A command with data busy RTY4...
Page 942: Table 24.5 Correspondence Between Commands And Settings Of Cmdtyr And Rsptyr
Section 24 Multimedia Card Interface (MMCIF) Table 24.5 summarizes the correspondence between the commands described in the MultiMediaCard System Specification Version 3.1 and the settings of the CMDTYR and RSPTYR registers. Table 24.5 Correspondence between Commands and Settings of CMDTYR and RSPTYR CMDTYR RSPTYR INDEX...
Page 943 Section 24 Multimedia Card Interface (MMCIF) CMDTYR RSPTYR INDEX Abbreviation resp TY6 TY5 TY4 TY3 TY2 TY[1:0] RTY5 RTY4 RTY[2:0] CMD32 TAG_SECTOR_START CMD33 TAG_SECTOR_END CMD34 UNTAG_SECTOR CMD35 TAG_ERASE_GROUP_ START CMD36 TAG_ERASE_GROUP_END CMD37 UNTAG_ERASE_GROUP CMD38 ERASE CMD39 FAST_IO CMD40 GO_IRQ_STATE CMD42 LOCK_UNLOCK CMD55 APP_CMD...
Page 944: Transfer Block Number Counter (Tbncr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.13 Transfer Block Number Counter (TBNCR) A value other than 0 must be written to the TBNCR register if a multiple block transfer is selected through the TY5 and TY6 bits in the CMDTYR. Set the transfer block number in the TBNCR. The value of TBNCR is decremented by one as each block transfer is executed and the command sequence ends when the TBNCR value equals 0.
Page 945: Response Registers 0 To 16, D (Rspr0 To Rspr16, Rsprd)
Section 24 Multimedia Card Interface (MMCIF) 24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD) RSPR0 to RSPR16 are command response registers, which are seventeen 8-bit registers. RSPRD is an 8-bit CRC status register. The number of command response bytes differs according to the command. The number of command response bytes can be specified by RSPTYR in the MMCIF.
Page 946 Section 24 Multimedia Card Interface (MMCIF) Clearing an RSPR is completed two transfer clock cycles after an arbitrary value is written to the RSPR. • RSPR0 to RSPR16 Bit: RSPR Initial value: R/W: Initial Bit Name Value Description 7 to 0 RSPR H'00 These bits are cleared to H'00 by writing an arbitrary...
Page 947: Data Timeout Register (Dtoutr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.15 Data Timeout Register (DTOUTR) DTOUTR specifies the period to generate a data timeout. The 16-bit counter (DTOUTC) and a prescaler, to which the peripheral bus does not have access, count the peripheral clock to monitor the data timeout.
Page 948: Data Register (Dr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.16 Data Register (DR) DR is a register for reading/writing FIFO data. Word/byte access is enabled to addresses of this register. Bit: Initial value: — — — — — — — — — — —...
Page 949: Fifo Pointer Clear Register (Fifoclr)
Section 24 Multimedia Card Interface (MMCIF) 1 word (2 bytes) H'01 H'23 H'45 H'67 64 words H'89 H'AB FIFO Figure 24.2 DR Access Example 24.3.17 FIFO Pointer Clear Register (FIFOCLR) The FIFO write/read pointer is cleared by writing an arbitrary value to FIFOCLR. Bit: FIFOCLR Initial value:...
Page 950: Dma Control Register (Dmacr)
Section 24 Multimedia Card Interface (MMCIF) 24.3.18 DMA Control Register (DMACR) DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal. The DMA request signal is output based on a value that has been set to SET2 to SET0. Bit: ...
Page 951: Operation
Section 24 Multimedia Card Interface (MMCIF) 24.4 Operation The multimedia card is an external storage media that can be easily connected or disconnected. The MMCIF operates in MMC mode. Insert a card and supply power to it. Then operate the MMCIF by applying the transfer clock after setting an appropriate transfer clock frequency.
Page 952 Section 24 Multimedia Card Interface (MMCIF) • All cards are initialized to the idle state by CMD0. • The operation condition registers (OCR) of all cards are read via wired-OR and cards that cannot operate are deactivated by CMD1. The cards that are not deactivated enter the ready state. •...
Page 953: Figure 24.3 Example Of Command Sequence For Commands Not Requiring Command Response
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK MCCMD Command output (48 bits) MCDAT CMDSTRT Command transmission Command transmission started ended (START) Cleared by INTSTR0 software (CMDI) CSTR (CWRE) Command transmission period (BUSY) Command sequence period (REQ) Figure 24.3 Example of Command Sequence for Commands Not Requiring Command Response Rev.1.00 Dec.
Page 954: Figure 24.4 Example Of Operational Flow For Commands Not Requiring Command Response
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Set command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 (CMDI) interrupt detected? End of command sequence Figure 24.4 Example of Operational Flow for Commands Not Requiring Command Response Operation of Commands without Data Transfer...
Page 955: Figure 24.5 Example Of Command Sequence For Commands Without Data Transfer (No Data Busy State)
Section 24 Multimedia Card Interface (MMCIF) • The command response is received from the card. If the card returns no command response, the command response is detected by the command timeout error (CTERI). • The end of the command sequence is detected by poling the BUSY flag in CSTR or by the command response receive end interrupt (CRPI).
Page 956: Figure 24.6 Example Of Command Sequence For Commands Without Data Transfer (With Data Busy State)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK Command response MCCMD Command output (48 bits) reception (Busy state) MCDAT CMDSTRT Command transmission Response reception started completed (START) INTSTR0 (CMDI) (CRPI) Busy state completed (DBSYI) CSTR Command transmission (CWRE) period (BUSY) Command sequence execution period (DTBUSY_TU)
Page 957: Figure 24.7 Example Of Operational Flow For Commands Without Data Transfer
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Set command data to CMDR0 to CMDR4 Set command type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 (CRCERI) interrupt detected? (CRPI) interrupt detected? response? DTBUSY...
Page 958 Section 24 Multimedia Card Interface (MMCIF) Commands with Read Data Flash memory operation commands include a number of commands involving read data. Such commands confirm the card status by the command argument and command response, and receive card information and flash memory data from the MCDAT pin. In multiple block transfer, two transfer methods can be used;...
Page 959: Figure 24.8 Example Of Command Sequence For Commands With Read Data (Block Size ≤ Fifo Size)
Section 24 Multimedia Card Interface (MMCIF) • The end of the command sequence is detected by poling the BUSY flag in CSTR, by the data transfer end interrupt (DTI) or pre-defined multiple block transfer end (BTI). • Write the CMDOFF bit to 1 if a CRC error (CRCERI) or a command timeout error (CTERI) occurs in the command response reception.
Page 960: Figure 24.9 Example Of Command Sequence For Commands With Read Data (Block Size > Fifo Size)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK Transfer clock Transfer clock CMD17 (READ_SINGLE_BLOCK) transmission halted transmission resumed Command Block data MCCMD Block data reception resumed reception suspended Command response MCDAT Read data Read data Command CMDSTRT transmission started (START) OPCR (RD_CONTI)
Page 961: Figure 24.10 Example Of Command Sequence For Commands With Read Data (Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK Transfer clock Transfer clock transmission resumed transmission halted CMD12 CMD18(READ_MULTIPLE_BLOCK) (STOP_TRANSMISSION) MCCMD Command Command Command Command response response Read data Read data Read data MCDAT Command CMDSTRT Block data transmission started reception ended (START) OPCR...
Page 962: Figure 24.11 Example Of Command Sequence For Commands With Read Data (Stream Transfer)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK Transfer clock Transfer clock Transfer clock transmission transmission resumed transmission resumed halted CMD12 CMD11 (READ_DAT_UNTIL_STOP) (STOP_TRANSMISSION) MCCMD Data reception Data reception Command Command suspended resumed Command Command response response Read data Read data MCDAT Command...
Page 963: Figure 24.12 Example Of Operational Flow For Commands With Read Data (Single Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to (TBCR) Execute CMD16 CMD16 normal end? Execute CMD17 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) inte rrupt detected? Read response register (CTERI) interrupt detected? Response status...
Page 964: Figure 24.13 Example Of Operational Flow For Commands With Read Data (1) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to (TBCR) Execute CMD16 CMD16 normal end? Execute CMD18 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? Read response register (CTERI) interrupt detected? Response status...
Page 965: Figure 24.13 Example Of Operational Flow For Commands With Read Data (2) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) (DTERI) interrupt detected? Cap ≥ Len (1 + n (DTI)) - Cap × n (FFI) (CRCERI) interrupt detected? (DTERI) interrupt detected? (DTI) interrupt detected? Next block read? (FFI) interrupt detected? Read data from FIFO Set the RD_CONTI to 1 Read data from FIFO Set the CMDOFF to 1...
Page 966: Figure 24.13 Example Of Operational Flow For Commands With Read Data (3) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to (TBCR) Execute CMD16 CMD16 normal end? Set the number of transfer block (TBNCR) Execute CMD23 CMD23 normal end? Execute CMD18 (CMDR to CMDSTRT) (CRCERI) interrupt detected?
Page 967: Figure 24.13 Example Of Operational Flow For Commands With Read Data (4) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) (DTERI) interrupt detected? Cap ≥ Len (1 + n (DTI)) - Cap × n (FFI) (CRCERI) interrupt detected? (DTERI) interrupt detected? (DTI) interrupt detected? (FFI) interrupt detected? TBNCR value = n (DTI) ? (BTI) interrupt detected? Read data from FIFO Read data from FIFO...
Page 968: Figure 24.14 Example Of Operational Flow For Commands With Read Data (Stream Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Execute CMD11 (CMDR to CMDSTRT) (CRCERI) inte rrupt detected? (CRPI) inte rrupt detected? Read response register (CTERI) interrupt detected? Response status normal ended? (DTERI) inte rrupt detected? (FFI) interrupt detected? Data read completed?
Page 969 Section 24 Multimedia Card Interface (MMCIF) Commands with Write Data Flash memory operation commands include a number of commands involving write data. Such commands confirm the card status by the command argument and command response, and transmit card information and flash memory data via the MCDAT pin. For a command that is related to time-consuming processing such as flash memory write, the card indicates the data busy state via the MCDAT pin.
Page 970 Section 24 Multimedia Card Interface (MMCIF) • The end of the command sequence is detected by poling the BUSY flag in CSTR, data transfer end interrupt (DTI), data response interrupt (DRPI), or pre-defined multiple block transfer end (BTI). • The data busy state is checked through DTBUSY in CSTR. If the card is in data busy state, the end of the data busy state is detected by the data busy end interrupt (DBSYI).
Page 971: Figure 24.15 Example Of Command Sequence For Commands With Write Data (Block Size ≤ Fifo Size)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK CMD24 (WRITE_SINGLE_BLOCK) MCCMD Command Command response Status MCDAT Busy Write data Command CMDSTRT transmission started (START) OPCR (DATAEN) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (DRPI) (DBSYI) (FEI) CSTR (CWRE) (BUSY) Single block write command execution sequence (FIFO_EMPTY) (DTBUSY) (DTBUSY_TU)
Page 972: Figure 24.16 Example Of Command Sequence For Commands With Write Data (Block Size > Fifo Size)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK Transfer clock Transfer clock transmission transmission resumed CMD24(WRITE_SINGLE_BLOCK) halted MCCMD Command Command response Write data Write data MCDAT Busy Command CMDSTRT Block data Block data transmission transmission transmission started suspended resumed (START) Writing data to FIFO OPCR...
Page 973: Figure 24.17 Example Of Command Sequence For Commands With Write Data (Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK CMD25 WRITE_MULTIPE_BLOCK CMD12(STOP_TRANSMISSION) MCCMD Command Command Command Write data Write data Write data Command response response Status Status MCDAT Command CMDSTRT transmission started (START) Next block data Block data Block data transmission transmission reception...
Page 974: Figure 24.18 Example Of Command Sequence For Commands With Write Data (Stream Transfer)
Section 24 Multimedia Card Interface (MMCIF) Input/output pins MCCLK Transfer Transfer Transfer Transfer clock clock clock clock trans- trans- transmission transmission mission mission resumed resumed halted halted CMD20 (WRITE_DAT_UNTIL_STOP) CMD12(STOP_TRANSMISSION) MCCMD Data Data Data Command Command transmission transmission transmission Command Command response response...
Page 975: Figure 24.19 Example Of Operational Flow For Commands With Write Data (Single Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Execute CMD24 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? Read response register (CTERI) interrupt detected? Response status...
Page 976: Figure 24.20 Example Of Operational Flow For Commands With Write Data (1) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Execute CMD25 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt Read response register detected? Response status normal ended?
Page 977: Figure 24.20 Example Of Operational Flow For Commands With Write Data (2) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Writing data to FIFO Set the DATAEN to 1 (FEI) interrupt detected? Cap × n (FEI) - Len (1 + n (DTI)) ≥ Len (DTI) interrupt detected? (CRCERI) interrupt detected? (DTERI) interrupt detected? (DRPI) interrupt detected? (DTBUSY) detected? (DBSYI) interrupt...
Page 978: Figure 24.20 Example Of Operational Flow For Commands With Write Data (3) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Set the number of block to TBNCR Execute CMD 23 CMD 23 normal end? Execute CMD25 (CMDR to CMDSTRT) (CRCERI) interrupt...
Page 979: Figure 24.20 Example Of Operational Flow For Commands With Write Data (4) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Writing data to FIFO Set the DATAEN to 1 (FEI) interrupt detected? Cap × n (FEI) - Len (1 + n (DRPI)) ≥ Len (DTI) interrupt detected? (CRCERI) interrupt detected? (DTERI) interrupt detected? (DRPI) interrupt detected? (DTBUSY) detected? (DBSYI) interrupt...
Page 980: Figure 24.21 Example Of Operational Flow For Commands With Write Data (Stream Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Execute CMD20 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt Read response register detected? Response status normal ended? Writing data to FIFO Set the DATAEN to 1 (FEI) interrupt detected? All data write to...
Page 981: Mmcif Interrupt Sources
Section 24 Multimedia Card Interface (MMCIF) 24.5 MMCIF Interrupt Sources Table 24.7 lists the MMCIF interrupt sources. The interrupt sources are classified into four groups, and four interrupt vectors are assigned. Each interrupt source can be individually enabled by the enable bits in INTCR0 to INTCR2.
Page 982: Operations When Using Dma
Section 24 Multimedia Card Interface (MMCIF) 24.6 Operations when Using DMA 24.6.1 Operation in Read Sequence In order to transfer data in FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC*. Transmit the read command after setting DMACR. Figure 24.22 to 24.24 shows the operational flow for a read sequence.
Page 983 Section 24 Multimedia Card Interface (MMCIF) • An error in a command sequence (during data reception) is detected through the CRC error flag or data timeout flag. When these flags are detected, set the CMDOFF bit in OPCR to 1, issue CMD12 and suspend the command sequence.
Page 984: Figure 24.22 Example Of Read Sequence Flow (Single Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Set DMAC-related condition Set DMACR Execute CMD17 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt Read response register...
Page 985: Figure 24.23 Example Of Read Sequence Flow (1) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Set DMAC-related condition Set DMACR Execute CMD 18 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt...
Page 986: Figure 24.23 Example Of Read Sequence Flow (2) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) (CRCERI) interrupt detected? (DTERI) interrupt detected? (DTI) interrupt detected? Next block read? Set RD_CONTI to 1 Set the DMACR to H'84 DMA transfer end? Set the CMDOFF to 1 Set the CMDOFF to 1 Set the CMDOFF to 1 Execute CMD12 Execute CMD12...
Page 987: Figure 24.23 Example Of Read Sequence Flow (3) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Set the number of block to TBNCR Execute CMD 23 CMD 23 normal end? Set DMAC-related condition Set DMACR Execute CMD 18...
Page 988: Figure 24.23 Example Of Read Sequence Flow (4) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) (CRCERI) interrupt detected? (DTERI) interrupt detected? (DTI) interrupt detected? TBNCR = n (DTI)? Set RD_CONTI to 1 (BTI) interrupt detected? Set the DMACR to H'84 DMA transfer end? Set the CMDOFF to 1 Set the CMDOFF to 1 Set the CMDOFF to 1 Execute CMD12 Clear the DMACR to H'00...
Page 989: Figure 24.24 Example Of Operational Flow For Stream Read Transfer
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set DMAC-related condition Set DMACR Execute CMD11 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt Read response register detected? Response status normal ended? (DTERI) interrupt detected? DMA transfer end? Set the CMDOFF to 1...
Page 990: Figure 24.25 Example Of Operational Flow For Auto-Mode Pre-Defined Multiple Block Read Transfer (1)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Set the number of transfer block to TBNCR Execute CMD 23 CMD 23 normal end? Set DMAC-related condition Set DMACR Execute CMD 18...
Page 991: Figure 24.25 Example Of Operational Flow For Auto-Mode Pre-Defined Multiple Block Read Transfer (2)
Section 24 Multimedia Card Interface (MMCIF) (CRCERI) interrupt detected? (DTERI) interrupt detected? (BTI) interrupt detected? Set the DMACR to H'84 DMA transfer end? Set the CMDOFF to 1 Set the CMDOFF to 1 Set the CMDOFF to 1 Execute CMD12 Clear the DMACR to H'00 Clear the DMACR to H'00 Clear the DMACR to H'00...
Page 992: Operation In Write Sequence
Section 24 Multimedia Card Interface (MMCIF) 24.6.2 Operation in Write Sequence To transfer data to FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC. Then, start transfer to the card after a FIFO ready interrupt. Figure 24.26 to 24.28 shows the operational flow for a write sequence.
Page 993 Section 24 Multimedia Card Interface (MMCIF) • An error in a command sequence (during data transmission) is detected through the CRC error flag (CRCERI) or data timeout error flag (DTERI). When these flags are detected, set the CMDOFF bit in OPCR to 1, issue CMD12 (Stop Tran in SPI mode), and suspend the command sequence.
Page 994: Figure 24.26 Example Of Write Sequence Flow (1) (Single Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Execute CMD 24 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt Read response register detected? Response status...
Page 995: Figure 24.26 Example Of Write Sequence Flow (2) (Single Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) (FRDYI) interrupt detected or DMA transfer end? Set the DATAEN bit to 1 DMA transfer end? Clear the DMACR to H'00 (DTI) interrupt detected? (CRCERI) interrupt detected? (DTERI) interrupt detected? (DRPI) interrupt detected? Set the CMDOFF to 1 (DTBUSY) detected? (DBSYI) interrupt detected?
Page 996: Figure 24.27 Example Of Write Sequence Flow (1) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Execute CMD 25 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt Read response register detected? Response status...
Page 997: Figure 24.27 Example Of Write Sequence Flow (2) (Open-Ended Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) (FRDYI) interrupt detected or DMA transfer end? Set the DATAEN to 1 DMA transfer end? Clear the DMACR to H'00 (DTI) interrupt detected? (CRCERI) interrupt detected? (DTERI) interrupt detected? (DRPI) interrupt detected? (DTBUSY) detected? (DBSYI) interrupt detected? Next block write?
Page 998: Figure 24.27 Example Of Write Sequence Flow (3) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Set the number of transfer block size to TBCR Execute CMD16 CMD16 normal end? Set the number of block to TBNCR Execute CMD 23 CMD 23 normal end? Execute CMD 25 (CMDR to CMDSTRT) (CRCERI) interrupt...
Page 999: Figure 24.27 Example Of Write Sequence Flow (4) (Pre-Defined Multiple Block Transfer)
Section 24 Multimedia Card Interface (MMCIF) (FRDYI) interrupt detected or DMA transfer end? Set the DATAEN to 1 DMA transfer end? Clear the DMACR to H'00 (DTI) interrupt detected? (CRCERI) interrupt detected? (DTERI) interrupt detected? (DRPI) interrupt detected? (DTBUSY) detected? (DBSYI) interrupt detected? TBNCR = n (DRPI)?
Page 1000: Figure 24.28 Example Of Operational Flow For Stream Write Transfer
Section 24 Multimedia Card Interface (MMCIF) Start of command sequence Clear FIFO Execute CMD 20 (CMDR to CMDSTRT) (CRCERI) interrupt detected? (CRPI) interrupt detected? (CTERI) interrupt Read response register detected? Response status normal ended? Set DMAC-related condition Set DMACR (FRDYI) interrupt detected or DMA transfer end? Set the DATAEN to 1...

Renesas SH7780 Series Hardware Manual

Section 1 Overview

Section 2 Programming Model

Section 3 Instruction Set

Section 4 Pipelining

Section 5 Exception Handling

Section 6 Floating-Point Unit (FPU)

Section 7 Memory Management Unit (MMU)

Section 8 Caches

Section 9 L Memory

Section 10 Interrupt Controller (INTC)

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Summary of Contents for Renesas SH7780 Series