Renesas SH-4A User Manual page 67

Table 1.4 Measurement Items (cont)
Classification Type
CPU Stalled
performance cycle
(cont)
TLB TLB
performance
Instruction bus Instruction
performance
Measurement Item
Cycles stalled in full-
trace mode (with
multi-counts)
Cycles stalled in full-
trace mode (without
multi-counts)
Number of UTLB miss
for instruction fetch
Number of UTLB miss
for operand fetch
Number of ITLB miss
Number of memory
accesses for
instruction fetch
Number of instruction
cache access
Option Note
SFM All items are counted
independently.
SF This item is not counted if the
stall cycle is generated
simultaneously with a stall
cycle that has occurred due
to instruction execution.
UMI The number of TLB-miss
exceptions generated by an
instruction fetch (number of
EXPEVT sets).
UMO The number of TLB-miss
exceptions generated by an
operand access (number of
EXPEVT sets).
IM The number of ITLB misses
for valid accesses (does not
include UTLB hits or misses).
MIF The number of memory
accesses by an instruction
fetch.
Accesses canceled by an
instruction-fetch bus are not
counted.
Instruction fetches, which
have been fetched in
anticipation of a branch but
not actually executed, are
counted.
Accesses by the PREFI
instruction are included.
IC The number of accesses for
an instruction cache during
memory access of the
opcode.
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