Page 1 REJ09B0256-0100 SH7763 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC Engine Family SH-4A Series R5S77630 Rev.1.00 Revision Date: Oct. 01, 2007...
Page 2 Rev. 1.00 Oct. 01, 2007 Page ii of lxvi...
Page 3 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 4 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 6 Preface This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems.
Page 7 Abbreviations Arithmetic Logic Unit ASID Address Space Identifier Ball Grid Array Timer/Counter (Compare Match Timer) Clock Pulse Generator Central Processing Unit Double Data Rate DDRIF DDR-SDRAM Interface Direct Memory Access DMAC Direct Memory Access Controller FIFO First-In First-Out Floating-point Unit Audio Codec H-UDI User Debugging Interface...
Page 8 Most Significant Bit Program Counter Peripheral Component Interconnect PCIC PCI (local bus) Controller Pin Function Controller RISC Reduced Instruction Set Computer Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO Serial Sound Interface Test Access Port Translation Lookaside Buffer Timer Unit UART...
Page 9: Table Of Contents
Contents Section 1 Overview......................... 1 Features of the SH7763......................1 Block Diagram ........................13 Pin Arrangement ........................14 Section 2 Programming Model ................37 Data Formats........................37 Register Descriptions ......................38 2.2.1 Privileged Mode and Banks ..................38 2.2.2 General Registers....................42 2.2.3...
Page 10 5.3.1 Exception Handling Flow ..................109 5.3.2 Exception Handling Vector Addresses ..............109 Exception Types and Priorities ..................110 Exception Flow ........................112 5.5.1 Exception Flow..................... 112 5.5.2 Exception Source Acceptance................114 5.5.3 Exception Requests and BL Bit ................115 5.5.4 Return from Exception Handling................
Page 11 6.5.4 Data TLB Multiple Hit Exception ................ 169 6.5.5 Data TLB Miss Exception ..................169 6.5.6 Data TLB Protection Violation Exception............170 6.5.7 Initial Page Write Exception................. 171 Memory-Mapped TLB Configuration................172 6.6.1 ITLB Address Array ..................... 173 6.6.2 ITLB Data Array....................174 6.6.3 UTLB Address Array....................
Page 12 7.6.1 IC Address Array....................206 7.6.2 IC Data Array ....................... 208 7.6.3 OC Address Array ....................209 7.6.4 OC Data Array...................... 210 Store Queues ........................212 7.7.1 SQ Configuration....................212 7.7.2 Writing to SQ......................212 7.7.3 Transfer to External Memory ................213 7.7.4 Determination of SQ Access Exception..............
Page 13 9.3.4 Interrupt Source Register (INTREQ)..............250 9.3.5 Interrupt Mask Register 0 (INTMSK0) ..............251 9.3.6 Interrupt mask register 1 (INTMSK1) ..............253 9.3.7 Interrupt mask register 2 (INTMSK2) ..............254 9.3.8 Interrupt Mask Clear Register 0 (INTMSKCLR0) ..........257 9.3.9 Interrupt mask clear register 1 (INTMSKCLR1)..........
Page 14 Section 10 SuperHyway Bus Bridge (SBR)............313 10.1 Features..........................313 10.2 Register Descriptions......................314 10.2.1 Bus Arbitration Priority Level Setting Register (SBRIVCLV) ......315 10.2.2 SuperHyway Bus Priority Control Resister (PRPRICR) ........316 10.3 Operation ........................... 317 10.3.1 SuperHyway Bus Interface ................... 317 10.3.2 Bus Arbitration .....................
Page 15 12.3 Data Conversion......................... 412 12.3.1 Data Alignment..................... 412 12.3.2 Data Alignment in Peripheral Modules ..............414 12.4 Register Descriptions ......................415 12.4.1 Memory Interface Mode Register (MIM) ............. 417 12.4.2 DDR-SDRAM Control Register (SCR)..............421 12.4.3 DDR-SDRAM Timing Register (STR)..............423 12.4.4 DDR-SDRAM Row Attribute Register (SDR) .............
Page 16 13.4.6 Normal mode ......................549 13.4.7 Power Management ....................549 13.4.8 PCI Local Bus Basic Interface................550 13.5 Usage Notes ........................562 13.5.1 Notes on PCIC Target Reading................562 13.5.2 Notes on Host Mode ..................... 562 Section 14 Direct Memory Access Controller (DMAC)........565 14.1 Features..........................
Page 17 Section 15 External CPU Interface (EXCPU) ...........621 15.1 Features..........................621 15.2 Input/Output Pins ....................... 622 15.3 Register Descriptions ......................623 15.3.1 External CPU Control Register (EXCCTRL) ............624 15.3.2 External CPU Memory Space Select Register (EXCMSETR) ......625 15.3.3 External CPU Interrupt Output Control Register (EXCINOR)......626 15.4 Operation ...........................
Page 18 Section 18 Power-Down Mode ................. 667 18.1 Features..........................667 18.1.1 Types of Power-Down Modes ................667 18.2 Input/Output Pins....................... 669 18.3 Register Descriptions......................670 18.3.1 Standby Control Register (STBCR)..............671 18.3.2 Module Stop Register 0 (MSTPCR0) ..............672 18.3.3 Module Stop Register 1 (MSTPCR1) ..............673 18.4 Sleep Mode ........................
Page 19 19.4.2 Input Capture Function ..................703 19.5 Interrupts..........................704 19.6 Usage Notes ........................705 19.6.1 Register Writes ..................... 705 19.6.2 Reading from TCNT..................... 705 19.6.3 External Clock Frequency..................705 Section 20 16-Bit Timer Pulse Unit (TPU) ............707 20.1 Features..........................707 20.2 Input/Output Pins .......................
Page 20 Section 22 Realtime Clock (RTC)..............759 22.1 Features..........................759 22.1.1 Block Diagram...................... 760 22.2 Input/Output Pins....................... 761 22.3 Register Descriptions......................762 22.4 Register Descriptions......................764 22.4.1 64 Hz Counter (R64CNT)..................764 22.4.2 Second Counter (RSECCNT) ................764 22.4.3 Minute Counter (RMINCNT)................765 22.4.4 Hour Counter (RHRCNT) ..................
Page 21 23.3.4 E-MAC Interrupt Permission Register (ECSIPR)..........816 23.3.5 PHY Interface Register (PIR) ................817 23.3.6 MAC Address High Register (MAHR) ..............818 23.3.7 MAC Address Low Register (MALR)..............819 23.3.8 Receive Frame Length Register (RFLR) .............. 820 23.3.9 PHY Status Register (PSR)................... 821 23.3.10 PHY_INT Polarity Register (PIPR)..............
Page 22 23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0)......867 23.3.45 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1)......868 23.3.46 VLANtag Set Register (Port 0) (TSU_VTAG0)........... 869 23.3.47 VLANtag Set Register (Port 1) (TSU_VTAG1)........... 870 23.3.48 CAM Entry Table Busy Register (TSU_ADSBSY) ..........
Page 23 23.3.72 Transmit Descriptor List Start Address Register (TDLAR) ......... 908 23.3.73 Receive Descriptor List Start Address Register (RDLAR)........909 23.3.74 E-MAC/E-DMAC Status Register (EESR) ............910 23.3.75 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR) ..... 916 23.3.76 Transmit/Receive Status Copy Enable Register (TRSCER)......... 920 23.3.77 Receive Missed-Frame Counter Register (RMFCR) ..........
Page 24 Section 24 IP Security Accelerator (SECURITY) ........... 995 Section 25 Stream Interface (STIF)..............997 25.1 Features..........................997 25.2 Input/Output Pins....................... 999 25.3 Register Descriptions....................... 1000 25.3.1 Mode Registers 0, 1 (STIMDR0, STIMDR1)............. 1002 25.3.2 Control Registers 0, 1 (STICR0, STICR1) ............1006 25.3.3 Interrupt Status Registers 0, 1 (STIISR0, STIISR1) ...........
Page 25 26.4.7 10-Bit Address Format..................1048 26.4.8 Master Transmit Operation ................. 1050 26.4.9 Master Receive Operation................... 1052 26.5 Programming Examples....................1054 26.5.1 Master Transmitter....................1054 26.5.2 Master Receiver ....................1055 26.5.3 Master Transmitter—Restart—Master Receiver ..........1056 Section 27 Serial Communication Interface with FIFO (SCIF) ......1059 27.1 Features..........................
Page 26 28.3.3 Transmit Shift Register (SCTSR) ............... 1127 28.3.4 Transmit FIFO Data Register (SCFTDR)............1127 28.3.5 Serial Mode Register (SCSMR)................1128 28.3.6 Serial Control Register (SCSCR)................ 1131 28.3.7 Serial Status Register (SCFSR) ................1135 28.3.8 Bit Rate Register (SCBRR) ................1141 28.3.9 FIFO Control Register (SCFCR) ................
Page 27 29.3.11 Transmit Data Assign Register (SITDAR) ............1213 29.3.12 Receive Data Assign Register (SIRDAR)............1214 29.3.13 Control Data Assign Register (SICDAR) ............1215 29.4 Operation ......................... 1217 29.4.1 Serial Clocks ....................... 1217 29.4.2 Serial Timing ...................... 1218 29.4.3 Transfer Data Format..................1220 29.4.4 Register Allocation of Transfer Data ..............
Page 28 Section 31 Multimedia Card Interface (MMCIF) ........... 1285 31.1 Features..........................1285 31.2 Input/Output Pins......................1287 31.3 Register Descriptions....................... 1288 31.3.1 Command Type Register (CMDTYR)..............1292 31.3.2 Response Type Register (RSPTYR)..............1293 31.3.3 Transfer Byte Number Count Register (TBCR) ..........1297 31.3.4 Transfer Block Number Counter (TBNCR)............
Page 29 32.3 Register Descriptions ....................... 1365 32.3.1 Area 6 Interface Status Register (PCC0ISR) ............1366 32.3.2 Area 6 General Control Register (PCC0GCR) ........... 1369 32.3.3 Area 6 Card Status Change Register (PCC0CSCR)..........1372 32.3.4 Area 6 Card Status Change Interrupt Enable Register (PCC0CSCIER)..... 1376 32.4 Operation .........................
Page 30 34.3.2 Status Register (SSISR) ..................1431 34.3.3 Transmit Data Register (SSITDR)..............1436 34.3.4 Receive Data Register (SSIRDR) ............... 1436 34.4 Operation ......................... 1437 34.4.1 Bus Format ......................1437 34.4.2 Non-Compressed Modes..................1438 34.4.3 Operation Modes ....................1448 34.4.4 Transmit Operation..................... 1449 34.4.5 Receive Operation ....................
Page 31 35.3.21 HcRhStatus Register (USBHRS) ................ 1484 35.3.22 HcRhPortStatus[2] Register (USBHRPS2)............1486 35.3.23 ConfigurationControl Register (USBHSC)............1489 35.4 Functional Description..................... 1491 35.4.1 General Functionality ..................1491 35.5 Connection Example of an External Circuit ..............1493 35.6 Usage Notes ........................1493 35.6.1 External memory that USBH accesses..............1493 35.6.2 Issuing USB Bus Reset ..................
Page 32 36.3.27 Trigger Register (TRG) ..................1536 36.3.28 Data Status Register (DASTS)................1537 36.3.29 FIFO Clear Register 0 (FCLR0) ................. 1538 36.3.30 FIFO Clear Register 1 (FCLR1) ................. 1539 36.3.31 DMA Transfer Setting Register (DMA) ............. 1540 36.3.32 Endpoint Stall Register 0 (EPSTL0)..............1541 36.3.33 Endpoint Stall Register 1 (EPSTL1)..............
Page 33 Section 37 LCD Controller (LCDC)..............1585 37.1 Features..........................1585 37.2 Input/Output Pins ......................1587 37.3 Register Configuration..................... 1588 37.3.1 LCDC Input Clock Register (LDICKR) ............. 1591 37.3.2 LCDC Module Type Register (LDMTR) ............1593 37.3.3 LCDC Data Format Register (LDDFR).............. 1596 37.3.4 LCDC Scan Mode Register (LDSMR) ...............
Page 34 37.6.2 Notes on Using NMI Interrupt................1653 Section 38 A/D Converter ................1655 38.1 Features..........................1655 38.2 Input Pins ......................... 1657 38.3 Register Descriptions....................... 1658 38.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ..........1658 38.3.2 A/D Control/Status Registers (ADCSR)............. 1660 38.4 Operation .........................
Page 35 40.2.8 Port H Control Register (PHCR) ................ 1705 40.2.9 Port I Control Register (PICR) ................1707 40.2.10 Port J Control Register (PJCR) ................1709 40.2.11 Port K Control Register (PKCR) ................ 1711 40.2.12 Port L Control Register (PLCR) ................. 1713 40.2.13 Port M Control Register (PMCR) ...............
Page 36 Section 41 User Break Controller (UBC)............1759 41.1 Features..........................1759 41.2 Register Descriptions....................... 1761 41.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ......1763 41.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ......1770 41.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)......
Page 37 Section 43 Electrical Characteristics ...............1825 43.1 Absolute Maximum Ratings .................... 1825 43.2 Power-On and Power-Off Order ..................1826 43.2.1 Power-On Order....................1826 43.2.2 Power-Off Order ....................1826 43.2.3 Power-Off and Power-On Order in RTC Power-Supply Backup Mode (Hardware Standby).................... 1828 43.2.4 Power-Off and Power-On Order in DDR-SDRAM Power-Supply Backup Mode......................
Page 38 Appendix ....................... 1903 CPU Operation Mode Register (CPUOPM) ..............1903 Instruction Prefetching and Its Side Effects..............1905 Speculative Execution for Subroutine Return..............1906 List of Mode Control Pins and Schematic Diagram of External Cicuits ......1907 Notes on Board Design ....................1909 Package Dimensions ......................
Page 39 Figures Section 1 Overview Figure 1.1 SH7763 Block Diagram ....................13 Figure 1.2 Pin Arrangement......................15 Section 2 Programming Model Figure 2.1 Data Formats ....................... 37 Figure 2.2 CPU Register Configuration in Each Processing Mode ..........41 Figure 2.3 General Registers ......................42 Figure 2.4 Floating-Point Registers ....................
Page 40 Figure 6.9 Flowchart of Memory Access Using UTLB.............. 160 Figure 6.10 Flowchart of Memory Access Using ITLB ............. 161 Figure 6.11 Operation of LDTLB Instruction................164 Figure 6.12 Memory-Mapped ITLB Address Array..............173 Figure 6.13 Memory-Mapped ITLB Data Array ................ 174 Figure 6.14 Memory-Mapped UTLB Address Array ..............
Page 41 Figure 11.8 SRAM Interface Wait Timing (Software Wait Only) ..........369 Figure 11.9 SRAM Interface Wait Cycle Timing (Wait Cycle Insertion by RDY Signal)..370 Figure 11.10 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting)..372 Figure 11.11 Burst ROM Basic Access Timing ................. 374 Figure 11.12 Burst ROM Wait Access Timing................
Page 42 Section 12 DDR-SDRAM Interface (DDRIF) Figure 12.1 DDRIF Block Diagram ................... 410 Figure 12.2 Data Alignment in DDR-SDRAM and DDRIF............414 Figure 12.3 Relationship between Write Values in SDMR and Output Signals to Memory Pins ......................428 Figure 12.4 DDR-SDRAM Access..................... 430 Figure 12.5 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes;...
Page 43 Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation (Local Address Space 0/1) ..................539 Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) ..540 Figure 13.12 Endian Conversion from PCI Local Bus to SuperHyway bus (Non-Byte Swapping: TBS = 0)................
Page 44 Figure 14.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection... 610 Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..... 611 Figure 14.16 Example of DREQ Input Detection in Burst Mode Level Detection ....611 Figure 14.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection) ......
Page 45 Section 19 Timer Unit (TMU) Figure 19.1 Block Diagram of TMU ..................688 Figure 19.2 Example of Count Operation Setting Procedure ............. 700 Figure 19.3 TCNT Auto-Reload Operation ................701 Figure 19.4 Count Timing when Operating on Internal Clock ........... 701 Figure 19.5 Count Timing when Operating on External Clock ..........
Page 46 Section 23 Gigabit Ethernet Controller (GETHER) Figure 23.1 Configuration of GETHER ..................784 Figure 23.2 GETHER Data Path and Various Settings .............. 938 Figure 23.3 Relationship between Transmit Descriptor and Transmit Buffer......940 Figure 23.4 Relationship between Receive Descriptor and Receive Buffer ....... 946 Figure 23.5 Relationship between Transmit Descriptor and Transmit Buffer......
Page 47 Figure 23.38 Data Subject to Checksum Calculation ..............993 Section 25 Stream Interface (STIF) Figure 25.1 Block Diagram of STIF ................... 998 Figure 25.2 Transmit/Receive Data Structure in External Memory (with 16-Byte Work Area) ..................1015 Figure 25.3 Clock Valid Reception Timing................1017 Figure 25.4 Strobe Reception Timing..................
Page 48 Figure 27.14 Sample Operation Using Modem Control (SCIF0_RTS) (Only in Channel 0) .................... 1104 Figure 27.15 Data Format in Clocked Synchronous Communication ........1104 Figure 27.16 Sample SCIF Initialization Flowchart ..............1106 Figure 27.17 Sample Serial Transmission Flowchart ............... 1107 Figure 27.18 Sample SCIF Transmission Operation in Clocked Synchronous Mode....
Page 49 Section 29 Serial I/O with FIFO (SIOF) Figure 29.1 Block Diagram of SIOF ..................1186 Figure 29.2 Serial Clock Supply....................1217 Figure 29.3 Serial Data Synchronization Timing ..............1219 Figure 29.4 SIOF Transmit/Receive Timing ................1220 Figure 29.5 Transmit/Receive Data Bit Alignment ..............1223 Figure 29.6 Control Data Bit Alignment ..................
Page 50 Figure 31.3 Example of Operational Flow for Commands Not Requiring Command Response....................1329 Figure 31.4 Example of Command Sequence for Commands without Data Transfer (No Data Busy State) .................... 1330 Figure 31.5 Example of Command Sequence for Commands without Data Transfer (with Data Busy State) ..................
Page 51 Figure 32.1 PC Card Controller Block Diagram............... 1360 Figure 32.2 Continuous 32-Mbyte Area Mode................. 1362 Figure 32.3 Continuous 16-Mbyte Area Mode (Area 6)............1363 Figure 32.4 SH7763 Interface....................1380 Figure 32.5 PCMCIA Memory Card Interface Basic Timing........... 1384 Figure 32.6 PCMCIA Memory Card Interface Wait Timing............ 1385 Figure 32.7 PCMCIA I/O Card Interface Basic Timing ............
Page 52 Figure 34.10 Inverted Clock ..................... 1445 Figure 34.11 Inverted Word Select................... 1445 Figure 34.12 Inverted Padding Polarity..................1445 Figure 34.13 Padding Bits First, Followed by Serial Data, with Delay........1446 Figure 34.14 Padding Bits First, Followed by Serial Data, without Delay....... 1446 Figure 34.15 Serial Data First, Followed by Padding Bits, without Delay.......
Page 53 Section 37 LCD Controller (LCDC) Figure 37.1 LCDC Block Diagram................... 1586 Figure 37.2 Valid Display and the Retrace Period..............1624 Figure 37.3 Color-Palette Data Format..................1628 Figure 37.4 Power-Supply Control Sequence and States of the LCD Module ......1634 Figure 37.5 Power-Supply Control Sequence and States of the LCD Module ......1634 Figure 37.6 Power-Supply Control Sequence and States of the LCD Module ......
Page 54 Section 39 D/A Converter (DAC) Figure 39.1 Block Diagram of D/A Converter ................. 1673 Figure 39.2 D/A Converter Operation Example ............... 1677 Section 41 User Break Controller (UBC) Figure 41.1 Block Diagram of UBC..................1760 Figure 41.2 Flowchart of User Break Debugging Support Function ........1790 Section 42 User Debugging Interface (H-UDI) Figure 42.1 H-UDI Block Diagram ..................
Page 55 Figure 43.23 MPX Basic Bus Cycle: Write................1853 Figure 43.24 MPX Bus Cycle: Burst Read................1854 Figure 43.25 MPX Bus Cycle: Burst Write ................1855 Figure 43.26 Byte Control SRAM Bus Cycle ................1856 Figure 43.27 Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, No Address Setup/Hold Time Insertion, RDS = 1, RDH = 0) ..........
Page 56 Figure 43.61 SIOF Transmission/Reception Timing (Master Mode 1, Sampling at the Falling Edge) ..........1885 Figure 43.62 SIOF Transmission/Reception Timing (Master Mode 1, Sampling at the Rising Edge) ..........1885 Figure 43.63 SIOF Transmission/Reception Timing (Master Mode 2, Sampling at the Falling Edge) ..........1886 Figure 43.64 SIOF Transmission/Reception Timing (Master Mode 2, Sampling at the Rising Edge) ..........
Page 57 Tables Section 1 Overview Table 1.1 Features of the SH7763................... 80 Table 1.2 Pin Configuration....................94 Section 2 Programming Model Table 2.1 Initial Register Values..................... 40 Table 2.2 Bit Allocation for FPU Exception Handling............50 Section 3 Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions ...........
Page 58 Section 7 Caches Table 7.1 Cache Features...................... 187 Table 7.2 Store Queue Features .................... 187 Table 7.3 Register Configuration..................190 Table 7.4 Register States in Each Processing State .............. 190 Section 8 L Memory Table 8.1 L Memory Addresses.................... 217 Table 8.2 Register Configuration..................
Page 59 Table 11.15 Relationship between Address and CE When Using PCMCIA Interface ..380 Section 12 DDR-SDRAM Interface (DDRIF) Table 12.1 Pin Configuration....................81 Table 12.2 Access and Data Alignment in Little Endian Mode (External Bus Width is 32 Bits) ................82 Table 12.3 Access and Data Alignment in Big Endian Mode (External Bus Width is 32 Bits) ................
Page 60 Table 15.4 Access and Data Alignment for Little Endian ............618 Table 15.5 Access and Data Alignment for Big Endian ............619 Section 16 Clock Pulse Generator (CPG) Table 16.1 Pin Configuration and Functions of CPG ............... 82 Table 16.2 Clock Operating Modes ..................
Page 61 Table 20.13 Up/Down-Count Conditions in Phase Counting Mode 4........731 Section 21 Compare Match Timer (CMT) Table 21.1 Register Configuration..................735 Table 21.2 Register State in Each Operating Mode ..............736 Section 22 Realtime Clock (RTC) Table 22.1 RTC Pins....................... 747 Table 22.2 Register Configuration..................
Page 62 Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA) Table 28.1 Pin Configuration....................1109 Table 28.2 Register Configuration..................1110 Table 28.3 Register States in each Operation Mode ............. 1111 Table 28.4 SCSMR Settings ....................1127 Table 28.5 Baud Rate (3.6864 MHz Clock) ................. 1134 Table 28.6 SCSMR Settings for Serial Transfer Format Selection........
Page 63 Table 31.6 Correspondence between Command Response Byte Number and RSPR... 1286 Table 31.7 List of Chattering Elimination Pulse Cycles............1311 Table 31.8 MMCIF Interrupt Sources................... 1343 Section 32 PC Card Controller (PCC) Table 32.1 Features of the PCMCIA Interface ..............1347 Table 32.2 PCC Pin Configuration ..................
Page 64 Table 37.3 Register State in Each Operating Mode..............83 Table 37.4 I/O Clock Frequency and Clock Division Ratio ............. 86 Table 37.5 Limits on the Resolution of Rotated Displays, Burst Length, and Connected Memory (32-bit SDRAM) ..................119 Table 37.6 Available Power-Supply Control-Sequence Periods at Typical Frame Rates..
Page 65 Table 43.3 DC Characteristics (1) [common] ................83 Table 43.4 DC Characteristics (2-a) [Except of USB Transceiver and I C Related Pins] ..84 Table 43.5 DC Characteristics (2-b) [I C Related Pins] ............85 Table 43.6 DC Characteristics (2-c) [USB Transceiver Related Pins] ........86 Table 43.7 Permissible Output Currents ...................
Page 66 Table G.1 Pin States ........................ 89 Table H.1 Handling of Unused Pins ..................107 Table I.1 Register Configuration..................119 Table J.1 Heat Resistance Simulation Results..............121 Rev. 1.00 Oct. 01, 2007 Page lxvi of lxvi...
Page 67: Section 1 Overview
Section 1 Overview Features of the SH7763 This LSI is a single-chip multifunction CMOS microcomputer that integrates the Renesas Technology original RISC (reduced instruction set computer) CPU core with the peripheral functions required for a wide range of application systems such as high-speed Ethernet, display, and digital AV systems.
Page 68: Section 1 Overview
Section 1 Overview Table 1.1 Features of the SH7763 Item Features • Maximum operating 266 MHz frequency • Performance 478 MIPS (266 MHz), 1862 MFLOPS (266 MHz) • Renesas Technology original architecture • 32-bit internal data bus • General-register files: ...
Page 69 Section 1 Overview Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt generation for IEEE754 compliance •...
Page 70 Section 1 Overview Item Features • Memory 4 Gbytes of physical address space, 256 address spaces (identified by management an 8-bit ASID (address space identifier)) unit (MMU) • Supports single virtual memory mode and multiple virtual memory mode • Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, or 1 Mbytes •...
Page 71 Section 1 Overview Item Features • Clock pulse Selectable CPU clock: 8 times EXTAL generator (CPG) • Clock modes:  CPU frequency: 266 MHz (max.)  Local bus frequency: 1/4 times the CPU clock 66 MHz (max.)  DDR-SDRAM I/F frequency: 1/2 times the CPU clock 133 MHz (max.) ...
Page 72 Section 1 Overview Item Features • Local bus state Physical address space divided into seven areas (areas 0 to 6), each controller (LBSC) comprising up to 64 Mbytes  I/F configuration, bus width, and wait cycle insertion are settable for each area •...
Page 73 Section 1 Overview Item Features • DDR-SDRAM DDR-SDRAM interface: 32-bit data bus width controller (DDRIF) • Supports the DDR266 or DDR200 SDRAM • DDR-SDRAM refreshing  Programmable refreshing intervals (auto-refresh mode)  Self-refresh mode • Supports a burst length of 2 •...
Page 74 Section 1 Overview Item Features • Timer unit (TMU) 6-channel auto-reload 32-bit timer • Input-capture function (channels 2 and 5 only) • Choice of seven types of counter input clock for each channel  External clock (TCLK), five peripheral clocks (Pck0/4, Pck0/16, Pck0/64, Pck0/256, Pck0/1024), and RTC clock •...
Page 75 Section 1 Overview Item Features • Serial sound Four channels (SSI0, SSI1, SSI2, SSI3) interface (SSI) • Supports various serial audio formats • Supports master/slave functions • Programmable word clock and bit clock generation • Multi-channel format • Supports 8/16/18/20/22/24/32-bit data formats •...
Page 76 Section 1 Overview Item Features • 8 bits ± 4LSB, two channels D/A converter • Conversion time: 10 µs (DAC) • Two data registers • Output range: 0 to Avcc (max. 3.6 V) • Display size: 16 × 1 pixels to 1024 × 1024 pixels LCD controller (LCDC) •...
Page 77 Section 1 Overview Item Features • Stream interface Parallel connection available when MPEG2 TS stream is input (STIF)  Parallel stream connection  Stream input: Master mode with clock-valid operation Byte transfer mode with strobe operation  Stream output: Master mode with clock-valid operation Byte transfer mode with strobe operation •...
Page 78 Section 1 Overview Item Features • Security Encryption/decryption based on AES (Advanced Encryption Standard) accelerator* (Key length: 128, 192, and 256 bits) (SECURITY) • DES/Triple-DES encryption/decryption based on DES (Data Encryption Standard) • Hash function generation based on the MD5 (Message-Digest Algorithm) •...
Page 79: Block Diagram
SECURITY*: Security accelerator TPU: 16-bit pulse unit USBH: USB host controller LCDC: LCD controller Note: * SECURITY is incorporated only in the R5S77630, not in the R5S77631. Figure 1.1 SH7763 Block Diagram Rev. 1.00 Oct. 01, 2007 Page 13 of 1956 REJ09B0256-0100...
Page 80: Pin Arrangement
Section 1 Overview Pin Arrangement Figure 1.2 shows the pin arrangement and table 1.2 lists the pin configuration of this LSI. Rev. 1.00 Oct. 01, 2007 Page 14 of 1956 REJ09B0256-0100...
Page 81: Figure 1.2 Pin Arrangement
Section 1 Overview Figure 1.2 Pin Arrangement Rev. 1.00 Oct. 01, 2007 Page 15 of 1956 REJ09B0256-0100...
Page 82: Table 1.2 Pin Configuration
Section 1 Overview Table 1.2 Pin Configuration Power Pin No. Pin Name Function Supply   VSSQ-DDR DDR-SDRAM I/O GND   VCCQ-DDR DDR-SDRAM I/O VCC M_VREF DDR-SDRAM VREF VCCQ_ M_CLK0 DDR-SDRAM clock VCCQ_ M_CLK1 DDR-SDRAM clock VCCQ_ M_WE DDR-SDRAM write enable VCCQ_ M_RAS DDR-SDRAM RAS...
Page 83 Section 1 Overview Power Pin No. Pin Name Function Supply PTJ1/ST0M_CLKIO/ IO/IO/I/I Port/ST data clock VCCQ RMII1_RX_ER/LCD_CLK RMII receive error/LCD clock source CS5/CE1A Chip select/Card select VCCQ PTM6/D30/EX_AD30/ST0_D6/ IO/IO/IO/IO/I/O/I Port/data bus/address-and-data VCCQ ET0_RX-CLK/RMII0_TXD1/ bus/ST data/ETHER receive clock/ PINT6 RMII transmit data/port interrupt input PTM4/D28/EX_AD28/ST0_D4/ IO/IO/IO/IO/I/I/I Port/data bus/address-and-data...
Page 84 Section 1 Overview Power Pin No. Pin Name Function Supply PTI3/ST0M_VALIDI/IIC0_SDA/ I/I/IO/I/I Port/ST data valid (mirror pin)/IIC VCCQ SIOF1_MCLK/USB_CLK serial data/ SIOF master clock/USB clock input PTK7/ST1_D7/GET0_ERXD7/ IO/IO/I/I/O Port/ST data /ETHER receive VCCQ SIOF2_MCLK/LCD_VCPWC data/SIOF master clock/LCD power supply control PTI5/MD10/ST1_VALID/ IO/I /IO/O Port/mode control (external CPU...
Page 85 Section 1 Overview Power Pin No. Pin Name Function Supply M_A12 DDR-SDRAM address bus VCCQ_ M_A11 DDR-SDRAM address bus VCCQ_ M_A9 DDR-SDRAM address bus VCCQ_ M_A8 DDR-SDRAM address bus VCCQ_ M_A7 DDR-SDRAM address bus VCCQ_ M_A6 DDR-SDRAM address bus VCCQ_ M_A5 DDR-SDRAM address bus VCCQ_...
Page 86 Section 1 Overview Power Pin No. Pin Name Function Supply   VSSQ I/O GND BS/EX_BS Bus cycle start VCCQ PTM2/D26/EX_AD26/ST0_D2/ IO/IO/IO/IO/O/I/I Port/data bus/address-and-data VCCQ ET0_WOL/RMII0_CRS_DV/ bus/ST data/ETHER wake on PINT2 run/RMII carrier detection/port interrupt input PTM1/D25/EX_AD25/ST0_D1/ IO/IO/IO/IO/I/I/I Port/data bus/address-and-data VCCQ ET0_TX-CLK/RMII0_RX_ER/ bus/ST data/ETHER transmit...
Page 87 Section 1 Overview Power Pin No. Pin Name Function Supply Chip select VCCQ   Internal VDD   VSSQ I/O GND   VCCQ I/O VCC RDWR/EX_RDWR Read/write VCCQ PTM0/D24/EX_AD24/ST0_D0/ IO/IO/IO/IO/O/I/I Port/data bus/address-and-data VCCQ ET0_TX-ER/PINT0/ bus/ST data/ETHER transmit RMII0M0_MDIO error/port interrupt input/RMII management data IO PTL7/D23/EX_AD23/...
Page 88 Section 1 Overview Power Pin No. Pin Name Function Supply   VSSQ I/O GND   Internal GND   VCCQ I/O VCC PTK3/ST1_D3/GET0_ETXD7/ IO/IO/O/IO/O Port/ST data/ETHER transmit VCCQ SIOF2_SYNC/LCD_D5 data/SIOF frame sync/LCD data PTK2/ST1_D2/GET0_ETXD6/ IO/IO/O/IO/O Port/ST data/ETHER transmit VCCQ SIOF1_SCK/LCD_D4 data/SIOF serial clock/LCD data...
Page 89 Section 1 Overview Power Pin No. Pin Name Function Supply M_D21 DDR-SDRAM data bus VCCQ_ M_D22 DDR-SDRAM data bus VCCQ_   VCCQ-DDR DDR-SDRAM I/O VCC   VCCQ-DDR DDR-SDRAM I/O VCC   Internal VDD PTL3/D19/EX_AD19/IRQ7/ IO/IO/IO/I/I/IO/I/ Port/data bus/address-and-data VCCQ IRL7/ET0_MDIO/INTC/ bus/external interrupt input/ETHER...
Page 90 Section 1 Overview Power Pin No. Pin Name Function Supply M_D7 DDR-SDRAM data bus VCCQ_ M_D6 DDR-SDRAM data bus VCCQ_ M_DQM2 DDR-SDRAM data mask VCCQ_   VSSQ-DDR DDR-SDRAM I/O GND   VSSQ-DDR DDR-SDRAM I/O GND   Internal GND D7/EX_AD7 IO/IO Data bus/address-and-data bus...
Page 91 Section 1 Overview Power Pin No. Pin Name Function Supply M_DQS1 DDR-SDRAM data strobe VCCQ_ M_DQM1 DDR-SDRAM data mask VCCQ_ M_DQM3 DDR-SDRAM data mask VCCQ_   VSS-DLL1 DLL1 GND   VSS-DLL2 DLL2 GND   Internal GND  ...
Page 92 Section 1 Overview Power Pin No. Pin Name Function Supply   Internal GND   Internal GND   Internal GND D1/EX_AD1 IO/IO Data bus/address-and-data bus VCCQ D0/EX_AD0 IO/IO Data bus/address-and-data bus VCCQ WE1/WE Data enable/PCMCIA WE VCCQ CLKOUT System clock output VCCQ M_D9...
Page 93 Section 1 Overview Power Pin No. Pin Name Function Supply   VSSQ-DDR DDR-SDRAM I/O GND   VSSQ-DDR DDR-SDRAM I/O GND   Internal GND   Internal GND   Internal GND   Internal GND   Internal GND ...
Page 94 Section 1 Overview Power Pin No. Pin Name Function Supply Address bus VCCQ Address bus VCCQ M_D13 DDR-SDRAM data bus VCCQ_ M_D12 DDR-SDRAM data bus VCCQ_   VSSQ-DDR DDR-SDRAM I/O GND   VCCQ-DDR DDR-SDRAM I/O VCC   VCCQ-DDR DDR-SDRAM I/O VCC ...
Page 95 Section 1 Overview Power Pin No. Pin Name Function Supply Address bus VCCQ   Internal VDD   Internal VDD   Internal VDD   Internal VDD   Internal VDD   Internal GND Address bus VCCQ Address bus VCCQ Address bus...
Page 96 Section 1 Overview Power Pin No. Pin Name Function Supply PTE0/INTA/PCC_DRV/ IO/IO/O/O/I Port/PCI interrupt/PCMCIA buffer VCCQ GET1_ETXD6/DREQ2 control/GMII transmit data/DMA transfer request PTD7/PCIRESET/ O/O/O/O/O Port/PCI reset/PCMCIA reset/GMII VCCQ PCC_RESET/GET1_ETXD7/ transmit data/LCD power supply LCDM_VEPWC control (mirror pin)   Internal GND ...
Page 97 Section 1 Overview Power Pin No. Pin Name Function Supply   AA15 VCCQ I/O VCC   AA16 VSSQ I/O GND   AA17 VSSQ I/O GND   AA18 VCCQ I/O VCC   AA19 VSSQ I/O GND ...
Page 98 Section 1 Overview Power Pin No. Pin Name Function Supply AB11 PTB2/AD11/PINT10/LCDM_D7 IO/IO/I/O Port/PCI address-and-data bus/port VCCQ interrupt input/LCD data (mirror pin) AB12 PTB6/CBE0/PINT14/ IO/IO/I/O Port/PCI command and byte VCCQ LCDM_D3 enable/port interrupt input/LCD data (mirror pin) AB13 PTC1/AD4/LCDM_D1 IO/IO/O Port/PCI address-and-data bus/LCD VCCQ data (mirror pin)
Page 99 Section 1 Overview Power Pin No. Pin Name Function Supply PTE3/AD20/SCIF2_SCK/ IO/IO/IO/I/IO Port/PCI address-and-data bus/IrDA VCCQ GET1_ERXD5/SSI0_WS serial clock /GMII receive data/SSI word select PTE2/AD16/PCC_IOIS16/ IO/IO/I/I/O Port/PCI address-and-data VCCQ GET1_ERXD7/TEND2 bus/PCMCIA 16-bit IO/GMII receive data/DMA transmit end PTD2/TRDY/PCC_RDY/ IO/IO/I/I/O/O Port/PCI target ready/PCMCIA VCCQ SIOF0_RXD/HAC_SYNC/ ready/SIOF receive data/HAC frame...
Page 100 Section 1 Overview Power Pin No. Pin Name Function Supply AC24 Analog input AVcc AC25 Analog input AVcc PTF3/CBE3/ET1_TX-CLK IO/IO/I Port/PCI command and byte VCCQ enable/transmit clock   VSSQ I/O GND   VCCQ I/O VCC PTH2/AD24/TPU_TI2A/ IO/IO/I/I/O Port/PCI address-and-data bus/TPU VCCQ ET1_ERXD0/RMII1M_TXD1 clock input/ETHER receive data/RMII...
Page 101 Section 1 Overview Power Pin No. Pin Name Function Supply AD17 PTO0/AUDSYNC/ IO/O/O/IO Port/AUD sync signal/RMII VCCQ RMII1_MDC/SSI2_WS management data clock/SSI word select AD18 PTO4/AUDATA3/EX_INT/ IO/O/O/IO Port/AUD data/external CPU VCCQ SSI3_WS interrupt/SSI word select ASEBRK/BRKACK AD19 Break mode acknowledge VCCQ ...
Page 102 Section 1 Overview Power Pin No. Pin Name Function Supply AE11 PTC3/AD8/MMC_ODMOD/ IO/IO/O/O Port/PCI address-and-data bus/MMC VCCQ LCDM_D4 open-drain control/LCD data (mirror pin) AE12 PTC6/AD5/LCDM_CL1 IO/IO/O Port/PCI address-and-data bus/LCD VCCQ shift clock (mirror pin) AE13 PTA6/AD1/MMC_VDDON IO/IO/O Port/PCI address-and-data bus/MMC VCCQ card power supply control AE14...
Page 103: Section 2 Programming Model
Section 2 Programming Model Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. Data Formats The data formats supported in this LSI are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits)
Page 104: Register Descriptions
Section 2 Programming Model Register Descriptions 2.2.1 Privileged Mode and Banks Processing Modes This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted.
Page 105 Section 2 Programming Model Control Registers Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processing modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode.
Page 106: Table 2.1 Initial Register Values
Section 2 Programming Model Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0_BANK0 to R7_BANK0, Undefined R0_BANK1 to R7_BANK1, R8 to R15 Control registers MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = B'1111, reserved bits = 0, others = undefined GBR, SSR, SPC, SGR, DBR Undefined...
Page 107: Figure 2.2 Cpu Register Configuration In Each Processing Mode
Section 2 Programming Model R0 _ BANK0* R0 _ BANK0* R0 _ BANK1* R1 _ BANK0* R1 _ BANK1* R1 _ BANK0* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK0* R3 _ BANK1* R4 _ BANK0* R4 _ BANK1* R4 _ BANK0*...
Page 108: General Registers
Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode.
Page 109: Floating-Point Registers
Section 2 Programming Model Note on Programming: As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0).
Page 110: Figure 2.4 Floating-Point Registers
Section 2 Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR=0 FPSCR.FR=1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XD10 XF10...
Page 111: Control Registers
Section 2 Programming Model 2.2.4 Control Registers Status Register (SR) BIt: Initial value: R/W: BIt: IMASK Initial value: R/W: Initial Bit Name Value Description — Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. Processing Mode Selects the processing mode.
Page 112 Section 2 Programming Model Initial Bit Name Value Description 27 to 16 — All 0 Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs.
Page 113: System Registers
Section 2 Programming Model Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of SR are saved to SSR in the event of an exception or interrupt. Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined) The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 114 Section 2 Programming Model Floating-Point Status/Control Register (FPSCR) BIt: Cause Initial value: R/W: BIt: Cause Enable (EN) Flag Initial value: R/W: Initial Bit Name Value Description 31 to 22 — All 0 Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
Page 115 Section 2 Programming Model Initial Bit Name Value Description 17 to 12 Cause All 0 FPU Exception Cause Field FPU Exception Enable Field 11 to 7 Enable (EN) All 0 FPU Exception Flag Field 6 to 2 Flag All 0 Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0.
Page 116: Figure 2.5 Relationship Between Sz Bit And Endian
Section 2 Programming Model <Big endian> Floating-point register DR (2i) FR (2i) FR (2i+1) 32 31 Memory area 8n+3 8n+4 8n+7 <Little endian> Floating-point register DR (2i) DR (2i) DR (2i) *1, *2 FR (2i) FR (2i+1) FR (2i) FR (2i+1) FR (2i) FR (2i+1) 32 31...
Page 117: Memory-Mapped Registers
Section 2 Programming Model Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. •...
Page 118: Data Formats In Registers
Section 2 Programming Model Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Figure 2.6 Formats of Byte Data and Word Data in Register Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.
Page 119: Processing States
Section 2 Programming Model A + 1 A + 2 A + 3 A + 11 A + 10 A + 9 A + 8 Address A Address A + 8 Byte 0 Byte 1 Byte 2 Byte 3 Byte 3 Byte 2 Byte 1 Byte 0 0 15 Address A + 4...
Page 120: Figure 2.8 Processing State Transitions
Section 2 Programming Model From any state when reset/manual reset input Reset state Reset/manual reset clearance Reset/manual Reset/manual reset input reset input Sleep instruction execution Instruction execution state Power-down state Interrupt occurence Figure 2.8 Processing State Transitions Rev. 1.00 Oct. 01, 2007 Page 54 of 1956 REJ09B0256-0100...
Page 121: Usage Note
Section 2 Programming Model Usage Note 2.7.1 Notes on Self-Modified Codes* This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the processing speed. Therefore if the instruction in the memory is modified and it is executed immediately, then the pre-modified code that is prefetched are likely to be executed. In order to execute the modified code definitely, one of the following sequences should be executed between the execution of modifying codes and modified codes.
Page 122 Section 2 Programming Model Rev. 1.00 Oct. 01, 2007 Page 56 of 1956 REJ09B0256-0100...
Page 123: Section 3 Instruction Set
Section 3 Instruction Set Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size.
Page 124 Section 3 Instruction Set T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below.
Page 125: Addressing Modes
Section 3 Instruction Set Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 126 Section 3 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @–Rn Effective address is register Rn contents, Byte: Rn – 1 → Rn indirect decremented by a constant beforehand: with pre- 1 for a byte operand, 2 for a word operand, Word: decrement 4 for a longword operand, 8 for a quadword...
Page 127 Section 3 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula GBR indirect @(disp:8, Effective address is register GBR contents with Byte: GBR + disp → EA with GBR) 8-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 Word: GBR + (word), or 4 (longword), according to the operand...
Page 128 Section 3 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC + 4 + disp × PC-relative disp:8 Effective address is PC + 4 with 8-bit 2 → Branch- displacement disp added after being sign-extended and multiplied by 2. Target PC + 4 + disp ×...
Page 129 Section 3 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or — XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or — CMP/EQ instruction is sign-extended.
Page 130: Instruction Set
Section 3 Instruction Set Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source operand...
Page 131 Section 3 Instruction Set Item Format Description Privileged mode "Privileged" means the instruction can only be executed in privileged mode. T bit Value of T bit after —: No change instruction execution  "New" means the instruction which is newly added in this LSI.
Page 132 Section 3 Instruction Set Table 3.4 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit New imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — — (disp × 2 + PC + 4) → sign 1001nnnndddddddd — — —...
Page 133 Rm:Rn middle 32 bits → Rn XTRCT Rm,Rn — — — 0010nnnnmmmm1101 The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the Note: displacement (disp). Rev. 1.00 Oct. 01, 2007 Page 67 of 1956 REJ09B0256-0100...
Page 134: Table 3.5 Arithmetic Operation Instructions
Section 3 Instruction Set Table 3.5 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn — — — 0011nnnnmmmm1100 #imm,Rn Rn + imm → Rn — — — 0111nnnniiiiiiii Rn + Rm + T → Rn, ADDC Rm,Rn —...
Page 135 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit DMULU.L Rm,Rn Unsigned, — — — 0011nnnnmmmm0101 Rn × Rm → MAC, 32 × 32 → 64 bits Rn – 1 → Rn; — — Comparison 0100nnnn00010000 when Rn = 0, result 1 →...
Page 136 Section 3 Instruction Set Table 3.6 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — — AND.B (R0 + GBR) & imm 11001101iiiiiiii —...
Page 137: Table 3.7 Shift Instructions
Section 3 Instruction Set Table 3.7 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — — LSB → Rn → T ROTR 0100nnnn00000101 — — T ← Rn ← T ROTCL 0100nnnn00100100 — —...
Page 138: Table 3.8 Branch Instructions
Section 3 Instruction Set Table 3.8 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — — 4 → PC When T = 1, nop BF/S label Delayed branch;...
Page 139 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit Rm → SGR Rm,SGR 0100mmmm00111010 Privileged — — Rm → SSR Rm,SSR 0100mmmm00111110 Privileged — — Rm → SPC Rm,SPC 0100mmmm01001110 Privileged — — Rm → DBR Rm,DBR 0100mmmm11111010 Privileged — —...
Page 140 Section 3 Instruction Set Instruction Operation Instruction Code Privileged T Bit 1 → T SETT 0000000000011000 — — SLEEP Sleep or standby 0000000000011011 Privileged — — SR → Rn SR,Rn 0000nnnn00000010 Privileged — — GBR → Rn GBR,Rn 0000nnnn00010010 — —...
Page 141: Table 3.10 Floating-Point Single-Precision Instructions
Section 3 Instruction Set Table 3.10 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H'0000 0000 → FRn FLDI0 1111nnnn10001101 — — — H'3F80 0000 → FRn FLDI1 1111nnnn10011101 — — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — —...
Page 142: Table 3.11 Floating-Point Double-Precision Instructions
Section 3 Instruction Set Table 3.11 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF — — — 1111nnn001011101 FFFF → DRn DRn + DRm → DRn FADD DRm,DRn — — — 1111nnn0mmm00000 When DRn = DRm, 1 →...
Page 143: Table 3.13 Floating-Point Graphics Acceleration Instructions
Section 3 Instruction Set Table 3.13 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn — — — 1111nnn1mmm01100 XDm → DRn FMOV XDm,DRn — — — 1111nnn0mmm11100 XDm → XDn FMOV XDm,XDn —...
Page 144 Section 3 Instruction Set Rev. 1.00 Oct. 01, 2007 Page 78 of 1956 REJ09B0256-0100...
Page 145: Section 4 Pipelining
Section 4 Pipelining Section 4 Pipelining This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. Pipelines Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of seven stages: instruction fetch (I1/I2), decode and register read (ID), execution (E1/E2/E3), and write-back (WB).
Page 146: Table 4.1 Representations Of Instruction Execution Patterns
Section 4 Pipelining Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.1 Representations of Instruction Execution Patterns Representation Description CPU EX pipe is occupied CPU LS pipe is occupied (with memory access) CPU LS pipe is occupied (without memory access) Either CPU EX pipe or CPU LS pipe is occupied E1/S1...
Page 147: Figure 4.2 Instruction Execution Patterns (1)
Section 4 Pipelining 1 issue cycle + 0 to 2 branch cycles (1-1) BF, BF/S, BT, BT/S, BRA, BSR: In branch instructions that are categorized Note: E1/S1 E2/s2 E3/s3 as (1-1), the number of branch cycles may be reduced by prefetching. (I1) (I2) (ID)
Page 148: Figure 4.2 Instruction Execution Patterns (2)
Section 4 Pipelining (2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT Note: Except for AND#, OR#, TST#, and XOR# instructions using GBR relative addressing mode (2-2) 1-step operation (LS type): 1 issue cycle MOVA...
Page 149: Figure 4.2 Instruction Execution Patterns (3)
Section 4 Pipelining (3-1) Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR) (3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles E1S1 E2S2 E3S3 (3-3) TAS.B: 4 issue cycles E1S1 E2S2 E3S3 E1S1 E2S2 E3S3 (3-4) PREF, OCBI, OCBP, OCBWB, MOVCA.L, SYNCO: 1 issue cycle (3-5) LDTLB: 1 issue cycle E1s1 E2s2...
Page 150: Figure 4.2 Instruction Execution Patterns (4)
Section 4 Pipelining (4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle (4-2) LDC to DBR/SGR: 4 issue cycles (4-3) LDC to GBR: 1 issue cycle (4-4) LDC to SR: 4 issue cycles + 3 branch cycles E1s1 E2s2 E3s3 (Branch to the (I1) (I2) (ID)
Page 151: Figure 4.2 Instruction Execution Patterns (5)
Section 4 Pipelining (4-9) STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-10) STC from SR: 1 issue cycle E1s1 E2s2 E3s3 (4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-12) STC.L from SR: 1 issue cycle E1S1 E2S2 E3S3 (4-13) LDS to PR: 1 issue cycle (4-14) LDS.L to PR: 1 issue cycle (4-15) STS from PR: 1 issue cycle (4-16) STS.L from PR: 1 issue cycle...
Page 152: Figure 4.2 Instruction Execution Patterns (6)
Section 4 Pipelining (5-1) LDS to MACH/L: 1 issue cycle (5-2) LDS.L to MACH/L: 1 issue cycle (5-3) STS from MACH/L: 1 issue cycle (5-4) STS.L from MACH/L: 1 issue cycle (5-5) MULS.W, MULU.W: 1 issue cycle (5-6) DMULS.L, DMULU.L, MUL.L: 1 issue cycle (5-7) CLRMAC: 1 issue cycle (5-8) MAC.W: 2 issue cycle (5-9) MAC.L: 2 issue cycle...
Page 153: Figure 4.2 Instruction Execution Patterns (7)
Section 4 Pipelining (6-1) LDS to FPUL: 1 issue cycle (6-2) STS from FPUL: 1 issue cycle (6-3) LDS.L to FPUL: 1 issue cycle (6-4) STS.L from FPUL: 1 issue cycle (6-5) LDS to FPSCR: 1 issue cycle (6-6) STS from FPSCR: 1 issue cycle (6-7) LDS.L to FPSCR: 1 issue cycle (6-8) STS.L from FPSCR: 1 issue cycle (6-9) FPU load/store instruction FMOV: 1 issue cycle...
Page 154: Figure 4.2 Instruction Execution Patterns (8)
Section 4 Pipelining (6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle (6-13) FLDI0, FLDI1: 1 issue cycle (6-14) Single-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG, FPCHG (6-15) Single-precision FDIV/FSQRT: 1 issue cycle FEDS (Divider occupied cycle) (6-16) Double-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FSUB, FTRC, FCNVSD, FCNVDS...
Page 155: Figure 4.2 Instruction Execution Patterns (9)
Section 4 Pipelining (6-19) FIPR: 1 issue cycle (6-20) FTRV: 1 issue cycle (6-21) FSRRA: 1 issue cycle FEPL Function computing unit occupied cycle (6-22) FSCA: 1 issue cycle FEPL Function computing unit occupied cycle Figure 4.2 Instruction Execution Patterns (9) Rev.
Page 156: Parallel-Executability
Section 4 Pipelining Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 4.2 Instruction Groups Instruction...
Page 157 Section 4 Pipelining Instruction Group Instruction FABS FMOV.S FR,@adr MOV.[BWL] @adr,R STC CR2,Rn FNEG FSTS MOV.[BWL] R,@adr STC.L CR2,@-Rn FLDI0 LDC Rm,CR1 MOVA STS SR2,Rn FLDI1 LDC.L @Rm+,CR1 MOVCA.L STS.L SR2,@-Rn FLDS LDS Rm,SR1 MOVUA STS SR1,Rn FMOV @adr,FR LDS Rm,SR2 OCBI STS.L SR1,@-Rn FMOV FR,@adr...
Page 158 Section 4 Pipelining The parallel execution of two instructions can be carried out under following conditions. 1. Both addr (preceding instruction) and addr+2 (following instruction) are specified within the minimum page size (1 Kbyte). 2. The execution of these two instructions is supported in table 4.3, Combination of Preceding and Following Instructions.
Page 159: Table 4.3 Combination Of Preceding And Following Instructions
Section 4 Pipelining Table 4.3 Combination of Preceding and Following Instructions Preceding Instruction (addr) Following Instruction (addr+2) Note: The following table shows the parallel-executability of pairs of instructions in this LSI. It is different from table 4.3. Preceding Instruction (addr) FLSR FLSM Following...
Page 160: Issue Rates And Execution Cycles
Section 4 Pipelining Issue Rates and Execution Cycles Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not considered in the issue rates and execution cycles in this section. 1.
Page 161: Table 4.4 Issue Rates And Execution Cycles
Section 4 Pipelining Table 4.4 Issue Rates and Execution Cycles Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Data transfer EXTS.B Rm,Rn instructions EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn Rm,Rn #imm,Rn MOVA @(disp,PC),R0 MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV.B @Rm,Rn...
Page 162 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Data transfer MOV.L Rm,@-Rn instructions MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B R0,@(disp,GBR) MOV.W R0,@(disp,GBR) MOV.L R0,@(disp,GBR) MOVCA.L R0,@Rn MOVCO.L R0,@Rn MOVLI.L...
Page 163 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Fixed-point CMP/GT Rm,Rn arithmetic CMP/HI Rm,Rn instructions CMP/HS Rm,Rn CMP/PL CMP/PZ CMP/STR Rm,Rn DIV0S Rm,Rn DIV0U DIV1 Rm,Rn DMULS.L Rm,Rn DMULU.L Rm,Rn MAC.L @Rm+,@Rn+ MAC.W @Rm+,@Rn+ MUL.L Rm,Rn...
Page 164 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Logical #imm,R0 instructions TST.B #imm,@(R0,GBR) Rm,Rn #imm,R0 XOR.B #imm,@(R0,GBR) Shift ROTL instructions ROTR ROTCL ROTCR 100 SHAD Rm,Rn 101 SHAL 102 SHAR 103 SHLD Rm,Rn 104 SHLL 105 SHLL2 106 SHLL8...
Page 165 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Branch 121 JSR instructions 122 RTS 1+0 to 3 System 123 NOP control 124 CLRMAC instructions 125 CLRS 126 CLRT 127 ICBI 8+5+3 128 SETS 129 SETT 130 PREFI 5+5+3...
Page 166 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern System 151 LDC.L @Rm+,VBR control 152 LDS Rm,MACH instructions 153 LDS Rm,MACL 154 LDS Rm,PR 4-13 155 LDS.L @Rm+,MACH 156 LDS.L @Rm+,MACL 157 LDS.L @Rm+,PR 4-14 158 STC DBR,Rn...
Page 167 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Single- 180 FLDI0 6-13 precision 181 FLDI1 6-13 floating-point 182 FMOV FRm,FRn instructions 183 FMOV.S @Rm,FRn 184 FMOV.S @Rm+,FRn 185 FMOV.S @(R0,Rm),FRn 186 FMOV.S FRm,@Rn 187 FMOV.S FRm,@-Rn 188 FMOV.S...
Page 168 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Double- 210 FABS 6-12 precision 211 FADD DRm,DRn 6-16 floating-point 212 FCMP/EQ DRm,DRn 6-16 instructions 213 FCMP/GT DRm,DRn 6-16 214 FCNVDS DRm,FPUL 6-16 215 FCNVSD FPUL,DRn 6-16 216 FDIV...
Page 169 Section 4 Pipelining Functional Instruction Execution Execution Category No. Instruction Group Issue Rate Cycles Pattern Graphics 241 FRCHG 6-14 acceleration 242 FSCHG 6-14 instructions 243 FPCHG 6-14 244 FSRRA 6-21 245 FSCA FPUL,DRn 6-22 246 FTRV XMTRX,FVn 6-20 Rev. 1.00 Oct. 01, 2007 Page 103 of 1956 REJ09B0256-0100...
Page 170 Section 4 Pipelining Rev. 1.00 Oct. 01, 2007 Page 104 of 1956 REJ09B0256-0100...
Page 171: Section 5 Exception Handling
Section 5 Exception Handling Section 5 Exception Handling Summary of Exception Handling Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing.
Page 172: Trapa Exception Register (Tra)
Section 5 Exception Handling 5.2.1 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. Bit: Initial value: R/W:...
Page 173: Exception Event Register (Expevt)
Section 5 Exception Handling 5.2.2 Exception Event Register (EXPEVT) The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs.
Page 174: Interrupt Event Register (Intevt)
Section 5 Exception Handling 5.2.3 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. Bit: Initial value: R/W: Bit:...
Page 175: Exception Handling Functions
Section 5 Exception Handling Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 176: Exception Types And Priorities
Section 5 Exception Handling Exception Types and Priorities Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.3 Exceptions Exception Transition Direction* Exception Execution Priority Priority Vector Exception Category Mode Exception Level* Order* Address Offset...
Page 177 Section 5 Exception Handling Exception Transition Direction* Exception Execution Priority Priority Vector Exception Category Mode Exception Level* Order* Address Offset Code* General Completion Unconditional trap (TRAPA) (VBR) H'100 H'160 exception type User break after instruction (VBR/DBR) H'100/— H'1E0 execution* Interrupt Completion Nonmaskable interrupt —...
Page 178: Exception Flow
Section 5 Exception Handling Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.1 shows the relative priority order of the different kinds of exceptions (reset, general exception, and interrupt).
Page 179: Figure 5.1 Instruction Execution And Exception Handling
Section 5 Exception Handling Reset requested? Execute next instruction Is highest- General priority exception exception requested? re-exception type? Cancel instruction execution result Interrupt requested? SSR ← SR EXPEVT ← exception code SPC ← PC SR. {MD, RB, BL, FD, IMASK} ← 11101111 SGR ←...
Page 180: Exception Source Acceptance
Section 5 Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline.
Page 181: Exception Requests And Bl Bit
Section 5 Exception Handling 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A0000000).
Page 182: Description Of Exceptions
Section 5 Exception Handling Description of Exceptions The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 Resets Power-On Reset • Condition: Power-on reset request •...
Page 183 Section 5 Exception Handling Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A0000000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 184: General Exceptions
Section 5 Exception Handling 5.6.2 General Exceptions Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 185 Section 5 Exception Handling Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 186 Section 5 Exception Handling Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'00000100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 187 Section 5 Exception Handling Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible...
Page 188 Section 5 Exception Handling Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H'00000100 •...
Page 189 Section 5 Exception Handling Data Address Error • Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) ...
Page 190 Section 5 Exception Handling Instruction Address Error • Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in user mode. For details, see section 8, L Memory.
Page 191 Section 5 Exception Handling Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'00000100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 192 Section 5 Exception Handling General Illegal Instruction Exception • Sources:  Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 193 Section 5 Exception Handling (10) Slot Illegal Instruction Exception • Sources:  Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR, ICBI, PREFI ...
Page 194 Section 5 Exception Handling (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD = 1 • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 195 Section 5 Exception Handling (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 196 Section 5 Exception Handling (13) Pre-Execution User Break/Post-Execution User Break • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'00000100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 197 Section 5 Exception Handling (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR .
Page 198: Interrupts
Section 5 Exception Handling 5.6.3 Interrupts NMI (Nonmaskable Interrupt) • Source: NMI pin edge detection • Transition address: VBR + H'00000600 • Transition operations: The PC and SR contents for the instruction immediately after this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 199: Priority Order With Multiple Exceptions
Section 5 Exception Handling General Interrupt Request • Source: The interrupt mask level bits setting in SR is smaller than the interrupt level of interrupt request, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'00000600 •...
Page 200 Section 5 Exception Handling With MAC instructions, memory-to-memory arithmetic/logic instructions, TAS instructions, and MOVUA instructions, two data transfers are performed by a single instruction, and an exception will be detected for each of these data transfers. In these cases, therefore, the following order is used to determine priority.
Page 201: Usage Notes
Section 5 Exception Handling Usage Notes Return from exception handling 1. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit in SR to 1 before restoring them. 2. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR contents are saved in SR, and branch is made to the SPC address to return from the exception handling routine.
Page 202 Section 5 Exception Handling bit. The completion type exception is accepted before branching to the destination of RTE instruction. However, if the re-execution type exception is occurred, the operation cannot be guaranteed. 2. The user break is not accepted by the instruction in the delay slot of the RTE instruction. Changing the SR register value and accepting exception 1.
Page 203: Section 6 Memory Management Unit (Mmu)
Section 6 Memory Management Unit (MMU) Section 6 Memory Management Unit (MMU) This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit physical address space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit (MMU) in this LSI.
Page 204 Section 6 Memory Management Unit (MMU) When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information.
Page 205: Figure 6.1 Role Of Mmu
Section 6 Memory Management Unit (MMU) Virtual Memory Physical Process 1 Physical Memory Physical Process 1 Memory Memory Process 1 Virtual Physical Process 1 Process 1 Memory Memory Physical Memory Process 2 Process 2 Process 3 Process 3 Figure 6.1 Role of MMU Rev.
Page 206: Address Spaces
Section 6 Memory Management Unit (MMU) 6.1.1 Address Spaces Virtual Address Space: This LSI supports a 32-bit virtual address space, and can access a 4- Gbyte address space. The virtual address space is divided into a number of areas, as shown in figures 6.2 and 6.3.
Page 207: Figure 6.3 Virtual Address Space (At In Mmucr = 1)
Section 6 Memory Management Unit (MMU) Physical address space H'0000 0000 H'0000 0000 Area 0 Area 1 Area 2 Area 3 P0 area U0 area Cacheable Area 4 Cacheable Address translation possible Area 5 Address translation possible Area 6 Area 7 H'8000 0000 H'8000 0000 P1 area...
Page 208 Section 6 Memory Management Unit (MMU) • P0, P3, and U0 Areas: The P0, P3, and U0 areas allow address translation using the TLB and access using the cache. When the MMU is disabled, replacing the upper 3 bits of an address with 0s gives the corresponding physical address.
Page 209: Figure 6.4 P4 Area
Section 6 Memory Management Unit (MMU) H'E000 0000 Store queue H'E400 0000 Reserved area H'E500 0000 On-chip memory area H'E600 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data array H'F400 0000...
Page 210: Figure 6.5 Physical Address Space
Section 6 Memory Management Unit (MMU) The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 7.6.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array.
Page 211 Section 6 Memory Management Unit (MMU) Address Translation: When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes.
Page 212: Register Descriptions
Section 6 Memory Management Unit (MMU) Register Descriptions The following registers are related to MMU processing. Table 6.1 Register Configuration Area 7 Register Name Abbreviation R/W P4 Address* Address* Size Page table entry high register PTEH FF00 0000 1F00 0000 Page table entry low register PTEL FF00 0004...
Page 213: Page Table Entry High Register (Pteh)
Section 6 Memory Management Unit (MMU) 6.2.1 Page Table Entry High Register (PTEH) PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN bit by hardware.
Page 214: Page Table Entry Low Register (Ptel)
Section 6 Memory Management Unit (MMU) 6.2.2 Page Table Entry Low Register (PTEL) PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued.
Page 215: Translation Table Base Register (Ttb)
Section 6 Memory Management Unit (MMU) 6.2.3 Translation Table Base Register (TTB) TTB is used to store the base address of the currently used page table, and so on. The contents of TTB are not changed unless a software directive is issued. This register can be used freely by software.
Page 216 Section 6 Memory Management Unit (MMU) Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series.
Page 217 Section 6 Memory Management Unit (MMU) Initial Bit Name Value Description  25, 24 All 0 Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 23 to 18 All 0 UTLB Replace Boundary These bits indicate the UTLB entry boundary at which replacement is to be performed.
Page 218: Physical Address Space Control Register (Pascr)
Section 6 Memory Management Unit (MMU) Initial Bit Name Value Description TLB Invalidate Bit Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit is always read as 0.  Reserved For details on reading from or writing to this bit, see description in General Precautions on Handling of Product.
Page 219: Instruction Re-Fetch Inhibit Control Register (Irmcr)
Section 6 Memory Management Unit (MMU) Initial Bit Name Value Description 7 to 0 All 0 Buffered Write Control for Each Area (64 Mbytes) When writing is performed without using the cache or in the cache write-through mode, these bits specify whether the next bus access from the CPU waits for the end of writing for each area.
Page 220 Section 6 Memory Management Unit (MMU) Bit: Initial value: R/W: Bit: Initial value: R/W: Initial Bit Name Value Description  31 to 5 All 0 Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
Page 221 Section 6 Memory Management Unit (MMU) Initial Bit Name Value Description Re-Fetch Inhibit after Writing Memory-Mapped IC This bit controls whether re-fetch is performed for the next instruction after writing memory-mapped IC while the ICE bit in CCR is set to 1. 0: Re-fetch is performed 1: Re-fetch is not performed Rev.
Page 222: Tlb Functions
Section 6 Memory Management Unit (MMU) TLB Functions 6.3.1 Unified TLB (UTLB) Configuration The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the ITLB in the event of an ITLB miss The UTLB is so called because of its use for the above two purposes.
Page 223 Section 6 Memory Management Unit (MMU) • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ[1:0]: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page •...
Page 224: Figure 6.7 Relationship Between Page Size And Address Format
Section 6 Memory Management Unit (MMU) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed •...
Page 225: Instruction Tlb (Itlb) Configuration
Section 6 Memory Management Unit (MMU) 6.3.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 6.8 shows the ITLB configuration.
Page 226: Address Translation Method
Section 6 Memory Management Unit (MMU) 6.3.3 Address Translation Method Figure 6.9 shows a flowchart of a memory access using the UTLB. Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area...
Page 227: Figure 6.10 Flowchart Of Memory Access Using Itlb
Section 6 Memory Management Unit (MMU) Figure 6.10 shows a flowchart of a memory access using the ITLB. Instruction access to virtual address (VA) VA is in P0, U0, VA is VA is VA is or P3 area in P1 area in P4 area in P2 area MMUCR.AT = 1...
Page 228: Mmu Functions
Section 6 Memory Management Unit (MMU) MMU Functions 6.4.1 MMU Hardware Management This LSI supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2.
Page 229: Mmu Instruction (Ldtlb)
Section 6 Memory Management Unit (MMU) 6.4.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, this LSI copies the contents of PTEH and PTEL to the UTLB entry indicated by the URC bit in MMUCR.
Page 230: Hardware Itlb Miss Handling
Section 6 Memory Management Unit (MMU) MMUCR 2625 2423 1817 1615 10 9 8 7 3 2 1 0 LRUI — — — TI — AT SQMD Entry specification PTEH PTEL 10 9 8 7 29 28 9 8 7 6 5 4 3 2 1 0 —...
Page 231: Avoiding Synonym Problems
Section 6 Memory Management Unit (MMU) 6.4.5 Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity.
Page 232: Mmu Exceptions
Section 6 Memory Management Unit (MMU) MMU Exceptions There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 6.9 and 6.10 for the conditions under which each of these exceptions occurs.
Page 233: Instruction Tlb Miss Exception
Section 6 Memory Management Unit (MMU) 6.5.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling routine.
Page 234: Instruction Tlb Protection Violation Exception
Section 6 Memory Management Unit (MMU) 6.5.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.
Page 235: Data Tlb Multiple Hit Exception
Section 6 Memory Management Unit (MMU) 6.5.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. When a data TLB multiple hit exception occurs, a reset is executed, and cache coherency is not guaranteed.
Page 236: Data Tlb Protection Violation Exception
Section 6 Memory Management Unit (MMU) 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry.
Page 237: Initial Page Write Exception
Section 6 Memory Management Unit (MMU) 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow.
Page 238: Memory-Mapped Tlb Configuration
Section 6 Memory Management Unit (MMU) 3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. 4. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR.
Page 239: Itlb Address Array
Section 6 Memory Management Unit (MMU) 6.6.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 240: Itlb Data Array
Section 6 Memory Management Unit (MMU) 6.6.2 ITLB Data Array The ITLB data array is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 241: Utlb Address Array
Section 6 Memory Management Unit (MMU) 6.6.3 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 242: Utlb Data Array
Section 6 Memory Management Unit (MMU) 14 13 Address field 1 1 1 1 0 1 1 0 0 0 0 0 * * * * * * * * * * 10 9 8 7 Data field ASID VPN: Virtual page number ASID: Address space identifier...
Page 243: 32-Bit Address Extended Mode
Section 6 Memory Management Unit (MMU) 14 13 Address field 1 1 1 1 0 1 1 1 0 0 0 0 * * * * * * * * * * 29 28 10 9 8 7 2 1 0 Data field PPN: Physical page number...
Page 244: Overview Of 32-Bit Address Extended Mode
Section 6 Memory Management Unit (MMU) 6.7.1 Overview of 32-Bit Address Extended Mode In 32-bit address extended mode, the privileged space mapping buffer (PMB) is introduced. The PMB maps virtual addresses in the P1 or P2 area which are not translated in 29-bit address mode to the 32-bit physical address space.
Page 245: Privileged Space Mapping Buffer (Pmb) Configuration
Section 6 Memory Management Unit (MMU) 6.7.3 Privileged Space Mapping Buffer (PMB) Configuration In 32-bit address extended mode, virtual addresses in the P1 or P2 area are translated according to the PMB mapping information. The PMB has 16 entries and configuration of each entry is as follows.
Page 246 Section 6 Memory Management Unit (MMU) • PPN: Physical page number Upper 8 bits of the physical address of the physical page number. With a 16-Mbyte page, PPN[31:24] are valid. With a 64-Mbyte page, PPN[31:26] are valid. With a 128-Mbyte page, PPN[31:27] are valid. With a 512-Mbyte page, PPN[31:29] are valid.
Page 247: Pmb Function
Section 6 Memory Management Unit (MMU) 6.7.4 PMB Function This LSI supports the following PMB functions. 1. Only memory-mapped write can be used for writing to the PMB. The LDTLB instruction cannot be used to write to the PMB. 2. Software must ensure that every accessed P1 or P2 address has a corresponding PMB entry before the access occurs.
Page 248: Memory-Mapped Pmb Configuration
Section 6 Memory Management Unit (MMU) 6.7.5 Memory-Mapped PMB Configuration To enable the PMB to be managed by software, its contents are allowed to be read from and written to by a P1 or P2 area program with a MOV instruction in privileged mode. The PMB address array is allocated to addresses H'F610 0000 to H'F61F FFFF in the P4 area and the PMB data array to addresses H'F710 0000 to H'F71F FFFF in the P4 area.
Page 249: Figure 6.18 Memory-Mapped Pmb Address Array
Section 6 Memory Management Unit (MMU) 12 11 Address field 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data field VPN: Physical page number : Reserved bits (write value should be 0 Validity bit and read value is undefined )
Page 250: Notes On Using 32-Bit Address Extended Mode
Section 6 Memory Management Unit (MMU) 6.7.6 Notes on Using 32-Bit Address Extended Mode When using 32-bit address extended mode, note that the items described in this section are extended or changed as follows. PASCR: The SE bit is added in bit 31 in the control register (PASCR). The bits 6 to 0 of the UB in the PASCR are invalid (Note that the bit 7 of the UB is still valid).
Page 251 Section 6 Memory Management Unit (MMU) • UB: Buffered write bit Specifies whether a buffered write is performed. 0: Buffered write (Subsequent processing proceeds without waiting for the write to complete.) 1: Unbuffered write (Subsequent processing is stalled until the write has completed.) In a memory-mapped TLB access, the UB bit can be read from or written to by bit 9 in the data array.
Page 252: Usage Notes
Section 6 Memory Management Unit (MMU) Usage Notes When using an LDTLB instruction instead of software to a value to the MMUCR. URC, execute 1 or 2 below. 1. In 29-bit address mode, follow A. and B. below. In 32-bit address mode, follow A. through B. below.
Page 253: Section 7 Caches
Section 7 Caches Section 7 Caches This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte operand cache (OC) for data. Features The features of the cache are given in table 7.1. This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory.
Page 254: Figure 7.1 Configuration Of Operand Cache (Oc)
Section 7 Caches The operand cache of this LSI uses the 4-way set-associative, each way comprising 256 cache lines. Figure 7.1 shows the configuration of the operand cache. The instruction cache is 4-way set-associative, each way is comprising 256 cache lines. Figure 7.2 shows the configuration of the instruction cache.
Page 255: Figure 7.2 Configuration Of Instruction Cache (Ic)
Section 7 Caches Virtual address 13 12 [12:5] Longword (LW) selection Entry selection Address array Data array (way 0 to way 3) (way 0 to way3) 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits...
Page 256: Register Descriptions
Section 7 Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each entry address.
Page 257: Cache Control Register (Ccr)
Section 7 Caches 7.2.1 Cache Control Register (CCR) CCR controls the cache operating mode, the cache write mode, and invalidation of all cache entries. CCR modifications must only be made by a program in the non-cacheable P2 area. After CCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area is performed.
Page 258 Section 7 Caches Initial Bit Name Value Description  10, 9 All 0 Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. IC Enable Bit Selects whether the IC is used. Note however when address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1.
Page 259: Queue Address Control Register 0 (Qacr0)
Section 7 Caches Initial Bit Name Value Description OC Enable Bit Selects whether the OC is used. Note however when address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used 7.2.2...
Page 260: Queue Address Control Register 1 (Qacr1)
Section 7 Caches 7.2.3 Queue Address Control Register 1 (QACR1) QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled. Bit: Initial value: R/W: Bit: AREA1 Initial value: R/W: Initial Bit Name Value Description ...
Page 261: On-Chip Memory Control Register (Ramcr)
Section 7 Caches 7.2.4 On-Chip Memory Control Register (RAMCR) RAMCR controls the number of ways in the IC and OC. RAMCR modifications must only be made by a program in the non-cacheable P2 area. After RAMCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area or the L memory area is performed.
Page 262 Section 7 Caches Initial Bit Name Value Description On-Chip Memory Protection Enable Bit For details, see section 8.4, L Memory Protective Functions. IC2W IC Two-Way Mode bit 0: IC is a four-way operation 1: IC is a two-way operation For details, see section 7.4.3, IC Two-Way Mode. OC2W OC Two-Way Mode bit 0: OC is a four-way operation...
Page 263: Operand Cache Operation
Section 7 Caches Operand Cache Operation 7.3.1 Read Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is read from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 264: Prefetch Operation
Section 7 Caches 5. Cache miss (with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address.
Page 265: Write Operation
Section 7 Caches 5. Cache miss (with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then data is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address.
Page 266 Section 7 Caches 5. Cache miss (copy-back, no write-back) A data write in accordance with the access size is performed for the data of the data field on the hit way which is indexed by virtual address bits [4:0]. Then, the data, excluding the cache- missed data which is written already, is read into the cache line on the way which is selected to replace from the physical address space corresponding to the virtual address.
Page 267: Write-Back Buffer
Section 7 Caches 7.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, this LSI has a write- back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss.
Page 268: Instruction Cache Operation
Section 7 Caches Instruction Cache Operation 7.4.1 Read Operation When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, U bit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 269: Prefetch Operation
Section 7 Caches 7.4.2 Prefetch Operation When the IC is enabled (ICE = 1 in CCR) and instruction prefetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, Ubit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 270: Cache Operation Instruction
Section 7 Caches Cache Operation Instruction 7.5.1 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In this LSI, the following six instructions are supported for cache operations. Details of these instructions are given in the Programming Manual.
Page 271: Prefetch Operation
Section 7 Caches PURGE transaction: When the operand cache is enabled, the PURGE transaction checks the operand cache and invalidates the hit entry. If the invalidated entry is dirty, the data is written back to the external memory. If the transaction is not hit to the cache, it is no-operation. FLUSH transaction: When the operand cache is enabled, the FLUSH transaction checks the operand cache and if the hit line is dirty, then the data is written back to the external memory.
Page 272: Memory-Mapped Cache Configuration
Section 7 Caches Memory-Mapped Cache Configuration To enable the IC and OC to be managed by software, the IC contents can be read from or written to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area.
Page 273: Figure 7.5 Memory-Mapped Ic Address Array
Section 7 Caches In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed.
Page 274: Ic Data Array
Section 7 Caches 7.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 275: Oc Address Array
Section 7 Caches 7.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 276: Oc Data Array
Section 7 Caches 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag in each way stored in the entry specified in the address field is compared with the tag specified in the data field.
Page 277: Figure 7.8 Memory-Mapped Oc Data Array
Section 7 Caches The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field.
Page 278: Store Queues
Section 7 Caches Store Queues This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. 7.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 7.9. These two store queues can be set independently.
Page 279: Transfer To External Memory
Section 7 Caches 7.7.3 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a transfer from the SQs to external memory.
Page 280: Determination Of Sq Access Exception
Section 7 Caches Physical address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. 7.7.4 Determination of SQ Access Exception Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is enabled or disabled.
Page 281: Notes On Using 32-Bit Address Extended Mode
Section 7 Caches Notes on Using 32-Bit Address Extended Mode In 32-bit address extended mode, the items described in this section are extended as follows. 1. The tag bits [28:10] (19 bits) in the IC and OC are extended to bits [31:10] (22 bits). 2.
Page 282 Section 7 Caches Rev. 1.00 Oct. 01, 2007 Page 216 of 1956 REJ09B0256-0100...
Page 283: Section 8 L Memory
Section 8 L Memory Section 8 L Memory This LSI includes on-chip L-memory which stores instructions or data. Features • Capacity Total L memory capacity is 16 Kbytes. • Page The L memory is divided into two pages (pages 0 and 1). •...
Page 284: Register Descriptions
Section 8 L Memory Register Descriptions The following registers are related to L memory. Table 8.2 Register Configuration Area 7 Name Abbreviation P4 Address* Address* Access Size On-chip memory control RAMCR H'FF000074 H'1F000074 register L memory transfer source LSA0 H'FF000050 H'1F000050 address register 0 L memory transfer source...
Page 285: Table 8.3 Register Status In Each Processing State
Section 8 L Memory Table 8.3 Register Status in Each Processing State Power-On Name Abbreviation Reset Manual Reset Sleep Standby On-chip memory control RAMCR H'00000000 H'00000000 Retained Retained register L memory transfer LSA0 Undefined Undefined Retained Retained source address register L memory transfer LSA1 Undefined...
Page 286: On-Chip Memory Control Register (Ramcr)
Section 8 L Memory 8.2.1 On-Chip Memory Control Register (RAMCR) RAMCR controls the protective functions in the L memory. Bit : Initial value : R/W: Bit : IC2W OC2W Initial value : R/W: Initial Bit Name Value Description 31to10 — All 0 Reserved For read/write in these bits, refer to General...
Page 287: L Memory Transfer Source Address Register 0 (Lsa0)
Section 8 L Memory Initial Bit Name Value Description 5 to 0 — All 0 Reserved For read/write in these bits, refer to General Precautions on Handling of Product. 8.2.2 L Memory Transfer Source Address Register 0 (LSA0) When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA0 specifies the transfer source physical address for block transfer to page 0 of the L memory.
Page 288 Section 8 L Memory Initial Bit Name Value Description 5 to 0 L0SSZ Undefined R/W L Memory Page 0 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to the L memory.
Page 289: L Memory Transfer Source Address Register 1 (Lsa1)
Section 8 L Memory 8.2.3 L Memory Transfer Source Address Register 1 (LSA1) When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA1 specifies the transfer source physical address for block transfer to page 1 in the L memory. Bit : L1SADR Initial value : R/W:...
Page 290 Section 8 L Memory Initial Bit Name Value Description 5 to 0 L1SSZ Undefined R/W L Memory Page 1 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 1 in the L memory.
Page 291: L Memory Transfer Destination Address Register 0 (Lda0)
Section 8 L Memory 8.2.4 L Memory Transfer Destination Address Register 0 (LDA0) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifies the transfer destination physical address for block transfer to page 0 of the L memory. Bit : L0DADR Initial value : R/W:...
Page 292 Section 8 L Memory Initial Bit Name Value Description 5 to 0 L0DSZ Undefined R/W L Memory Page 0 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 0 in the L memory.
Page 293: L Memory Transfer Destination Address Register 1 (Lda1)
Section 8 L Memory 8.2.5 L Memory Transfer Destination Address Register 1 (LDA1) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifies the transfer destination physical address for block transfer to page 1 in the L memory. Bit : L0SADR Initial value : R/W:...
Page 294 Section 8 L Memory Initial Bit Name Value Description 5 to 0 L1DSZ Undefined R/W L Memory Page 1 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 1 in the L memory.
Page 295: Operation
Section 8 L Memory Operation 8.3.1 Access from the CPU and FPU L memory access from the CPU and FPU is direct via the instruction bus and operand bus by means of the virtual address. As long as there is no conflict on the page, the L memory is accessed in one cycle.
Page 296 Section 8 L Memory of the OCBWB instruction) to the PPN field. The ASID, V, SZ, SH, PR, and D bits have the same meaning as normal address conversion; however, the C and WT bits have no meaning in this page. When the PREF instruction is issued to the L memory area, address conversion is performed in order to generate the physical address bits [28:10] in accordance with the SZ bit specification.
Page 297: L Memory Protective Functions
Section 8 L Memory When the OCBWB instruction is issued to the L memory area, the physical address bits [28:10] are generated in accordance with the LDA0 or LDA1 specification. The physical address bits [9:5] are generated from the virtual address. The physical address bits [4:0] are fixed to 0. Block transfer is performed from the L memory to the external memory specified by these physical addresses.
Page 298: Usage Notes
Section 8 L Memory Usage Notes 8.5.1 Page Conflict In the event of simultaneous access to the same page from different buses, page conflict occurs. Although each access is completed correctly, this kind of conflict tends to lower L memory accessibility.
Page 299: Section 9 Interrupt Controller (Intc)
Section 9 Interrupt Controller (INTC) Section 9 Interrupt Controller (INTC) The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU (SH-4A). The INTC has a register that sets the priority of each interrupt and interrupt requests are processed according to the priority set in this register by the user.
Page 300: Figure 9.1 Block Diagram Of Intc
Section 9 Interrupt Controller (INTC) Input exception control IRQ7/IRL7 to handing Comparator IRQ0/IRL0 Interrupt Priority determination SR.IMASK USERIMASK.UIMASK INTPRI interface ICR0, ICR1 GPIO ports PINT15 GPIO interrupt to PINT0 On- chip Module Interrupt request Interrupt Prority Interrupt request H-UDI determination Interrupt request DMAC Interrupt request...
Page 301: Interrupt Method
Section 9 Interrupt Controller (INTC) 9.1.1 Interrupt Method The basic exception handling flow for the interrupt is as follows. In interrupt exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate interrupt exception handling routine according to the vector address.
Page 302: Interrupt Types In Intc
The external interrupts is the interrupt input from external pins, NMI, IRL, and IRQ. The IRQ and IRL are assigned to the same pin in the SH7763. The pin function is selected according to the system.
Page 303 Section 9 Interrupt Controller (INTC) Number of Sources Source Priority INTEVT Remarks (Max.) IRL[7:4] pin = H'9 External Inversion values of input H'320 High interrupts pin values (because of interrupt* IRL[3:0] pin = H'9 negative pins) IRL[7:4] pin = H'A H'340 For example IRL[7:4] pin = H'0 means...
Page 304 Section 9 Interrupt Controller (INTC) Number of Sources Source Priority INTEVT Remarks (Max.) LCDC Setting value of INT2PRI0 H'620 LCDCI On-chip to INT2PRI13 module DMAC 7(5/7) H'640 DMTE0 interrupts* H'660 DMTE1 H'680 DMTE2 H'6A0 DMTE3 H'6C0 DMAE SCIF0 H'700 ERI0 H'720 RXI0 H'740...
Page 305 Section 9 Interrupt Controller (INTC) Number of Sources Source Priority INTEVT Remarks (Max.) SCIF1 Setting value of INT2PRI0 H'B80 ERI1 On-chip to INT2PRI13 module H'BA0 RXI1 interrupts* H'BC0 BRI1 H'BE0 TXI1 SIOF0 H'C00 SIOFI0 SIOF1 H'C20 SIOFI1 SIOF2 H'C40 SIOFI2 USBH H'C60 USBHI...
Page 306: Input/Output Pins
Section 9 Interrupt Controller (INTC) Number of Sources Source Priority INTEVT Remarks (Max.) GPIO Setting value of INT2PRI0 H'F80 On-chip to INT2PRI13 module H'FA0 interrupts* H'FC0 H'FE0 Notes: 1. Since the IRL interrupt request by IRL[3:0] (IRQ3/IRL3 to IRQ0/IRL0 pins) and IRL interrupt request by IRL[7:4] (IRQ7/IRL7 to IRQ4/IRL4 pins) have the same INTEVT codes, it is impossible to distinguish the former from the latter.
Page 307: Register Descriptions
Section 9 Interrupt Controller (INTC) Pin Name Function Description IRQ7/IRL7 to External interrupt input pin Input Interrupt request signal input IRQ4/IRL4 IRL [7:4] 4-bit level-encoded interrupt input when ICR0.IRLM1 = 0 IRQ7 to IRQ4 individual interrupt input when ICR0.IRLM1 = 1 IRQOUT Interrupt request output Output...
Page 308 Section 9 Interrupt Controller (INTC) Area 7 Access Name Abbreviation P4 Address Address Size NMI flag control register NMIFCR R/(W) H'FFD0 00C0 H'1FD0 00C0 User interrupt mask level USERIMASK H'FFD3 0000 H'1FD3 0000 register Interrupt priority register 0 INT2PRI0 H'FFD4 0000 H'1FD4 0000 Interrupt priority register 1 INT2PRI1...
Page 309 Section 9 Interrupt Controller (INTC) Area 7 Access Name Abbreviation P4 Address Address Size Individual module interrupt INT2B2 H'FFD4 0048 H'1FD4 0048 source register 2 Individual module interrupt INT2B3 H'FFD4 004C H'1FD4 004C source register 3 Individual module interrupt INT2B4 H'FFD4 0050 H'1FD4 0050 source register 4...
Page 310 Section 9 Interrupt Controller (INTC) Table 9.4 Register States in Each Operating Mode Power-on Name Abbreviation Reset Manual Reset Sleep Standby Interrupt control register 0 ICR0 H'x000 0000 H'x000 0000 Retained Retained Interrupt control register 1 ICR1 H'0000 0000 H'0000 0000 Retained Retained Interrupt priority register INTPRI...
Page 311 Section 9 Interrupt Controller (INTC) Power-on Name Abbreviation Reset Manual Reset Sleep Standby Interrupt source register 1 INT2A1 H'0000 0000 H'0000 0000 Retained Retained (mask state is affected) Interrupt source register 11 INT2A11 H'0000 0000 H'0000 0000 Retained Retained (mask state is affected) Interrupt mask register INT2MSKR H'FFFF FFFF...
Page 312: Interrupt Control Register 0 (Icr0)
Section 9 Interrupt Controller (INTC) 9.3.1 Interrupt Control Register 0 (ICR0) ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode of the external interrupt input pins (IRQ7/IRL7 to IRQ0/IRL0) and NMI pin, and indicates the input level to the NMI pin.
Page 313 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description NMIB NMI Block Mode Selects whether an NMI interrupt is held until the BL bit in SR is cleared to 0 or detected immediately when the BL bit in SR of the CPU is set to 1. 0: An NMI interrupt is held when the BL bit in SR is set to 1 (initial value) 1: An NMI interrupt is not held when the BL bit in SR is...
Page 314: Interrupt Control Register 1 (Icr1)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description IRLM1 IRL Pin Mode 1 Selects whether IRQ7/IRL7 to IRQ4/IRL4 are used as the 4-bit encoded interrupt requests or as four independent interrupts. 0: IRQ7/IRL7 to IRQ4/IRL4 are used as the 4-bit level- encoded interrupt requests (IRL [7:4] interrupt;...
Page 315: Interrupt Priority Register (Intpri)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description 31, 30 IRQ0S IRQn Sense Select (n = 0 to 7) 29, 28 IRQ1S Selects whether interrupt signals to the IRQ7/IRL7 to IRQ0/IRL0 pins are detected at the rising edge, falling 27, 26 IRQ2S edge, high level, or low level.
Page 316: Interrupt Source Register (Intreq)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description 31 to 28 IP0 Set priority of an independent interrupt request of IRQ0. 27 to 24 IP1 Set priority of an independent interrupt request of IRQ1. 23 to 20 IP2 Set priority of an independent interrupt request of IRQ2.
Page 317: Interrupt Mask Register 0 (Intmsk0)
Section 9 Interrupt Controller (INTC) Description At Edge Detection At Level Detection Initial (IRQnS = 00 or 01, (IRQnS = 10 or 11, Bit Name Value n = 0 to 7) n = 0 to 7) [When reading] [When reading] 0: A corresponding IRQ 0: A corresponding IRQ interrupt request is not...
Page 318 Section 9 Interrupt Controller (INTC) Bit: − − − − − − − − IM00 IM01 IM06 IM07 IM02 IM03 IM04 IM05 Initial value: R/W: Bit: − − − − − − − − − − − − − − −...
Page 319: Interrupt Mask Register 1 (Intmsk1)
Section 9 Interrupt Controller (INTC) 9.3.6 Interrupt mask register 1 (INTMSK1) INTMSK1 is 32-bit readable and writable with conditions registers that control mask settings for each interrupt request. To clear the mask settings for interrupts, write 1 to the corresponding bits in INTMSKCLR1.
Page 320: Interrupt Mask Register 2 (Intmsk2)
Section 9 Interrupt Controller (INTC) 9.3.7 Interrupt mask register 2 (INTMSK2) INTMSK2 is 32-bit readable and writable with conditions registers that control mask settings for each interrupt request. To clear the mask settings for interrupts, write 1 to the corresponding bits in INTMSKCLR2.
Page 321 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description IM009 Sets masking of an [When reading] interrupt request when 0: Interrupts are accepted IRL [3:0] = LHHL (H'6). 1: Interrupts are masked IM008 Sets masking of an [When writing] interrupt request when IRL [3:0] = LHHH (H'7).
Page 322 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description IM115 Sets masking of an [When reading] interrupt request when 0: Interrupts are accepted IRL [7:4] = LLLL (H'0). 1: Interrupts are masked IM114 Sets masking of an [When writing] interrupt request when IRL [7:4] = LLLH (H'1).
Page 323: Interrupt Mask Clear Register 0 (Intmskclr0)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description IM103 Sets masking of an [When reading] interrupt request when 0: Interrupts are accepted IRL [7:4] = HHLL (H'C). 1: Interrupts are masked IM102 Sets masking of an [When writing] interrupt request when IRL [7:4] = HHLH (H'D).
Page 324 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description IC00 Clears masking of an [When reading] independent interrupt An undefined value is request of IRQ0. read. IC01 Clears masking of an [When writing] independent interrupt 0: Invalid request of IRQ1. 1: Clears the IC02 Clears masking of an...
Page 325: Interrupt Mask Clear Register 1 (Intmskclr1)
Section 9 Interrupt Controller (INTC) 9.3.9 Interrupt mask clear register 1 (INTMSKCLR1) INTMSKCLR1 is 32-bit write-only registers that clear the mask settings for IRL interrupt requests. An undefined value is read. Bit: − − − − − − − − −...
Page 326: Interrupt Mask Clear Register 2 (Intmskclr2)
Section 9 Interrupt Controller (INTC) 9.3.10 Interrupt mask clear register 2 (INTMSKCLR2) INTMSKCLR2 is 32-bit write-only registers that clear the mask settings for IRL interrupt requests. An undefined value is read. Bit: − IC015 IC014 IC009 IC008 IC007 IC006 IC013 IC012 IC011 IC010...
Page 327 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description IC007 Clears masking of an [When reading] interrupt request when An undefined value is IRL[3:0] = HLLL (H'8). read. IC006 Clears masking of an [When writing] interrupt request when IRL[3:0] = HLLH (H'9). 0: Invalid 1: Clears the IC005...
Page 328 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description IC111 Clears masking of an [When reading] interrupt request when An undefined value is IRL[7:4] = LHLL (H'4). read. IC110 Clears masking of an [When writing] interrupt request when IRL[7:4] = LHLH (H'5). 0: Invalid 1: Clears the IC109...
Page 329: Nmi Flag Control Register (Nmifcr)
Section 9 Interrupt Controller (INTC) 9.3.11 NMI Flag Control Register (NMIFCR) NMIFCR is a 32-bit readable and partially writable with conditions register that has an NMI flag (NMIFL bit) that can be read or cleared by software. The NMIFL bit is automatically set to 1 by hardware when an NMI interrupt is detected by the INTC.
Page 330: User Interrupt Mask Level Register (Userimask)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Description NMIFL NMI Interrupt Request Signal Detection Indicates whether an NMI interrupt request signal has been detected. This bit is automatically set to 1 when the INTC detects an NMI interrupt request. Write 0 to clear the bit.
Page 331 Section 9 Interrupt Controller (INTC) To prevent incorrect writing, this register can only be written to with bits 31 to 24 set to H'A5. Bit: − − − − − − − − − − − − − − − −...
Page 332: On-Chip Module Interrupt Priority Registers (Int2Pri0 To Int2Pri13)
Section 9 Interrupt Controller (INTC) UIMASK level are held disabled, and correct operation may not be performed (for example, the OS cannot switch tasks). An example of the usage procedure is shown below. 1. Classify interrupts to A and B as described below and set the A priority higher than the B priority.
Page 333 Section 9 Interrupt Controller (INTC) Table 9.5 shows the correspondence between interrupt request sources and bits in INT2PRI0 to INT2PRI13. Table 9.5 Interrupt Request Sources and INT2PRI0 to INT2PRI13 Register 28 to 24 20 to 16 12 to 8 4 to 0 INT2PRI0 TMU0 (TUNI0) TMU0 (TUNI1)
Page 334: Interrupt Source Register 0 (Mask State Is Not Affected) (Int2A0)
Section 9 Interrupt Controller (INTC) 9.3.14 Interrupt Source Register 0 (Mask State is not affected) (INT2A0) INT2A0 (mask state is not affected) is a 32-bit read-only register that indicates interrupt source modules. Even if interrupt masking is set in the interrupt mask register, INT2A0 indicates a source module in a corresponding bit (the corresponding interrupt is not generated).
Page 335: Interrupt Source Register 01 (Mask State Is Not Affected) (Int2A01)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description Indicates CMT interrupt source Indicates interrupt sources for each 11 to 9 — All 0 This bit is always read as 0. The peripheral module write value should always be 0. (INT2A0 is not DMAC Indicates DMAC interrupt source...
Page 336 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description 31 to 26 — All 0 This bit is always read as 0. Indicates interrupt The write value should sources for each always be 0. peripheral module (INT2A01 is not affected SCIF2 Indicates SCIF2 interrupt by the state of the...
Page 337 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description SIOF2 Indicates SIOF2 interrupt Indicates interrupt source sources for each peripheral module SIOF1 Indicates SIOF1 interrupt (INT2A01 is not affected source by the state of the LCDC Indicates LCDC interrupt interrupt mask register).
Page 338: Interrupt Source Register (Mask State Is Affected) (Int2A1)
Section 9 Interrupt Controller (INTC) 9.3.16 Interrupt Source Register (Mask State is affected) (INT2A1) INT2A1 (mask state is affected) is a 32-bit read-only register that indicates interrupt source modules. Note that if interrupt masking is set in the interrupt mask register, INT2A1 does not indicate a source module in a corresponding bit.
Page 339 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description PCIC3 Indicates PCIC3 interrupt source Indicates interrupt sources for each PCIC2 Indicates PCIC2 interrupt source peripheral module PCIC1 Indicates PCIC1 interrupt source (INT2A1 is affected by the state of the PCIC0 Indicates PCIC0 interrupt source interrupt mask...
Page 340: Interrupt Source Register 11 (Mask State Is Affected) (Int2A11)
Section 9 Interrupt Controller (INTC) 9.3.17 Interrupt Source Register 11 (Mask State is affected) (INT2A11) INT2A11 (mask state is affected) is a 32-bit read-only register that indicates interrupt source modules. Note that if interrupt masking is set in the interrupt mask register, INT2A11 does not indicate a source module in a corresponding bit.
Page 341 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description USBH Indicates USBH interrupt Indicates interrupt source sources for each peripheral module GETHER Indicates GETHER interrupt (INT2A11 is affected source by the state of the Indicates PCC interrupt source interrupt mask register).
Page 342: Interrupt Mask Register (Int2Mskr)
Section 9 Interrupt Controller (INTC) 9.3.18 Interrupt Mask Register (INT2MSKR) INT2MSKR is a 32-bit readable/writable register that sets masking for each source indicated in the interrupt source register. Interrupts whose corresponding bits in INT2MSKRG are set to 1 are not notified to the CPU. INT2MSKR is initialized to H'FFFF FFFF (mask state) by a reset.
Page 343: Interrupt Mask Register 1 (Int2Mskr1)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description Masks HAC interrupts Masks interrupts for each peripheral Masks CMT interrupts module. 11 to 9 — All 1 These bits are always read as 1. [When writing] The write value should always be 0: Invalid 1: Interrupts are DMAC...
Page 344 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description 31 to 26 — All 1 These bits are always read as 1. Masks interrupts for The write value should always each peripheral be 1. module. [When writing] SCIF2 Masks SCIF2 interrupts 0: Invalid USBF...
Page 345: Interrupt Mask Clear Register (Int2Mskcr)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description SSI2 Masks SSI2 interrupts Masks interrupts for each peripheral SSI1 Masks SSI1 interrupts module. Masks SECURITY interrupts SECURITY* [When writing] 0: Invalid 1: Interrupts are masked [When reading] 0: No mask setting 1: Mask setting Note: This bit is reserved in the R5S77631.
Page 346 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description 31 to 26 — All 0 These bits are always read as Clears interrupt 0. The write value should masking for each always be 0 peripheral module. [When writing] GPIO Clears GPIO interrupt masking...
Page 347: Interrupt Mask Clear Register 1 (Int2Mskcr1)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description H-UDI Clears H-UDI interrupt Clears interrupt masking masking for each peripheral module. — This bit is always read as 0. [When writing] The write value should always be 0 0: Invalid Clears WDT interrupt masking 1: Interrupt mask is...
Page 348 Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description 31 to 26 — All 0 These bits are always read as Clears interrupt 0. The write value should masking for each always be 0 peripheral module. [When writing] SCIF2 Clears SCIF2 interrupt masking 0: Invalid...
Page 349: On-Chip Module Interrupt Source Registers (Int2B0 To Int2B7 And Int2B9 To Int2B11)
Section 9 Interrupt Controller (INTC) Initial Bit Name Value Function Description SSI1 Clears SSI1 interrupt masking Clears interrupt masking for each peripheral Clears SECURITY interrupt SECURITY* module. masking [When writing] 0: Invalid 1: Interrupt mask is cleared [When reading] Always 0 Note: This bit is reserved in the R5S77631.
Page 350 Section 9 Interrupt Controller (INTC) INT2B0: Indicates detailed interrupt sources for the TMU. Module Source Function Description 31 to 7 — These bits are always read as 0. The Indicates TMU interrupt write value should always be 0. sources. This register indicates the TMU TUNI5 TMU channel 5 underflow interrupt...
Page 351 Section 9 Interrupt Controller (INTC) Module Source Function Description SCIF0 TXI0 SCIF channel 0 transmit FIFO data Indicates SCIF interrupt empty interrupt sources. This register indicates the SCIF BRI0 SCIF channel 0 break interrupt or interrupt sources even if overrun error interrupt mask setting is made in RXI0 SCIF channel 0 receive FIFO data full...
Page 352 Section 9 Interrupt Controller (INTC) INT2B4: Indicates detailed interrupt sources for the PCIC. Module Source Function Description PCIC 31 to 10 — These bits are always read as 0. The Indicates PCIC interrupt write value should always be 0. sources. This register indicates the PCIC PWD0 PCIC power state D0 state interrupt...
Page 353 Section 9 Interrupt Controller (INTC) INT2B6: Indicates detailed interrupt sources for the SCIF2. Module Source Function Description SCIF2 31 to 4 — These bits are always read as 0. The Indicates SCIF2 write value should always be 0. interrupt sources. This register indicates the TXI2 SCIF channel 2 transmit FIFO data...
Page 354 Section 9 Interrupt Controller (INTC) Module Source Function Description GPIO PINT6I GPIO interrupt from PINT6 pin Indicates GPIO interrupt sources. This register PINT5I GPIO interrupt from PINT5 pin indicates GPIO interrupt PINT4I GPIO interrupt from PINT4 pin sources even if mask setting is made in the 7 to 4 —...
Page 355: Gpio Interrupt Set Register ( Int2Gpic )
Section 9 Interrupt Controller (INTC) INT2B11: Indicates detailed interrupt sources for the SIM. Module Source Function Description 31 to 4 — These bits are always read as 0. The Indicates SIM interrupt write value should always be 0. sources. This register indicates the SIM TEND Transmit end interrupt...
Page 356 Section 9 Interrupt Controller (INTC) Initial Bit Name Value R/W Function Description 31 to 28 — All 0 Reserved Enables a GPIO interrupt request for These bits are always read as 0. each pin. The write value should always be 0. 0: Disables an interrupt request PINT15E...
Page 357 Section 9 Interrupt Controller (INTC) Initial Bit Name Value R/W Function Description PINT7E R/W Enables a GPIO interrupt Enables a GPIO request from PINT7 pin interrupt request for each pin. PINT6E R/W Enables a GPIO interrupt 0: Disables an interrupt request from PINT6 pin request PINT5E...
Page 358: Interrupt Sources
Section 9 Interrupt Controller (INTC) Interrupt Sources There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip modules. Each interrupt has a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored.
Page 359: Irl Interrupts
(interrupt priority level 15), and all high level indicates no interrupt request (interrupt priority level 0). Figure 9.2 shows an example of IRL interrupt connection, and table 9.6 shows the correspondence between the IRL pins and interrupt levels. SH7763 Interrupt Priprity IRQ3/IRL3 to...
Page 360: Table 9.6 Rl[3:0], Irl[7:4] Pins And Interrupt Levels
Section 9 Interrupt Controller (INTC) Table 9.6 RL[3:0], IRL[7:4] Pins and Interrupt Levels IRL3 or IRL2 or IRL1 or IRL0 or Interrupt IRL7 IRL6 IRL5 IRL4 Priority Level Interrupt Request Level 15 Interrupt Request High Level 14 Interrupt Request High Level 13 Interrupt Request High High...
Page 361: On-Chip Module Interrupts
Section 9 Interrupt Controller (INTC) 9.4.4 On-chip Module Interrupts On-chip module interrupts are interrupts generated by on-chip modules. Not every interrupt source is assigned a different interrupt vector, but sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT value as a branch offset in the exception handling routine.
Page 362: Interrupt Exception Handling And Priority
Section 9 Interrupt Controller (INTC) and determines the priorities of individual interrupt sources. The lowest one bit is then rounded off, the data is converted to 4-bit data, and the priority levels are notified. For example, two interrupt sources whose priority levels are set to H'1A and H'1B are both output as 4-bit priority level H'D.
Page 363: Table 9.7 Interrupt Exception Handling And Priority
Section 9 Interrupt Controller (INTC) The priority order of the on-chip modules is specified as desired by setting priority levels from 31 to 0 in INT2PRI0 to INT2PRI14. The priority order of the on-chip modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 9.7.
Page 364 Section 9 Interrupt Controller (INTC) Interrupt Detail Priority INTEVT Interrupt MASK/CLEAR Source Source in the Default Interrupt Source Code Priority Register Register Register Source Priority IRL[7:4] = LHLH H'2A0 10 — — High INTMSK2[10] (H'5) L: Low INTMSKCLR2[10] level IRL[3:0] = LHLH —...
Page 365 Section 9 Interrupt Controller (INTC) Interrupt Detail Priority INTEVT Interrupt MASK/CLEAR Source Source in the Default Interrupt Source Code Priority Register Register Register Source Priority IRL[7:4] = HHLL H'380 3 — — High INTMSK2[3] (H'C) L: Low INTMSKCLR2[3] level IRL[3:0] = HHLL —...
Page 366 Section 9 Interrupt Controller (INTC) Interrupt Detail Priority INTEVT Interrupt MASK/CLEAR Source Source in the Default Interrupt Source Code Priority Register Register Register Source Priority H'480 High High INT2PRI INT2MSKR[2] INT2A0[2] INT2B1[0] 1[4:0] H'4A0 INT2MSKCR[2] INT2A1[2] INT2B1[1] H'4C0 INT2B1[2] SECI H'4E0 —...
Page 367 Section 9 Interrupt Controller (INTC) Interrupt Detail Priority INTEVT Interrupt MASK/CLEAR Source Source in the Default Interrupt Source Code Priority Register Register Register Source Priority SCIF0 ERI0* H'700 High High INT2PRI2 INT2MSKR[3] INT2A0[3] INT2B2[0] [28:24] RXI0* H'720 INT2MSKCR[3] INT2A1[3] INT2B2[1] BRI0* H'740 INT2B2[2]...
Page 368 Section 9 Interrupt Controller (INTC) Interrupt Detail Priority INTEVT Interrupt MASK/CLEAR Source Source in the Default Interrupt Source Code Priority Register Register Register Source Priority PCIC5 PCIERR H'AA0 High High INT2PRI5 INT2MSKR[19] INT2A0[19] INT2B4[5] [4:0] PCIPWD3 H'AC0 INT2MSKCR[19] INT2A1[19] INT2B4[6] PCIPWD2 H'AE0 INT2B4[7]...
Page 369 Section 9 Interrupt Controller (INTC) Interrupt Detail Priority in INTEVT Interrupt MASK/CLEAR Source Source Default Interrupt Source Code Priority Register Register Register Source Priority H'CC0 INT2A01 — High INT2PRI10 INT2MSKR1[11] [11] [28:24] INT2MSKCR1 INT2A11 [11] [11] PCCI H'CE0 INT2A01 — INT2PRI11 INT2MSKR1[15] [15]...
Page 370 Section 9 Interrupt Controller (INTC) Interrupt Detail Priority INTEVT Interrupt MASK/CLEAR Source Source in the Default Interrupt Source Code Priority Register Register Register Source Priority SSI2 SSII2 H'EC0 — High INT2PRI8 INT2MSKR1[2] INT2A01[2] [20:16] INT2MSKCR1[2] INT2A11[2] SSI3 SSII3 H'EE0 — INT2PRI8 INT2MSKR1[3] INT2A01[3]...
Page 371: Operation
Section 9 Interrupt Controller (INTC) Operation 9.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 9.4 is the flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the INTC. 2. The INTC selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in INTPRI and INT2PRI0 to INT2PRI14.
Page 372: Figure 9.4 Interrupt Operation Flowchart
Section 9 Interrupt Controller (INTC) Program execution state ICR0.MAI=1? NMI input is low? Interrupt generated? SR.BL = 0 or Sleep mode? ICR0.NMIB=1? NMI? NMI? Level 15 interrupt? Level 14 interrupt? SR. IMASK level is 14 or low Level 1 interrupt? SR.
Page 373: Multiple Interrupts
Section 9 Interrupt Controller (INTC) 9.5.2 Multiple Interrupts When handling multiple interrupts, an interrupt handling routine should include the following procedures: 1. To identify the interrupt source, branch to a specific interrupt handling routine for the interrupt source by using the INTEVT code as an offset. 2.
Page 374: Interrupt Response Time
Section 9 Interrupt Controller (INTC) Interrupt Response Time Table 9.8 shows the interrupt response time, which is the interval from when an interrupt request occurs until the interrupt exception handling is started and the start instruction of the exception handling routine is fetched. Table 9.8 Interrupt Response Time Number of States...
Page 375: Usage Notes
Section 9 Interrupt Controller (INTC) Usage Notes 9.7.1 Example of Interrupt Handling Routine for Level-Encoded IRL and Level-Sensed If an interrupt request is accepted when level-sensed IRQ or level-encoded IRL interrupt request is selected, the held request must be cleared in the interrupt handling routine. Figure 9.5 shows an example of clearing the interrupt request held in the detection circuit.
Page 376: Notes On Setting Irq7/Irl7 To Irq0/Irl0 Pin Function
Section 9 Interrupt Controller (INTC) INTMSK0/INTMSK1 and INTMSKCLR0/INTMSKCLR1 and reading from INTMSK0/INTMSK1 should be consecutively executed. 9.7.2 Notes on Setting IRQ7/IRL7 to IRQ0/IRL0 Pin Function When switching the IRQ7/IRL7 to IRQ0/IRL0 pin function, it is possible that the INTC may hold an interrupt by mistake.
Page 377 Section 9 Interrupt Controller (INTC) • To clear IRQ edge-detection interrupt requests To clear an IRQ edge-detection interrupt request from the IRQ7/IRL7 to IRQ0/IRL0 pins, write 0 after reading 1 in the corresponding IRn (n = 0 to 7) bit in INTREQ. The IRQ interrupt requests detected by the INTC is not cleared even if 1 is written to a corresponding bit in INTMSK0.
Page 378 Section 9 Interrupt Controller (INTC) Rev. 1.00 Oct. 01, 2007 Page 312 of 1956 REJ09B0256-0100...
Page 379: Section 10 Superhyway Bus Bridge (Sbr)
Section 10 SuperHyway Bus Bridge (SBR) Section 10 SuperHyway Bus Bridge (SBR) The SuperHyway bus bridge (SBR) performs access protocol conversion between the SuperHyway (Shwy) bus and the SuperHyway bridge bus. At the same time, it also arbitrates between the accesses to the SuperHyway bus by the three peripheral modules (SECURITY, GETHER, and USBH) connected to the SuperHyway bridge bus.
Page 380: Register Descriptions
Section 10 SuperHyway Bus Bridge (SBR) 10.2 Register Descriptions Table 10.1 shows the SBR register configuration. Table 10.2 shows the register state in each operating mode. Table 10.1 Register Configuration Area P4 Area 7 Access Register Name Abbreviation R/W Address* Address* Size Bus arbitration priority level...
Page 381: Bus Arbitration Priority Level Setting Register (Sbrivclv)
Section 10 SuperHyway Bus Bridge (SBR) 10.2.1 Bus Arbitration Priority Level Setting Register (SBRIVCLV) SBRIVCLV sets the priority levels used when SuperHyway bus access requests from the SECURITY, GETHER, and USBH coincide. Bit: — — — — — — — —...
Page 382: Superhyway Bus Priority Control Resister (Prpricr)
Section 10 SuperHyway Bus Bridge (SBR) 10.2.2 SuperHyway Bus Priority Control Resister (PRPRICR) PRPRICR controls the SuperHyway bus access priority given to the CPU and the other function modules. Bit: − − − − − − − − − − −...
Page 383: Operation
Section 10 SuperHyway Bus Bridge (SBR) 10.3 Operation 10.3.1 SuperHyway Bus Interface The SuperHyway bus bridge (SBR) performs access protocol conversion between the SuperHyway bus and the SuperHyway bridge bus. 10.3.2 Bus Arbitration The SBR performs arbitration for the access requests from the four ports of the three modules (SECURITY, GETHER, and USBH) connected to the SuperHyway bridge bus.
Page 384 Section 10 SuperHyway Bus Bridge (SBR) The priority level of access requests from SECURITY, GETHER1, GETHER0, and USBH can be set to level 2 or level 3 through the SBRIVCLV register. Note that, in the USBH module, round- robin arbitration is first performed between read and write requests, then inter-module arbitration is performed using the result.
Page 385: Section 11 Local Bus State Controller (Lbsc)
Section 11 Local Bus State Controller (LBSC) Section 11 Local Bus State Controller (LBSC) The local bus state controller (LBSC) divides the external memory space and outputs control signals corresponding to the specifications of various types of memory and bus interfaces. The LBSC enables the connection of SRAM or ROM, etc., to this LSI.
Page 386 Section 11 Local Bus State Controller (LBSC) • MPX interface  Address/data multiplexing Connectable areas: 0 to 2 and 4 to 6 Settable bus width: 32 bits • Byte control SRAM interface  SRAM interface with byte control Connectable areas: 1 and 4 Settable bus widths: 32 and 16 bits •...
Page 387: Figure 11.1 Lbsc Block Diagram
Section 11 Local Bus State Controller (LBSC) Figure 11.1 shows a block diagram of the LBSC. interface Wait CSnWCR control unit CS0 to CS2 Area CSnBCR CS4 to CS6 control CE2A, CE2B unit CE1A, CE1B A0 to A25 RD/FRAME Memory RDWR control WE3/IOWR...
Page 388: Input/Output Pins
Section 11 Local Bus State Controller (LBSC) 11.2 Input/Output Pins Table 11.1 shows the LBSC pin configuration. Table 11.1 Pin Configuration Pin Name Function Description A25 to A0 Address Bus Output Address output D31 to D0 Data Bus Data input/output Bus Cycle Start Output Signal that indicates the start of a bus cycle.
Page 389 Section 11 Local Bus State Controller (LBSC) Pin Name Function Description BREQ Bus Release Input Bus release request signal Request BACK Bus Request Output Bus release acknowledge signal Acknowledge CE2A* PCMCIA Card Output When setting PCMCIA, corresponds to PCMCIA CE2B* Select card select signal D15 to D8.
Page 390: Area Overview
Section 11 Local Bus State Controller (LBSC) 2. Can be selectable the polarity (initial state is low active). For details, see section 14, Direct Memory Access Controller (DMAC). 11.3 Area Overview 11.3.1 Space Divisions The architecture of this LSI provides a 32-bit virtual address space. The virtual address space is divided into five areas according to the upper address value.
Page 391: Figure 11.2 Correspondence Between Virtual Address Space And External Memory Space
Section 11 Local Bus State Controller (LBSC) H'0000 0000 Area 0 (CS0) H'0000 0000 Area 1 (CS1) H'0400 0000 H'0800 0000 Area 2 (CS2) P0 and P0 and U0 areas H'0C00 0000 Area 3 U0 areas H'1000 0000 Area 4 (CS4) H'1400 0000 Area 5 (CS5) H'8000 0000...
Page 392 Section 11 Local Bus State Controller (LBSC) External Specifiable Area addresses Size Connectable Memory Bus Width Access Size* H'0800 0000 to 64 Mbytes SRAM 8, 16, 32* 8/16/32 bits H'0BFF FFFF and 32 bytes Burst ROM 8, 16, 32* (DDR-SDRAM* H'0C00 0000 to 64 Mbytes (DDR-SDRAM)
Page 393: Figure 11.3 External Memory Space Allocation
Section 11 Local Bus State Controller (LBSC) Area 0: H'00000000 SRAM/burst ROM/MPX Area 0: H'04000000 SRAM/burst ROM/MPX/byte control SRAM Area 0: H'08000000 SRAM/burst ROM/MPX/DDR-SDRAM Area 0: H'0C000000 DDR-SDRAM Area 0: H'10000000 SRAM/burst ROM/MPX/byte control SRAM/ DDR-SDRAM/PCI Area 0: H'14000000 SRAM/burst ROM/MPX/PCMCIA /DDR-SDRAM The PCMCIA interface is for memory and I/O card use.
Page 394: Memory Bus Width
Section 11 Local Bus State Controller (LBSC) 11.3.2 Memory Bus Width The memory bus width of the LBSC can be set independently for each area. For area 0, a bus width of 8, 16, or 32 bits is set according to the external pin settings at a power-on reset by the PRESET pin.
Page 395: Data Alignment
Section 11 Local Bus State Controller (LBSC) 11.3.3 Data Alignment This LSI supports big endian and little endian as data alignment. Data alignment is determined by the level of the external pin (MD5) at a power-on reset. Table 11.4 Correspondence between External Pin (MD5) and Endian Data Alignment Big endian High...
Page 396: Table 11.6 Pcmcia Support Interface
Section 11 Local Bus State Controller (LBSC) Table 11.6 PCMCIA Support Interface IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name* I/O* Function Name* I/O* Function Pin of this LSI  Ground Ground Data Data Data Data Data Data Data Data...
Page 397 Section 11 Local Bus State Controller (LBSC) IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name* I/O* Function Name* I/O* Function Pin of this LSI Data Data Data Data Data Data IOIS16 IOIS16 Write protect 16-bit I/O port ...
Page 398 Section 11 Local Bus State Controller (LBSC) IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name* I/O* Function Name* I/O* Function Pin of this LSI INPACK Input acknowledge  RSRVD Reserved Attribute Attribute memory memory space space select select SPKR BVD2...
Page 399: Register Descriptions
Section 11 Local Bus State Controller (LBSC) 11.4 Register Descriptions The LBSC has 16 registers as shown in table 11.7 and 11.8. The following registers control memory interfaces, wait cycles, etc. Table 11.7 Register Configuration Area 7 Access Register Name Abbrev.
Page 400: Memory Address Map Select Register (Mmselr)
Section 11 Local Bus State Controller (LBSC) Power-On Manual Register Name Abbreviation Reset Reset Sleep Standby CS2 Bus Control Register CS2BCR H'7777 7770 H'7777 7770 Retained Retained CS4 Bus Control Register CS4BCR H'7777 7770 H'7777 7770 Retained Retained CS5 Bus Control Register CS5BCR H'7777 7770 H'7777 7770...
Page 401 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 31 to 16  All 0 Reserved Set these bits to H'A5A5 only when writing to AREASEL bits in this register. These bits are always read as 0. ...
Page 402: Bus Control Register (Bcr)
Section 11 Local Bus State Controller (LBSC) Example: ----------------------------------------------------------------------- MOV.L #H'FE600020, R0 MOV.L #MMSELR_DATA, R1 ; MMSELR_DATA=Writing value of MMSELR SYNCO (upper word=H'A5A5) MOV.L R1, @R0 ; Writing to MMSELR MOV.L @R0, R2 MOV.L @R0, R2 SYNCO ----------------------------------------------------------------------- Modify executing instruction of MMSELR should allocate non-cacheable P2 area and the address that should not be affected by address map change.
Page 403 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description ENDIAN Undefined R Endian Flag The value of the external pin (MD5) designating the endian mode is sampled at a power-on reset by the PRESET pin. This bit determines the endian mode of all spaces.
Page 404 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description OPUP Control Output Pin Pull-Up Resistor Control Specifies the pull-up resistor state (A25 to A0, BS, CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WEn, RDWR, CE2A, and CE2B) when the control output pins are high-impedance.
Page 405 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description DMABST DMAC Burst Mode Transfer Priority Setting Specifies the priority of burst mode transfers by the DMAC. When this bit is cleared to 0, the priority is as follows: bus release, DMAC, CPU.
Page 406: Csn Bus Control Register (Csnbcr)
Section 11 Local Bus State Controller (LBSC) 11.4.3 CSn Bus Control Register (CSnBCR) CSnBCR is a 32-bit readable/writable register that specifies the bus width for area n (n = 0 to 2 and 4 to 6), numbers of wait, setup, and hold cycles to be inserted, burst length, and memory types.
Page 407 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 30 to 28 IWW Idle Cycles between Write-Read/Write-Write Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed.
Page 408 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 22 to 20 IWRWS Idle Cycles between Read-Write to Same Space Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed.
Page 409 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IWRRS Idle Cycles between Read-Read to Same Space Specify the number of idle cycles to be inserted after an access to a memory connected to the space is completed.
Page 410 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 9, 8 R/W* Bus Width Specify the bus width. In CS0BCR, the external pins (MD3 and MD4) are sampled at a power-on reset. Set to 11 for the MPX interface, and set to 10 or 11 for the byte control SRAM interface.
Page 411 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description R/W* MPX Interface Setting Selects the type of MPX interface 0: SRAM/byte-control SRAM interface selected 1: MPX interface selected Note: * The MPX bit in CS0BCR is read-only. 2 to 0 TYPE Memory Type Setting...
Page 412: Csn Wait Control Register (Csnwcr)
Section 11 Local Bus State Controller (LBSC) 11.4.4 CSn Wait Control Register (CSnWCR) The CSn wait control register (CSnWCR) is a 32-bit readable/writable register that specifies the number of wait cycles to be inserted, the pitch of data access for burst memory accesses, and the number of cycles to be inserted for the address setup time to the read/write strobe assertion or for the data hold time from the write strobe negation.
Page 413 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. 26 to 24 ADH Address Hold Cycle Specify the number of cycles to be inserted to ensure the address hold time to the CSn negation.
Page 414 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. RD Hold Cycle (RD Negate–CSn Negate Delay Cycle) 18 to 16 RDH Specify the number of cycles to be inserted to ensure the RD hold time to the T2.
Page 415 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. WEn Hold Cycle (WEn Negate–CSn Negate Delay 10 to 8 Cycle) Specify the number of cycles to be inserted to ensure the WEn hold time to the T2.
Page 416 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 3 to 0 IW[3:0] 1111 Insert Wait Cycle Specify the number of wait cycles to be inserted. (Available only when the SRAM interface, byte control SRAM interface, or burst ROM interface is selected.) 0000: No cycle inserted 0001: 1 cycle inserted 0010: 2 cycles inserted...
Page 417: Csn Pcmcia Control Register (Csnpcr)
Section 11 Local Bus State Controller (LBSC) 11.4.5 CSn PCMCIA Control Register (CSnPCR) CSnPCR is a 32-bit readable/writable register that specifies the timing for the PCMCIA interface connected to area n (n = 5 and 6), the space property, and the assert/negate timing for the OE and WE signals.
Page 418 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 26 to 24 SAB Space Property B Specify the space property of PCMCIA connected to second half of area 5 or 6. 000: ATA complement mode 001: Dynamic I/O bus sizing 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory...
Page 419 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description 19 to 16 PCIW 0000 PCMCIA Insert Wait Cycle B Specify the number of wait cycles to be inserted. These bits are valid, when the access area of PCMCIA interface is second half of area 5 or 6, 0000: No cycle inserted 0001: 1 cycle inserted...
Page 420 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description OE/WE Assert Delay A 14 to 12 TEDA These bits set the delay time from address output to OE/WE assertion for the access of first half area of PCMCIA interface.
Page 421 Section 11 Local Bus State Controller (LBSC) Initial Bit Name Value Description OE/WE Negate-Address Delay A 6 to 4 TEHA These bits set the delay time from OE/WE negation to address hold for the access of first half area of PCMCIA interface.
Page 422: Operation
Section 11 Local Bus State Controller (LBSC) 11.5 Operation 11.5.1 Endian/Access Size and Data Alignment This LSI supports both big-endian mode, in which the upper byte (MSByte) in a string of byte data is at address 0, and little-endian mode, in which the lower byte (LSByte) in a string of byte data is at address 0.
Page 423: Table 11.9 32-Bit External Device/Big-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.9 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 424: Table 11.11 8-Bit External Device/Big-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.11 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 425: Table 11.12 32-Bit External Device/Little-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.12 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 426: Table 11.14 8-Bit External Device/Little-Endian Access And Data Alignment
Section 11 Local Bus State Controller (LBSC) Table 11.14 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access D31 to D23 to D15 to D7 to Size Address No.    Byte Data Assert 7 to 0 ...
Page 427: Areas
Section 11 Local Bus State Controller (LBSC) 11.5.2 Areas Area 0 For area 0, external address bits A28 to A26 are 000. The interfaces that can be set for this area are the SRAM, MPX, and burst ROM interfaces. A bus width of 8, 16, or 32 bits is selectable with external pins MD4 and MD3 at a power-on reset. For details, see section 11.3.2, Memory Bus Width.
Page 428 Section 11 Local Bus State Controller (LBSC) As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS1WCR can be selected. When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable with bits BW[2:0] in CS1BCR.
Page 429 Section 11 Local Bus State Controller (LBSC) For details, see section 12, DDR-SDRAM Interface (DDRIF). Area 4 For area 4, physical address bits A28 to A26 are 100. The interfaces that can be set for this area are the SRAM, MPX, burst ROM, byte control SRAM, DDR-SDRAM and PCI interfaces.
Page 430 Section 11 Local Bus State Controller (LBSC) While the PCMCIA interface is used, the CE1A/CS5 and CE2A signals, the RD signal, (which can be used as OE), the WE0, WE1, WE2, and WE3 signals, (which can be used as, PCC_REG, WE, IORD, and IOWR, respectively) are asserted.
Page 431: Sram Interface
Section 11 Local Bus State Controller (LBSC) Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY). (When the insert number is 0, the RDY signal is ignored.) The setup time and hold time (cycle number) of the address and CS6 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS6WCR.
Page 432: Figure 11.4 Basic Timing Of Sram Interface
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 RDWR D31 to D0 (read) D31 to D0 (Write) DACKn (DA) DA: Dual address DMA Figure 11.4 Basic Timing of SRAM Interface Rev. 1.00 Oct. 01, 2007 Page 366 of 1956 REJ09B0256-0100...
Page 433: Figure 11.5 Example Of 32-Bit Data-Width Sram Connection
Section 11 Local Bus State Controller (LBSC) Figures 11.5 to 11.7 show examples of the connection to SRAM with data width of 32, 16, and 8 bits. 128 K × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 11.5 Example of 32-Bit Data-Width SRAM Connection...
Page 434: Figure 11.6 Example Of 16-Bit Data-Width Sram Connection
Section 11 Local Bus State Controller (LBSC) 128 K × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 Figure 11.6 Example of 16-Bit Data-Width SRAM Connection 128K × 8-bit This LSI SRAM I/O7 I/O0 Figure 11.7 Example of 8-Bit Data-Width SRAM Connection Rev.
Page 435: Figure 11.8 Sram Interface Wait Timing (Software Wait Only)
Section 11 Local Bus State Controller (LBSC) Wait Cycle Control Wait cycle insertion for the SRAM interface can be controlled by CSnWCR. If the IW bits for each area in CSnWCR is not 0, a software wait is inserted in accordance with the wait-control bits. For details, see section 11.4.4, CSn Wait Control Register (CSnWCR).
Page 436: Figure 11.9 Sram Interface Wait Cycle Timing (Wait Cycle Insertion By Rdy Signal)
Section 11 Local Bus State Controller (LBSC) When software wait insertion is specified by CSnWCR, the external wait input signal (RDY) is also sampled. The RDY signal sampling timing is shown in figure 11.9, where a single wait cycle is specified as a software wait. The RDY signal is sampled at the transition from the Tw state to the T2 state.
Page 437 Section 11 Local Bus State Controller (LBSC) Read-Strobe Negate Timing When the SRAM interface is used, the negation timing of the strobe signal during a read operation can be specified through the RDH bit in CSnWCR. Rev. 1.00 Oct. 01, 2007 Page 371 of 1956 REJ09B0256-0100...
Page 438: Figure 11.10 Sram Interface Wait State Timing (Read-Strobe Negate Timing Setting)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 RDWR (read) D31 to D0 (read) : RD Setup wait : RD Hold wait CSnWCR RDS SnWCR RDH (0 to 7) (0 to 7) : Address Setup wait : Access wait : Address Hold wait CSnWCR RDS CSnWCR IW...
Page 439: Burst Rom Interface
Section 11 Local Bus State Controller (LBSC) 11.5.4 Burst ROM Interface Setting the TYPE bit in CSnBCR(n=0 to 2 and 4 to 6) to 010 allows a burst ROM to be connected to areas 0 to 2 and 4 to 6. The burst ROM interface provides high-speed access to ROM that has a burst access function.
Page 440: Figure 11.11 Burst Rom Basic Access Timing
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A5 A4 to A0 RDWR D31 to D0 (read) Figure 11.11 Burst ROM Basic Access Timing CLKOUT A25 to A5 A4 to A0 RDWR D31 to D0 (read) Figure 11.12 Burst ROM Wait Access Timing Rev.
Page 441: Pcmcia Interface
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A5 A4 to A0 RDWR D31 to D0 (read) DACK Note: * When CSnBCR RDSPL is set to 1. Figure 11.13 Burst ROM Wait Access Timing 11.5.5 PCMCIA Interface Areas 5 and 6 can be set to the IC memory card interface or I/O card interface, which is stipulated in JEIDA specification version 4.2 (PCMCIA 2.1), by setting bits TYPE[2:0] in CS5BCR and CS6BCR.
Page 442 Section 11 Local Bus State Controller (LBSC) When the first half area is accessed, bits IW[3:0] in CSnWCR (n=5 or 6) and bits PCWA[1:0], TEDA[2:0], and TEHA[2:0] in CSnPCR (n=5 or 6) are selected. When the second half area is accessed, bits IW[3:0] in CSnWCR (n=5 or 6) and bits PCWB[1:0], TEDB[2:0], and TEHB[2:0] in CSnPCR (n=5 or 6) are selected.
Page 443: Figure 11.14 Cexx And Dack Output Of Ata Complete Mode In Dma Transfer
Section 11 Local Bus State Controller (LBSC) Specify the number of wait cycles between accesses to be 0 for the DACK assertion area, when setting the size of DMA transfer is 16-byte. After the DMA burst transfer has finished, that DACKBST was enabled, set the DACKBST bit to 1 again before starting the next DMA transfer.
Page 444: Table 11.15 Relationship Between Address And Ce When Using Pcmcia Interface
Section 11 Local Bus State Controller (LBSC) Table 11.15 Relationship between Address and CE When Using PCMCIA Interface Access Read/ Size Odd/ IOIS16 Bus (Bits) Write (bits)* Even Access D15 to D8 D7 to D0 ×  Read Even Invalid Read data ×...
Page 445 Section 11 Local Bus State Controller (LBSC) Access Read/ Size Odd/ IOIS16 Bus (Bits) Write (bits)* Even Access D15 to D8 D7 to D0  Dynamic Write Even Invalid Write data Bus Sizing* First Invalid Write data Second Invalid Write data Even First Upper write data Lower write data...
Page 446: Figure 11.15 Example Of Pcmcia Interface
Section 11 Local Bus State Controller (LBSC) A25 to A0 A25∼A0 A25 to A0 D15 to D0 RDWR D7 to D0 CE1B/(CS6) D15 to D0 D15∼D0 CE1A/(CS5) CE2B CE2A D15 to D8 PC card PCカード (memory I/O) （メモリ/IO） This LSI WE/PGM IORD) IORD...
Page 447: Figure 11.16 Basic Timing For Pcmcia Memory Card Interface
Section 11 Local Bus State Controller (LBSC) Memory Card Interface Basic Timing Figure 11.16 shows the basic timing for the PCMCIA memory card interface, and figure 11.17 shows the wait timing for the PCMCIA memory card interface. pcm1 pcm2 CLKOUT A25 to A0 CExx PCC_REG...
Page 448: Figure 11.17 Wait Timing For Pcmcia Memory Card Interface
Section 11 Local Bus State Controller (LBSC) pcm0 pcm0w pcm1 pcm1w pcm1w pcm2 pcm2w CLKOUT A25 to A0 CExx PCC_REG RDWR (read) D15 to D0 (read) (Write) D15 to D0 (Write) DACK (DA) DA: Dual address DMA Figure 11.17 Wait Timing for PCMCIA Memory Card Interface Rev.
Page 449: Figure 11.18 Basic Timing For Pcmcia I/O Card Interface
Section 11 Local Bus State Controller (LBSC) I/O Card Interface Timing Figures 11.18 and 11.19 show the timing for the PCMCIA I/O card interface. When accessing a PCMCIA card via the I/O card interface, it is possible to perform dynamic sizing of the I/O bus width using the IOIS16 pin.
Page 450: Figure 11.19 Wait Timing For Pcmcia I/O Card Interface
Section 11 Local Bus State Controller (LBSC) pci0 pci0w pci1 pci1w pci1w pci2 pci2w CLKOUT A25 to A0 CExx PCC_REG (WE0) RDWR IORD (Write) D15 to D0 (Write) IOWR (Write) D15 to D0 (Write) IOIS16 DACK (DA) DA: Dual address DMA Figure 11.19 Wait Timing for PCMCIA I/O Card Interface Rev.
Page 451: Figure 11.20 Dynamic Bus Sizing Timing For Pcmcia I/O Card Interface
Section 11 Local Bus State Controller (LBSC) pci2 pci2w pci0 pci1w pci2 pci2w pci0 pci1w CLKOUT A25 to A1 CExx PCC_REG (WE0) RDWR IORD (WE2) (read) D15 to D0 (read) IOWR (WE3) (Write) D15 to D0 (Write) IOIS16 DACK (DA) DA: Dual address DMA Figure 11.20 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.
Page 452: Mpx Interface
Section 11 Local Bus State Controller (LBSC) 11.5.6 MPX Interface When both the MODE4 and MODE3 pins are set to 0 at a power-on reset by the PRESET pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1, 2, and 4 to 6 by the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR.
Page 453: Figure 11.21 Example Of 32-Bit Data Width Mpx Connection
Section 11 Local Bus State Controller (LBSC) This LSI MPX device CLKOUT FRAME RDWR D31 to D0 I/O31 to I/O0 Figure 11.21 Example of 32-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1, 2, and 4 to 6, a bus size of 32 bits should be specified by CSnBCR.
Page 454: Figure 11.23 Mpx Interface Timing 2 (Single Read, Iw = 0, One External Wait Inserted)
Section 11 Local Bus State Controller (LBSC) md1w md1w CLKOUT RD/FRAME D31 to D0 RDWR DACK (DA) DA: Dual address DMA Figure 11.23 MPX Interface Timing 2 (Single Read, IW = 0, One External Wait Inserted) Rev. 1.00 Oct. 01, 2007 Page 388 of 1956 REJ09B0256-0100...
Page 455: Figure 11.24 Mpx Interface Timing 3 (Single Write Cycle, Iw = 0, No External Wait)
Section 11 Local Bus State Controller (LBSC) CLKOUT RD/FRAME D31 to D0 RDWR DACK (DA) DA: Dual address DMA Figure 11.24 MPX Interface Timing 3 (Single Write Cycle, IW = 0, No External Wait) Rev. 1.00 Oct. 01, 2007 Page 389 of 1956 REJ09B0256-0100...
Page 456: Figure 11.25 Mpx Interface Timing
Section 11 Local Bus State Controller (LBSC) md1w md1w CLKOUT RD/FRAME D31 to D0 RDWR DACK (DA) DA: Dual address DMA Figure 11.25 MPX Interface Timing 4 (Single Write Cycle, IW = 1, One External Wait Inserted) Rev. 1.00 Oct. 01, 2007 Page 390 of 1956 REJ09B0256-0100...
Page 457: Figure 11.26 Mpx Interface Timing 5 (Burst Read Cycle, Iw = 0, No External Wait)
Section 11 Local Bus State Controller (LBSC) Figure 11.26 MPX Interface Timing 5 (Burst Read Cycle, IW = 0, No External Wait) Rev. 1.00 Oct. 01, 2007 Page 391 of 1956 REJ09B0256-0100...
Page 458: Figure 11.27 Mpx Interface Timing 6 (Burst Read Cycle, Iw = 0, External Wait Control)
Section 11 Local Bus State Controller (LBSC) Figure 11.27 MPX Interface Timing 6 (Burst Read Cycle, IW = 0, External Wait Control) Rev. 1.00 Oct. 01, 2007 Page 392 of 1956 REJ09B0256-0100...
Page 459: Figure 11.28 Mpx Interface Timing 7 (Burst Write Cycle, Iw = 0, No External Wait)
Section 11 Local Bus State Controller (LBSC) Figure 11.28 MPX Interface Timing 7 (Burst Write Cycle, IW = 0, No External Wait) Rev. 1.00 Oct. 01, 2007 Page 393 of 1956 REJ09B0256-0100...
Page 460: Figure 11.29 Mpx Interface Timing 8 (Burst Write Cycle, Iw = 1, External Wait Control)
Section 11 Local Bus State Controller (LBSC) Figure 11.29 MPX Interface Timing 8 (Burst Write Cycle, IW = 1, External Wait Control) Rev. 1.00 Oct. 01, 2007 Page 394 of 1956 REJ09B0256-0100...
Page 461: Figure 11.30 Mpx Interface Timing 9 (Burst Read Cycle, Iw = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)
Section 11 Local Bus State Controller (LBSC) Figure 11.30 MPX Interface Timing 9 (Burst Read Cycle, IW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) Rev. 1.00 Oct. 01, 2007 Page 395 of 1956 REJ09B0256-0100...
Page 462: Figure 11.31 Mpx Interface Timing 10 (Burst Read Cycle, Iw = 0, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)
Section 11 Local Bus State Controller (LBSC) Figure 11.31 MPX Interface Timing 10 (Burst Read Cycle, IW = 0, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev. 1.00 Oct. 01, 2007 Page 396 of 1956 REJ09B0256-0100...
Page 463: Figure 11.32 Mpx Interface Timing 11 (Burst Write Cycle, Iw = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)
Section 11 Local Bus State Controller (LBSC) Figure 11.32 MPX Interface Timing 11 (Burst Write Cycle, IW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) Rev. 1.00 Oct. 01, 2007 Page 397 of 1956 REJ09B0256-0100...
Page 464: Figure 11.33 Mpx Interface Timing 12 (Burst Write Cycle, Iw = 1, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)
Section 11 Local Bus State Controller (LBSC) Figure 11.33 MPX Interface Timing 12 (Burst Write Cycle, IW = 1, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev. 1.00 Oct. 01, 2007 Page 398 of 1956 REJ09B0256-0100...
Page 465: Byte Control Sram Interface
Section 11 Local Bus State Controller (LBSC) 11.5.7 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte-select strobe (WEn) in both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM having an upper byte select strobe and lower select strobe functions, such as UB and LB.
Page 466: Figure 11.35 Byte-Control Sram Basic Read Cycle (No Wait)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 RDWR D31 to D0 (read) DACKn (DA) DA: Dual address DMA Figure 11.35 Byte-Control SRAM Basic Read Cycle (No Wait) Rev. 1.00 Oct. 01, 2007 Page 400 of 1956 REJ09B0256-0100...
Page 467: Figure 11.36 Byte-Control Sram Basic Read Cycle (One Internal Wait Cycle)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 RDWR D31 to D0 (read) DACKn (DA) DA: Dual address DMA Figure 11.36 Byte-Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev. 1.00 Oct. 01, 2007 Page 401 of 1956 REJ09B0256-0100...
Page 468: Figure 11.37 Byte-Control Sram Basic Read Cycle (One Internal Wait + One External Wait)
Section 11 Local Bus State Controller (LBSC) CLKOUT A25 to A0 RDWR D31 to D0 (read) DACKn (DA) DA: Dual address DMA Figure 11.37 Byte-Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev. 1.00 Oct. 01, 2007 Page 402 of 1956 REJ09B0256-0100...
Page 469: Wait Cycles Between Accesses
Section 11 Local Bus State Controller (LBSC) 11.5.8 Wait Cycles between Accesses A problem associated with higher operating frequencies for external memory buses is that the data buffer turn-off after completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and resulting in lower reliability or malfunctions.
Page 470: Figure 11.38 Wait Cycles Between Access Cycles
Section 11 Local Bus State Controller (LBSC) wait wait CLKOUT A25 to A0 RDWR D31 to D0 Area m space read Area n space read Area n space Write Area m inter-access wait specificaton Area n inter-access wait specification Figure 11.38 Wait Cycles between Access Cycles Rev.
Page 471: Bus Arbitration
Section 11 Local Bus State Controller (LBSC) 11.5.9 Bus Arbitration This LSI is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. This bus arbitration supports master mode. In master mode the bus is held on a constant basis, and is released to another device in response to a bus request.
Page 472: Figure 11.39 Arbitration Sequence
Section 11 Local Bus State Controller (LBSC) CLKOUT BREQ Asserted for Negated least 2 cycles within 2 cycles BACK A25 to A0 RDWR D31 to D0 (Write) Master access Slave access Master access (a) Master mode device access CLKOUT Must be asserted for Must be negated at least 2 cycles within 2 cycles...
Page 473: 11.5.10 Master Mode
Section 11 Local Bus State Controller (LBSC) 11.5.10 Master Mode The master mode processor holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends.
Page 474: 11.5.11 Cooperation Between Master And Slave
Section 11 Local Bus State Controller (LBSC) 11.5.11 Cooperation between Master and Slave To enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. When designing an application system that includes this LSI, all control, including initialization, and low power consumption control, are supposed to be carried out by this LSI.
Page 475: Section 12 Ddr-Sdram Interface (Ddrif)
Section 12 DDR-SDRAM Interface (DDRIF) Section 12 DDR-SDRAM Interface (DDRIF) The memory controller is a module that arbitrates accesses from the CPU and modules and outputs control signals for the DDR-SDRAM. This module allows direct connection with the DDR- SDRAM. This module is provided with two interface modules (SHIF: SuperHyway bus interface and LCDIF: LCD interface) and one DDR-SDRAM controller (DDRC), and an arbiter (ARBT) that arbitrates accesses from interface modules to the DDRC.
Page 476: Figure 12.1 Ddrif Block Diagram
Section 12 DDR-SDRAM Interface (DDRIF) Figure 12.1 shows a block diagram of the DDRIF. M_CLK0 From CPG M_CLK1 M_BKPRST DDRIF M_CKE M_CS M_RAS LCDC LCDC DDR-SDRAM interface M_CAS Arbiter controller (LCDIF) (ARBT) M_WE (DDRC) M_BA1, M_BA0 M_A13 to M_A 0 M_DQM3 to M_DQM0 SuperHyway bus...
Page 477: Input/Output Pins
Section 12 DDR-SDRAM Interface (DDRIF) 12.2 Input/Output Pins Table 12.1 shows the DDRIF pin configuration. For details on connection with the DDR-SDRAM, see the LSI pin information section. Note that clock-related signals will be determined later. Table 12.1 Pin Configuration Pin Name Function Description...
Page 478: Data Conversion
Section 12 DDR-SDRAM Interface (DDRIF) 12.3 Data Conversion 12.3.1 Data Alignment Data Alignment in DDR-SDRAM: The DDRIF supports both big endian mode where an address of the upper byte is 0 and little endian mode where an address of the lower byte is 0. These modes can be switched by using external pins at a power-on reset.
Page 479: Table 12.3 Access And Data Alignment In Big Endian Mode (External Bus Width Is 32 Bits)
Section 12 DDR-SDRAM Interface (DDRIF) Table 12.3 Access and Data Alignment in Big Endian Mode (External Bus Width is 32 Bits) M_D31 to M_D24 M_D23 to M_D16 M_D15 to M_D8 M_D7 to M_D0 Byte access at address 0 Data 7 to 0 Byte access at address 1 Data 7 to 0 Byte access at address 2...
Page 480: Data Alignment In Peripheral Modules
Section 12 DDR-SDRAM Interface (DDRIF) 12.3.2 Data Alignment in Peripheral Modules The endian mode in the DDRIF matches that in the CPU, and both big endian and little endian are available. Bit 31 Bit 0 Example of memory address A[3:0] = (0000) DDR-SDRAM (Address A + 0) Other than the above, the DDRC wraps around the data...
Page 481: Register Descriptions
Section 12 DDR-SDRAM Interface (DDRIF) 12.4 Register Descriptions Table 12.4 shows the DDRIF registers. These registers should be set when access is not made to the DDR-SDRAM from peripheral modules. When the access is not made and the DCE bit (DDR-SDRAM control enable) in the memory interface mode register is cleared to 0 or the SELFS bit (self-refresh status) in that register is set to 1, set other registers.
Page 482: Table 12.5 Register State In Each Operating Mode
Section 12 DDR-SDRAM Interface (DDRIF) Table 12.5 Register State in Each Operating Mode Power-On Manual Register Name Abbreviation Reset Reset Sleep Standby Memory interface mode H'0000 0000 H'0000 0000 Retained Retained register 0C34 xx00* 0C34 xx00* DDR-SDRAM control register H'0000 0000 H'0000 0000 Retained Retained...
Page 483: Memory Interface Mode Register (Mim)
Section 12 DDR-SDRAM Interface (DDRIF) 12.4.1 Memory Interface Mode Register (MIM) Bit: Initial value: R/W: Bit: BOMODE MODE Initial value: R/W: Bit: DRI[12:0] Initial value: R/W: Bit: LOCK DLLEN Initial value: R/W: Note: * Depends on the setting of external pins (MD5). Initial Bit Name Value...
Page 484 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. PCKE Power Down When the DDR-SDRAM is not accessed (in the idle state or bank active state), this bit sets the CKE pin low and the power-down mode is entered.
Page 485 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 28 to 16 DRI H'0C34 DRAM Refresh Interval When refreshing is valid (the DRE bit in MIM is set to 1), these bits specify the maximum refresh interval (auto refresh). One count is the same as the cycle of the memory clock.
Page 486 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description ENDIAN Undefined R Endian Identification Indicates whether the big endian mode or little endian mode is set to the external data bus. 1: Big endian mode 0: Little endian mode ...
Page 487: Ddr-Sdram Control Register (Scr)
Section 12 DDR-SDRAM Interface (DDRIF) 12.4.2 DDR-SDRAM Control Register (SCR) Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Rev. 1.00 Oct. 01, 2007 Page 421 of 1956 REJ09B0256-0100...
Page 488 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description  63 to 3 All 0 Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 SDRAM Mode Select These bits initialize the DDR-SDRAM at a power-on or after release of a reset.
Page 489: Ddr-Sdram Timing Register (Str)
Section 12 DDR-SDRAM Interface (DDRIF) 12.4.3 DDR-SDRAM Timing Register (STR) STR specifies the DDR-SDRAM timing. (Details on the number range depend on the parameters used by each memory manufacturer. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: SRFC...
Page 490 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 17, 16 Minimum Number of Cycles from Read command to Write Commands These bits specify the minimum number of cycles for the WRITE command issuance after the READ command is issued for the DDR-SDRAM. 00: 3 cycles 01: 4 cycles 10: 5 cycles...
Page 491 Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 10 to 8 SRAS Minimum Number of Cycles between ACT and PRE Commands These bits specify the minimum number of cycles from ACT command issuance to PRE command issuance in the same bank (Tras).
Page 492: Ddr-Sdram Row Attribute Register (Sdr)
Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description SRCD Number of Cycles between RAS and CAS Commands Specifies the number of cycles from RAS (ACT) command issuance to CAS (READ/READA, WRITE/WRITEA) command issuance (Trcd). 0: 3 cycles 1: 4 cycles Number of Cycles between PRE and ACT Commands Specifies the number of cycles from PRE command issuance to ACT command issuance (Trp).
Page 493: Ddr-Sdram Mode Register (Sdmr)
Section 12 DDR-SDRAM Interface (DDRIF) Initial Bit Name Value Description 63 to 12  All 0 Reserved These bits are always read as 0. The write value should always be 0. 11 to 8 SPLIT 0001 DDR-SDRAM Memory Configuration These bits specify the DDR-SDRAM row/column configuration.
Page 494: Figure 12.3 Relationship Between Write Values In Sdmr And Output Signals To Memory Pins
Section 12 DDR-SDRAM Interface (DDRIF) Figure 12.3 shows the relationship between write values in SDMR and output signals to the memory pins. SDRAM address DDR-SDRAM MA10 MA11 MA12 MA13 M_CS M_RAS M_CAS L: Low level M_WE H: High level Figure 12.3 Relationship between Write Values in SDMR and Output Signals to Memory Pins For example, when the DLL reset release, CAS latency of 2.5 cycles, sequential burst sequence, and burst length of 2 are set to the mode register in the DDR-SDRAM, the following signals must...
Page 495: Ddr-Sdram Back-Up Register (Dbk)
Section 12 DDR-SDRAM Interface (DDRIF) 12.4.6 DDR-SDRAM Back-up Register (DBK) This register indicates the DDR-SDRAM back-up status. For details, see section 18, Power-Down Mode. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: SDBUP Initial value: R/W: Initial Bit Name...
Page 496: Operation
Section 12 DDR-SDRAM Interface (DDRIF) 12.5 Operation 12.5.1 DDR-SDRAM Access The DDR-SDRAM is accessed with a burst length of 2. Read or write commands that hit the page are issued continuously and read data continuously. Write command Write data read command read data Figure 12.4 DDR-SDRAM Access 12.5.2...
Page 497 Section 12 DDR-SDRAM Interface (DDRIF) 9. Use SDMR to issue the MRS command and reset the DLL. Also set the burst length, CAS latency, and so on. 10. After the PREALL command is issued, use the SMS field in SCR to issue the REF command twice.
Page 498: Supported Ddr-Sdram Commands
Section 12 DDR-SDRAM Interface (DDRIF) 12.5.3 Supported DDR-SDRAM Commands Table 12.6 shows the DDR-SDRAM commands supported by the DDRIF. Table 12.6 DDR-SDRAM Commands Issued by DDRIF MA13 MA9 to CKEn − 1 CKEn CS Function Symbol MA11 (MA10) Device deselect DESL No operation Read...
Page 499: Ddr-Sdram Access Mode
Section 12 DDR-SDRAM Interface (DDRIF) 12.5.4 DDR-SDRAM Access Mode The DDRIF supports the following two DDR-SDRAM access modes. Each mode can be set using the BOMODE bits in MIM. Bank Open Mode: The DDR-SDRAM is accessed without the PRE command immediately after memory read or memory write, meaning that the bank is always open.
Page 500: Registers That Set Ddr-Sdram Timing Restrictions
Section 12 DDR-SDRAM Interface (DDRIF) 5. Whether the DDR-SDRAM enters the self-refresh mode can be checked by reading the SELFS bit in MIM. [Recovery from self-refresh state] 1. Clear the RMODE and DRE bits in MIM to 0 to clear the self-refresh state. 2.
Page 501: Operating Frequency
Section 12 DDR-SDRAM Interface (DDRIF) 12.5.7 Operating Frequency The DDRIF is supported only when the clock ratio between the SuperHyway bus clock and the external memory clock is 1:1 (DDR266 or DDR200). The maximum operating frequency for the SuperHyway bus is 133 MHz. The minimum operating frequency depends on the DDR-SDRAM clock frequency.
Page 502: 12.5.11 Note On Setting Auto-Refresh Interval
Section 12 DDR-SDRAM Interface (DDRIF) 12.5.11 Note on Setting Auto-Refresh Interval The auto-refresh interval is specified by the DRI bits in MIM. If the DRE bit is set to 1 at the same time as the DRI bits are set, the time until the first auto-refresh is that selected by the value of the DRI bits before the new setting was made.
Page 503: 12.5.14 Coherency When Accessing Ddr-Sdram
Section 12 DDR-SDRAM Interface (DDRIF) At level 0, DDR-SDRAM controls such as DDR-SDRAM refresh and page management have the highest priority. The memory is refreshed according to the memory refresh intervals specified separately. At level 1, access is rotated between access from the SHway bus and access from the LCDC (in round-robin method).
Page 504: Ddrif Basic Timing
Section 12 DDR-SDRAM Interface (DDRIF) 12.6 DDRIF Basic Timing Figures 12.5 to 12.14 show examples of basic DDRIF timing. In every figure, the DDR-SDRAM is idle at T0. The various timings should be set in the STR register within the range specified by the DDR- SDRAM used.
Page 505: Figure 12.6 Basic Ddrif Timing (1 Burst Write: 1, 2, 4, Or 8 Bytes; Without Auto-Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command WRITE (SRCD = 1) MA9-0 Col 0 MA13-11 MA10 Bank Bank Bank BA1-0 MRAS MCAS Hi-Z MDQS Hi-Z D0 D1 MDQM Figure 12.6 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes; Without Auto- Precharge) Rev.
Page 506: Figure 12.7 Basic Ddrif Timing (1 Burst Read: 1, 2, 4, Or 8 Bytes; With Auto-Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command READA (SRC = 011) (SRCD = 1) (SRP = 0) (SRAS = 000) MA9-0 Col 0 MA13-11 MA10 BA1-0 Bank Bank Bank MRAS MCAS Hi-Z MDQS CL = 2.5 Hi-Z D0 D1 MDQM Figure 12.7 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes;...
Page 507: Figure 12.8 Basic Ddrif Timing (1 Burst Write: 1, 2, 4, Or 8 Bytes; With Auto-Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command WRITEA (SRC = 101) (SRCD = 1) (SWR = 0) (SRP = 0) (SRAS = 010) MA9-0 Col 0 MA13-11 MA10 BA1-0 Bank Bank Bank MRAS MCAS Hi-Z MDQS Hi-Z D0 D1 MDQM Figure 12.8 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes;...
Page 508: Figure 12.9 Basic Ddrif Timing (4 Burst Read: 32 Bytes; Without Auto-Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command READ READ READ READ (SRCD = 1) MA9-0 Col 0 Col 2 Col 4 Col 6 MA13-11 MA10 BA1-0 Bank Bank Bank Bank Bank Bank MRAS MCAS Hi-Z MDQS Hi-Z CL = 2.5 D0 D1 D2 D3 D4 D5 D6 D7 MDQM Figure 12.9 Basic DDRIF Timing (4 Burst Read: 32 Bytes;...
Page 509: Figure 12.10 Basic Ddrif Timing (4 Burst Write: 32 Bytes; Without Auto-Precharge)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command WRITE WRITE WRITE WRITE (SRCD = 1) MA9-0 Col 0 Col 2 Col 4 Col 6 MA13-11 MA10 Bank Bank Bank Bank Bank Bank BA1-0 MRAS MCAS Hi-Z MDQS Hi-Z D1 D2 D3 D4 D5 D6 D7 MDQM Figure 12.10 Basic DDRIF Timing (4 Burst Write: 32 Bytes;...
Page 510: Figure 12.11 Basic Ddrif Timing (Precharge All Banks (Preall) To Bank Activate (Act))
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command PREALL (SRP = 1) MA9-0 MA13-11 MA10 BA1-0 Bank MRAS MCAS Hi-Z MDQS Hi-Z MDQM Figure 12.11 Basic DDRIF Timing (Precharge all Banks (PREALL) to Bank Activate (ACT)) Rev. 1.00 Oct. 01, 2007 Page 444 of 1956 REJ09B0256-0100...
Page 511: Figure 12.12 Basic Ddrif Timing (Mode Register Set (Mrs))
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command MA9-0 MA13-11 MA10 BA1-0 MRAS MCAS Hi-Z MDQS Hi-Z MDQM Notes: 1. Sets the operating mode and other necessary parameters. 2. For mode register setting: BA1 = low, BA0 = low For extended mode register setting: BA1 = low, BA0 = high Figure 12.12 Basic DDRIF Timing (Mode Register Set (MRS)) Rev.
Page 512: Figure 12.13 Basic Ddrif Timing (Auto-Refresh (Refa) Enter/Exit To Bank Activate (Act))
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command REFA REFA = 11 to 15 cycles = 11 to 15 cycles MA9-0 MA13-11 MA10 BA1-0 Bank MRAS MCAS Auto-refresh Figure 12.13 Basic DDRIF Timing (Auto-Refresh (REFA) Enter/Exit to Bank Activate (ACT)) Rev.
Page 513: Figure 12.14 Basic Ddrif Timing (Self-Refresh Entry From Idle (Refs)/Self-Refresh Exit (Refsx) To Any Command Input)
Section 12 DDR-SDRAM Interface (DDRIF) (MCLK) MCLK Command REFS REFSX Command XSNR XSRD MA9-0 MA13-11 MA10 BA1-0 MRAS MCAS Self-refresh Notes: 1. This timing should satisfy the conditions specified by the DDR-SDRAM used when driving CKE high. 2. This timing should satisfy the conditions specified by the DDR-SDRAM used. is for a non-READ command and t is for a READ command;...
Page 514 Section 12 DDR-SDRAM Interface (DDRIF) Rev. 1.00 Oct. 01, 2007 Page 448 of 1956 REJ09B0256-0100...
Page 515: Section 13 Pci Controller (Pcic)
Section 13 PCI Controller (PCIC) Section 13 PCI Controller (PCIC) The PCI controller (PCIC) controls the PCI bus for data transfers between memory connected to an external bus and a PCI device connected to the PCI bus. The ability to connect PCI devices facilitates the design of systems using the PCI bus and enables more compact systems capable of faster data transfer.
Page 516 Section 13 PCI Controller (PCIC) • Exclusive access (target only)  Once locked, only accessible from the device that accessed the LOCK signal  The SuperHyway bus in not locked during lock transfer • Can support cache coherency between a device connected to the PCI bus and system memory (PCI target) although device performance may become suboptimal •...
Page 517: Figure 13.1 Pcic Block Diagram
Section 13 PCI Controller (PCIC) Figure 13.1 is a block diagram of the PCIC. PCIRESET PCICLK (PCI bus clock) PCI local bus PCI standard signal PCIC SuperHyway bus PCI bus Interface MODE6 Interface (PCI bus access control) Host/normal SuperHyway bus Data FIFO Target control 32-Byte ×...
Page 518: Input/Output Pins
Section 13 PCI Controller (PCIC) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the PCIC. Table 13.1 Input/Output Pins PCI standard Pin Name signal name Description AD31 to AD0 AD[31:0] PCI Address/Data Bus (TRI) Address and data buses are multiplexed. Each bus transaction consists of an address phase followed by one or more data phases.
Page 519 Section 13 PCI Controller (PCIC) PCI standard Pin Name signal name Description IDSEL IDSEL Input PCI Configuration Device Select This signal is input to the PCI device to select configuration cycles (only for normal mode). DEVSEL DEVSEL PCI Device Select (STRI) Indicates the device driving this signal has decoded its address as the target.
Page 520 Section 13 PCI Controller (PCIC) [Legend] TRI: Tri-state STRI: Sustained tri-state O/D: Open Drain Note: Clear the PCIC-related interrupt masks only after the PCIC-related pins are selected as the PCIC. Rev. 1.00 Oct. 01, 2007 Page 454 of 1956 REJ09B0256-0100...
Page 521: Register Descriptions
Section 13 PCI Controller (PCIC) 13.3 Register Descriptions Table 13.2 shows the PCIC register configuration. Table 13.3 shows the register states in each operating mode. The PCI configuration register address and its offset are used for little endian operation. Table 13.2 List of PCIC Registers PCI* Access Name...
Page 522 Section 13 PCI Controller (PCIC) PCI* Access Name Abbreviation P4 address Area 7 address Size* PCI minimum grant register PCIMINGNT H'FE04 003E H'1E04 003E PCI maximum latency register PCIMAXLAT H'FE04 003F H'1E04 003F PCI capability ID register PCICID H'FE04 0040 H'1E04 0040 PCI next item pointer register PCINIP...
Page 523 Section 13 PCI Controller (PCIC) PCI* Access Name Abbreviation P4 address Area 7 address Size* PCI memory bank register 0 PCIMBR0 — H'FE04 01E0 H'1E04 01E0 PCI memory bank mask register 0 PCIMBMR0 — H'FE04 01E4 H'1E04 01E4 PCI memory bank register 1 PCIMBR1 —...
Page 524: Table 13.3 Register States In Each Operating Mode
Section 13 PCI Controller (PCIC) Table 13.3 Register States in Each Operating Mode Power-On Manual Name Abbreviation Reset Reset Sleep Mode Standby Control register space PCIC enable control register PCIECR H'0000 0000 H'0000 0000 Retained Retained PCI configuration register space PCI vendor ID register PCIVID H'1912...
Page 525 Section 13 PCI Controller (PCIC) Power-On Manual Name Abbreviation Reset Reset Sleep Mode Standby PCI power management capability PCIPMC H'000A H'000A Retained Retained register PCI power management PCIPMCSR H'0000 H'0000 Retained Retained control/status register PCI PMCSR bridge support H'00 H'00 Retained Retained PCIPMCSR...
Page 526: Pcic Enable Control Register (Pciecr)
Section 13 PCI Controller (PCIC) Power-On Manual Name Abbreviation Reset Reset Sleep Mode Standby PCI memory bank mask register 2 PCIMBMR2 H'0000 0000 H'0000 0000 Retained Retained PCI I/O bank register PCIIOBR H'0000 0000 H'0000 0000 Retained Retained PCI I/O bank master register PCIIOBMR H'0000 0000 H'0000 0000 Retained Retained...
Page 527: Configuration Registers
PCI Vender ID PCI: R Indicates the PCI device manufacture identifier (vender ID) that is allocated by PCI-SIG. Renesas Technology’s vendor ID is H'1912. PCI Device ID Register (PCIDID) This register uniquely identifies this LSI amongst PCI devices manufactured by the vendor.
Page 528 Section 13 PCI Controller (PCIC) PCI Command Register (PCICMD) The PCI command register provides coarse control over a device's ability to generate and respond to PCI cycles. When 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses except configuration accesses.
Page 529 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/W Parity Error PCI: R/W Controls the device's response when the PCIC detects a parity error or receives a parity error. When this bit is set to 1, the PERR signal is asserted. 0: No response parity error 1: Response parity error VGAPS...
Page 530 Section 13 PCI Controller (PCIC) PCI Status Register (PCISTATUS) This status register is used to record status information for PCI bus related events. The definition of each of the bits is given in the table below. A device may not need to implement all the bits, depending on device functionality.
Page 531 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/WC Master Abort Receive Status PCI: R/WC Indicates that the PCIC has terminated a transaction with a master abort when the PCIC is a master. 0: PCIC has not terminated a transaction with a master abort 1: PCIC has terminated a transaction with a master abort...
Page 532 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description FBBC SH: R Fast Back-to-Back Status PCI: R Indicates whether or not the PCIC is capable of accepting fast back-to-back transactions when the transactions are not to the same agent if the PCIC functions as a target.
Page 533 Section 13 PCI Controller (PCIC) PCI Revision ID Register (PCIRID) This register specifies a device specific revision identifier. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 H'00 SH: R Revision ID PCI: R Indicates the PCIC revision.The initial value is H'00.RID value varies according to the logic version of the PCIC and it may be changed in the future.
Page 534 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description  6 to 4 All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R/W PCI Programmable Indicator (Secondary) PCI: R When the CFINIT bit in PCICR is 0, this bit is writable.
Page 535 Section 13 PCI Controller (PCIC) PCI Sub Class Code Register (PCISUB) This register identifies the sub class code. For details of the class code, refer to “PCI Local Bus Specification Revision 2.2 Appendix D.” Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value...
Page 536 Section 13 PCI Controller (PCIC) PCI Cacheline Size Register (PCICLS) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 H'20 SH: R Cache Line Size: Not supported PCI: R A memory target does not support a cache. SDON and SBO are ignored.
Page 537 Section 13 PCI Controller (PCIC) (11) PCI Header Type Register (PCIHDR) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description SH: R Multiple Function Enable PCI: R 0: Single function 1: Multiple (from two to eight) functions (not supported) 6 to 0 H'00...
Page 538 Section 13 PCI Controller (PCIC) (13) PCI I/O Base Address Register (PCIIBAR) This register packages the I/O space base address register of the PCI configuration register that is prescribed with PCI local bus specification. Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: IOB (upper) Initial value:...
Page 539 Section 13 PCI Controller (PCIC) (14) PCI Memory Base Address Register 0 (PCIMBAR0) This register packages the memory space base address register of the PCI configuration register that is prescribed with PCI local bus specification. Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: MBA (upper) MBA (lower)
Page 540 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 2, 1 SH: R Memory Type PCI: R Indicates the memory type of local address space 0. 00: 32-bit base address and 32-bit space 01: 32-bit base address and 1-Mbyte space (Not supported) 10: 64-bit base address (Not supported) 11: Reserved...
Page 541 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 31 to 20 MBA H'000 SH: R/W PCI Memory Space 1 Base Address (upper 12 bits) (upper) PCI: R/W Specifies the upper 12 bits of PCI memory base address that corresponds the base address of local address space 1 (SuperHyway bus address space of this LSI).
Page 542 Section 13 PCI Controller (PCIC) (16) PCI Subsystem vender ID Register (PCISVID) Refer to miscellaneous registers section of PCI local bus specification Revision 2.2. Bit: SVID Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 15 to 0 SVID H'0000 SH: R/W Subsystem Vendor ID...
Page 543 Section 13 PCI Controller (PCIC) (18) PCI Capability Pointer Register (PCICP) This register is the expansion function pointer register of the PCI configuration register that is prescribed in the PCI power management specification. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value...
Page 544 Section 13 PCI Controller (PCIC) (20) PCI Interrupt Pin Register (PCIINTPIN) Bit: INTPIN Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 INTPIN H'01 SH: R/W Interrupt Pin Select PCI: R Specifies which interrupt pin is used for connection when the PCIC outputs interrupt request.
Page 545 Section 13 PCI Controller (PCIC) (22) PCI Maximum Latency Register (PCIMAXLAT) This register is not programmable. Bit: MAXLAT Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 MAXLAT H'00 SH: R Maximum Latency PCI: R Specify the worst time from the bus request by the PCI master device to the bus acquisition (not supported).
Page 546 Section 13 PCI Controller (PCIC) (24) PCI Next Item Pointer Register (PCINIP) PCINIP gives the location of the next item in the function's capability list. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value Description 7 to 0 H'00 SH: R Next Item Pointer...
Page 547 Section 13 PCI Controller (PCIC) (25) PCI Power Management Capability Register (PCIPMC) PCIPMCS is a 16-bit register that provides information on the capabilities of the power management related functions. For details, refer to “PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface”. This register must be set during initializing the PCIC registers (PCICR.CFINIT = 0).
Page 548 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description  8 to 6 All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R PCI: R Specifies whether or not the device requires the specific initialization.
Page 549 Section 13 PCI Controller (PCIC) (26) PCI Power Management Control/Status Register (PCIPMCSR) This 16-bit register is used to manage the PCI function's power management status as well as to enable/monitor PMEs. For details, refer to “PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface”.
Page 550 Section 13 PCI Controller (PCIC) (27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE) This register supports PCI bridge specific functionality and is required for all PCI-to-PCI bridges. Bit: — — — — — — B2B3N Initial value: SH R/W: PCI R/W: Initial Bit Name Value...
Page 551 Section 13 PCI Controller (PCIC) (28) PCI Power Consumption/Radiation Register (PCIPCDD) The data register is an 8-bit register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. For details, refer to “PCI Bus Power Management Interface Specification Revision 1.1 Chapter 3 PCI Power Management Interface”.
Page 552: Local Register
Section 13 PCI Controller (PCIC) 13.3.3 Local Register PCI Control Register (PCICR) PCICR is a 32-bit register which specifies the operation of the PCIC. The register is write protected; only writes in which the upper eight bits (that is, bits 31 to 24) have the value H'A5 are performed.
Page 553 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/W Byte Swap PCI: R Specifies whether or not byte data is swapped when accessing to the PCI local bus. 0: No swap 1: Byte data is swapped For details, see section 13.4.3 (5), Endian or section 13.4.4 (6), Endian.
Page 554 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description PCIRESET Output RSTCTL SH: R/W Controls the PCIRESET output by software. This bit is PCI: R valid when the PCIC operates in host bus bridge mode. 0: Negates PCIRESET output (high level output) 1: Asserts PCIRESET output (low level output) Note: The PCIRESET is also asserted during power- on reset.
Page 555 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 31 to 29  All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. 28 to 20 LSR 0 0000 SH: R/W Size of Local Address Space 0 (9 bits) 0000...
Page 556 Section 13 PCI Controller (PCIC) PCI Local Space Register 1 (PCILSR1) Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: — — — — — — — Initial value: SH R/W: PCI R/W: Bit: — — — — —...
Page 557 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description MBARE SH: R/W PCI Memory Base Address Register 1 Enable PCI: R The local address space 1 can be accessed by setting this bit to 1. 0: PCIMBAR1 disabled 1: PCIMBAR1 enabled PCI Local Address Register 0 (PCILAR0) Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Page 558 Section 13 PCI Controller (PCIC) PCI Local Address Register 1 (PCILAR1) Refer to Section 13.4.4 (1), Accessing This LSI Address Space. Bit: — — — — Initial value: SH R/W: PCI R/W: Bit: — — — — — — — —...
Page 559 Section 13 PCI Controller (PCIC) PCI Interrupt Register (PCIIR) PCIIR records the source of an interrupt. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, the source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs.
Page 560 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 13 to 10  All 0 SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. TMTOI SH: R/WC Target Memory Read Retry Timeout Interrupt PCI: R When the PCIC functions as a target, the master did not attempt a retry within the prescribed number of...
Page 561 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description APEDI SH: R/WC Address Parity Error Detection Interrupt PCI: R Indicates an address parity error has been detected. When both the PER and SERRE bits in the PCI command register are set to 1, an address parity error is detected.
Page 562 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description Data Parity Error Interrupt for Target PERR PEDITR SH: R/WC Indicates that the PERR signal has been received PCI: R during a target read access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a target.
Page 563 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description Master Write PERR Detection Interrupt MWPDI SH: R/WC Indicates that the PERR signal has been received PCI: R during a master write access (only detected when PCICMD.PER is set to 1) when the PCIC functions as a master.
Page 564 Section 13 PCI Controller (PCIC) PCI Interrupt Mask Register (PCIIMR) This register is the mask register for PCIIR. Bit: — — — — — — — — — — — — — — — — Initial value: SH R/W: PCI R/W: Bit: DPEI DPEI...
Page 565 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SERR Detection Interrupt Mask SEDIM SH: R/W PCI: R 0: PCIIR.SEDI disabled (masked) 1: PCIIR.SEDI enabled (not masked) DPEITWM 0 SH: R/W Data Parity Error Interrupt Mask for Target Write PCI: R 0: PCIIR.DPEITW disabled (masked) 1: PCIIR.DPEITW enabled (not masked)
Page 566 Section 13 PCI Controller (PCIC) PCI Error Address Information Register (PCIAIR) This register records PCI address information when an error is detected. Bit: Initial value: — — — — — — — — — — — — — — — —...
Page 567 Section 13 PCI Controller (PCIC) PCI Error Command Information Register (PCICIR) This register records the PCI command information when an error is detected. Bit: MTEM — — — — — — — — — — — — — — Initial value: —...
Page 568 Section 13 PCI Controller (PCIC) (10) PCI Arbiter Interrupt Register (PCIAINT) In host bus bridge mode, this register records source of an interrupt. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, source is registered in corresponding bit (set to 1) in this register, however, no interrupt occurs.
Page 569 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description TBTOI SH: R/WC Target Bus Time-Out Interrupt An interrupt is detected when the TRDY or STOP PCI: R signal is not asserted within 16 clock cycles on the first data transfer. An interrupt is detected when the TRDY or STOP signal is not asserted within eight clock cycles during the data transfer subsequent to the 2nd.
Page 570 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description SH: R/WC Target-Abort Interrupt PCI: R Indicates that a transaction is terminated with a target-abort when a device other than the PCIC functions as a bus master. 0: Target-abort interrupt does not occur [Clear condition] Write 1 to this bit (write clear).
Page 571 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description WDPEI SH: R/WC Write Parity Error Interrupt The PERR assertion is detected during a data write PCI: R when a device other than the PCIC functions as a bus master. 0: Write parity error interrupt does not occur [Clear condition] Write 1 to this bit (write clear).
Page 572 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description MBIM SH: R/WC Master-Broken Interrupt Mask PCI: R 0: PCIAINT.MBI disabled (masked) 1: PCIAINT.MBI enabled (not masked) TBTOIM SH: R/WC Target Bus Time-Out Interrupt Mask PCI: R 0: PCIAINT.TBTOI disabled (masked) 1: PCIAINT.TBTOI enabled (not masked) MBTOIM SH: R/WC...
Page 573 Section 13 PCI Controller (PCIC) (12) PCI Arbiter Bus Master Information Register (PCIBMIR) In host bridge mode, this register records when the interrupt is invoked by PCIAINT. When multiple interrupts occur, only the first source is registered. When an interrupt is masked, the source is registered in corresponding bit (set to 1), however, an interrupt occurs.
Page 574 Section 13 PCI Controller (PCIC) (13) PCI PIO Address Register (PCIPAR) This register is configuration address register. Refer to Section 13.4.5 (2), Configuration Space Access. Bit: CCIE — — — — — — — Initial value: — — — — —...
Page 575 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 15 to 11 DN Undefined SH: R/W Device Number PCI:  Specify the device number for a configuration access. Device numbers ranging from 0 to 31 are represented in five bits. A single bit of bits 31 to 16 of the AD signals is driven to high level instead of the IDSEL assertion.
Page 576 Section 13 PCI Controller (PCIC) (14) PCI Power Management Interrupt Register (PCIPINT) This register controls the power management interrupt. Bit: — — — — — — — — — — — — — — — — Initial value: SH R/W: PCI R/W: —...
Page 577 Section 13 PCI Controller (PCIC) (15) PCI Power Management Interrupt Mask Register (PCIPINTM) This is the mask register for PCIPINT. Bit: — — — — — — — — — — — — — — — — Initial value: SH R/W: PCI R/W: —...
Page 578 Section 13 PCI Controller (PCIC) (16) PCI Memory Bank Register 0 (PCIMBR0) This register specifies the upper 14-bit address of the PCI memory space 0 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: PMSBA0 —...
Page 579 Section 13 PCI Controller (PCIC) (17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register specifies the size of the PCI memory space 0. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — — — — —...
Page 580 Section 13 PCI Controller (PCIC) (18) PCI Memory Bank Register 1 (PCIMBR1) This register specifies the upper 14-bit address of the PCI memory space 1 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: PMSBA1 —...
Page 581 Section 13 PCI Controller (PCIC) (19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register specifies the size of the PCI memory space 1. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — — — — MSBAM1 —...
Page 582 Section 13 PCI Controller (PCIC) (20) PCI Memory Bank Register 2 (PCIMBR2) This register specifies the upper 14-bit address of the PCI memory space 2 (address bits 31 to 18). Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: PMSBA2 —...
Page 583 Section 13 PCI Controller (PCIC) (21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register specifies the size of the PCI memory space 2. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — MSBAM2 — — Initial value: SH R/W: PCI R/W:...
Page 584 Section 13 PCI Controller (PCIC) (22) PCI I/O Bank Register (PCIIOBR) This register specifies the upper 14-bit address of the PCI I/O space (address bits 31 to 18). Refer to Section 13.4.3 (3), Accessing PCI I/O Space. Bit: PIOSBA — —...
Page 585 Section 13 PCI Controller (PCIC) (23) PCI I/O Bank Mask Register (PCIIOBMR) This register specifies the size of the PCI I/O space. Refer to Section 13.4.3 (2), Accessing PCI Memory Space. Bit: — — — — — — — — —...
Page 586 Section 13 PCI Controller (PCIC) (24) PCI Cache Snoop Control Register 0 (PCICSCR0) An external device can access local memory of this LSI via the PCIC. When an external PCI device accesses cacheable areas of this LSI, the PCIC can support cache snoop function to the on- chip caches.
Page 587 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 1, 0 SNPMD All 0 SH: R/W Snoop Mode for PCICSAR0 PCI: — Specify if PCICSAR0 is compared with address requested by an external device. Also, specify how snoop function is executed when PCICSAR0 is compared.
Page 588 Section 13 PCI Controller (PCIC) (25) PCI Cache Snoop Control Register 1 (PCICSCR1) An external device can access local memory of this LSI via the PCIC. When an external PCI device accesses cacheable areas of this LSI, the PCIC can support cache snoop function to the on- chip caches.
Page 589 Section 13 PCI Controller (PCIC) Initial Bit Name Value Description 1, 0 SNPMD All 0 SH: R/W Snoop Mode for PCICSAR1 PCI: — Specify if PCICSAR1 is compared with address requested by an external device. Also, specify how snoop function is executed when PCICSAR1 is compared.
Page 590 Section 13 PCI Controller (PCIC) (26) PCI Cache Snoop Address Register 0 (PCICSAR0) PCICSAR0 specifies the address to be compared with the PCI address requested by an external device. Refer to section 13.4.4 (7), Cache Coherency. Bit: CADR Initial value: SH R/W: PCI R/W: —...
Page 591 Section 13 PCI Controller (PCIC) (27) PCI Cache Snoop Address Register 1 (PCICSAR1) PCICSAR1 specifies the address to be compared with the PCI address requested by an external device. Refer to section 13.4.4 (7), Cache Coherency. Bit: CADR Initial value: SH R/W: PCI R/W: —...
Page 592 Section 13 PCI Controller (PCIC) (28) PCI PIO Data Register (PCIPDR) When accessed, this register will cause the generation of a configuration cycle on the PCI bus. Refer to section 13.4.5 (2), Configuration Space Access. Bit: Initial value: — — —...
Page 593: Operation
Section 13 PCI Controller (PCIC) 13.4 Operation 13.4.1 Supported PCI Commands Table 13.4 Supported Bus Commands CBE[3:0] Command Type PCI Master PCI Target  0000 Interrupt acknowledge cycle  0001 Special cycle Yes* 0010 I/O read Yes* 0011 I/O write Yes* ...
Page 594: Pcic Initialization
Section 13 PCI Controller (PCIC) 13.4.2 PCIC Initialization After a power-on reset, the PCIC enable bit (ENBL) of the PCIC enable control register (PCIECR) and the internal register initialization bit (CFINIT) of the PCI control register (PCICR) is cleared. At this point, if the PCIC is operating as the PCI bus host (host bus bridge mode), the bus privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI bus.
Page 595: Master Access
Section 13 PCI Controller (PCIC) 13.4.3 Master Access This section describes how the PCIC is accessed by software in this LSI and the restrictions on usage, such as buffering and synchronization with other devices, when the PCIC is used in both the host bus bridge and normal modes.
Page 596: Figure 13.2 Superhyway Bus To Pci Local Bus Access
Section 13 PCI Controller (PCIC) Accessing PCI Memory Space Figure 13.2 shows the method for accessing the PCI bus allocated to the PCI memory space from the SuperHyway bus. SuperHyway bus PCI local bus address space (4GB) address space (4GB) H'0000 0000 16 Mbytes H'1000 0000...
Page 597: Figure 13.3 Superhyway Bus To Pci Local Bus Address Translation (Pci Memory Space 0)
Section 13 PCI Controller (PCIC) For PCI memory space 0 accesses, bits 23 to 18 of a SuperHyway bus address are controlled by PCI memory bank mask register 0 (PCIMBMR0). Note: In the following items and figures, “SH” means the SuperHyway bus of this LSI and “PCI”...
Page 598: Figure 13.4 Superhyway Bus To Pci Local Bus Address Translation (Pci Memory Space 1)
Section 13 PCI Controller (PCIC) 26 25 18 17 26 25 18 17 SH address PCI address mask 26 25 18 17 26 25 18 17 PCIMBMR1 PCIMBR1 MSBAM1 PMSBA1 Figure 13.4 SuperHyway Bus to PCI Local Bus Address Translation (PCI Memory Space 1) For PCI memory space 2 accesses, bits 28 to 18 of a SuperHyway address are controlled by the PCI memory bank mask register 2 (PCIMBMR2).
Page 599: Figure 13.6 Superhyway Bus To Pci Local Bus Address Translation (Pci I/O)
Section 13 PCI Controller (PCIC) Accessing PCI I/O Space Access within the size of 4-byte. Burst I/O transfers are not supported. The PCI I/O address space is allocated from H'FD20 0000 to H'FE3F FFFF (2 Mbytes). Address translation from SuperHyway bus to PCI local bus The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation.
Page 600 Section 13 PCI Controller (PCIC) Accessing Internal Registers of this LSI All internal registers, that is, PCIECR, PCI configuration registers, and PCI local registers are accessible from the CPU. 4-byte, 2-byte, and byte transmission are supported. Endian The PCIC of this LSI supports both the big endian and little endian formats. Since PCI local bus is inherently little endian, the PCIC supports both byte swapping and non-byte swapping.
Page 601: Figure 13.7 Endian Conversion From Superhyway Bus To Pci Local Bus (Non-Byte Swapping: Tbs = 0)
Section 13 PCI Controller (PCIC) 1. Little Endian MSByte LSByte SH data C' D' A Buffer data C' D' A PCI Address[2] = 1 PCI Address[2] = 0 PCI data 2. Big Endian MSByte LSByte SH data C' D' Buffer data C' D' PCI Address[2] = 0 PCI Address[2] = 1...
Page 602: Figure 13.8 Endian Conversion From Superhyway Bus To Pci Local Bus (Byte Swapping: Tbs = 1)
Section 13 PCI Controller (PCIC) 1. Little Endian MSByte LSByte SH data C' D' A Buffer data C' D' A PCI Address[2] = 1 PCI Address[2] = 0 PCI data 2. Big Endian MSByte LSByte SH data D' C' B' Buffer data C' D' PCI Address[2] = 1...
Page 603: Target Access
Section 13 PCI Controller (PCIC) 13.4.4 Target Access This section describes how the PCIC of this LSI is accessed by an external PCI local bus master when the PCIC is used in both the host bus bridge and normal modes. Accessing This LSI Address Space Accesses to the address space of this LSI by an external PCI bus master are described here.
Page 604 Section 13 PCI Controller (PCIC) To access the address space of this LSI, use the PCI memory base address register (PCIMBAR0/1), PCI local space register (PCILSR0/1), and PCI local address register (PCILAR0/1). The address spaces are mapped by software. The PCIC includes two memory mapping registers.
Page 605: Figure 13.10 Pci Local Bus To Superhyway Bus Address Translation (Local Address Space 0/1)
Section 13 PCI Controller (PCIC) 2928 20 19 2928 2019 SH address PCI address compare 29 28 2019 2928 2019 PCIMBAR0/1 PCILAR0/1 MBA (upper) 2928 2019 PCILSR0/1 0 0 0 0 0 1 1 0 0 Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation (Local Address Space 0/1) When all the MBARE bits in PCILSR0/1 are 0, the PCI local bus address is sent to the SuperHyway bus without translation.
Page 606: Figure 13.11 Pci Local Bus To Superhyway Bus Address Translation (Pcic I/O Space)
Section 13 PCI Controller (PCIC) SH address H'FE04 01 PCI Address compare IOB (upper) PCIIBAR Figure 13.11 PCI Local Bus to SuperHyway Bus Address Translation (PCIC I/O Space) Accessing PCIC Registers Configuration Registers: Access the configuration registers using an offset from the PCI configuration register space base address with the configuration read or write command.
Page 607 Section 13 PCI Controller (PCIC) Exclusive Access The lock access on the PCI bus is supported. When the PCI local bus is locked, the PCIC is accessible from the device that activates the LOCK signal. SuperHyway bus resource lock does not occur. (Another on-chip module can access the PCIC during a lock transfer.) Endian This LSI supports both the big and little endian formats.
Page 608: Figure 13.12 Endian Conversion From Pci Local Bus To Superhyway Bus (Non-Byte Swapping: Tbs = 0)
Section 13 PCI Controller (PCIC) 1. Little Endian PCI data PCI Address[2] = 0 PCI Address[2] = 1 Buffer data C' D' A MSByte LSByte SH data C' D' A 2. Big Endian PCI data PCI Address[2] = 1 PCI Address[2] = 0 Buffer data C' D' MSByte...
Page 609: Figure 13.13 Endian Conversion From Pci Local Bus To Superhyway Bus (Non-Byte Swapping: Tbs = 1)
Section 13 PCI Controller (PCIC) 1. Little Endian PCI data PCI Address[2] = 0 PCI Address[2] = 1 Buffer data C' D' D MSByte LSByte SH data C' D' A 2. Big Endian PCI data PCI Address[2] = 1 PCI Address[2] = 0 Buffer data D' C' B' MSByte...
Page 610 Section 13 PCI Controller (PCIC) Cache Coherency The PCIC supports cache snoop function. When the PCIC functions as a target device, cache coherency is guaranteed for accesses from a master device connected to a PCI bus in both the host bus bridge mode and normal mode. When accessing this LSI cacheable area, set the cache snoop registers: the PCI cache snoop control registers (PCICSCR0 and PCICSCR1) and PCI cache snoop address register (PCICSAR0 and PCICSAR1).
Page 611: Figure 13.14 Cache Flush/Purge Execution Flow For Pci Local Bus To Superhyway Bus
Section 13 PCI Controller (PCIC) PCI address Cache snoop control register SuperHyway address Cache snoop address register compare No hit issue the flush/purge Issue the read/write issue the read/write Figure 13.14 Cache Flush/Purge Execution Flow for PCI local Bus to SuperHyway Bus Rev.
Page 612: Host Bus Bridge Mode
Section 13 PCI Controller (PCIC) 13.4.5 Host Bus Bridge Mode PCI Host bus bridge Mode Operation The PCIC supports a subset of the PCI Local Bus Specification Revision 2.2 and can be connected to a device with a PCI bus interface. While the PCIC is set in host bus bridge mode, or while set in normal mode, operation differs according to whether or not bus parking is performed, and whether or not the PCI bus arbiter function is enabled or not.
Page 613: Figure 13.15 Address Generation For Type 0 Configuration Access
Section 13 PCI Controller (PCIC) 31 30 24 23 16 15 11 10 Configuration Reserved address register (PCIPAR) CCIE PCI local bus Only one '1' 00000 address (AD31 to AD0) 16 15 11 10 Figure 13.15 Address Generation for Type 0 Configuration Access In configuration accesses, a PCI master abort (no device connected) will not cause an interrupt.
Page 614: Table 13.6 Interrupt Priority
Section 13 PCI Controller (PCIC) After device 1 has claimed and granted the bus, and transferred data, the priority is as follows: PCIC > device 0 > device 2 > device 3 > device 1 Then, after the PCIC has claimed and granted the bus, and transferred data, the priority is changed Device 0 >...
Page 615: Normal Mode
Section 13 PCI Controller (PCIC) The PCIC can store the error information on the PCI bus. If an error occurs, the error address is stored in the PCI error address information register (PCIAIR), the types of transfer and command information are stored in the PCI error command information register. And then if the PCIC operates host bus bridge mode, the bus master information is stored in the PCI error bus master information register.
Page 616: Pci Local Bus Basic Interface
Section 13 PCI Controller (PCIC) (normal) (clock stop) (bus idle) (power down) Figure 13.16 PCI Local Bus Power Down State Transition The PCIC detects when the power state (PS) bit of the PCI power management control/status register changes (when it is written to from an external PCI device), and issues a power management interrupt.
Page 617: Figure 13.17 Master Write Cycle In Host Bus Bridge Mode (Single)
Section 13 PCI Controller (PCIC) Master Read/Write Cycle Timing Figures13.17 is an example of a single-write cycle in host bus bridge mode. Figure 13.18 is an example of a single read cycle in host bus bridge mode. Figure 13.19 is an example of a burst write cycle in normal mode.
Page 618: Figure 13.18 Master Read Cycle In Host Bus Bridge Mode (Single)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.18 Master Read Cycle in Host Bus Bridge Mode (Single) Rev.
Page 619: Figure 13.19 Master Write Cycle In Normal Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.19 Master Write Cycle in Normal Mode (Burst) Rev.
Page 620: Figure 13.20 Master Read Cycle In Normal Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.20 Master Read Cycle in Normal Mode (Burst) Rev.
Page 621 Section 13 PCI Controller (PCIC) Target Read/Write Cycle Timing The PCIC responds to target memory burst read accesses from an external master by retries until 8 longword (32-bit) data are prepared in the PCIC's internal FIFO. That is, it always responds to the first target burst read with a retry.
Page 622: Figure 13.21 Target Read Cycle In Normal Mode (Single)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL At configuration access REQOUT GNTIN [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.21 Target Read Cycle in Normal Mode (Single) Rev.
Page 623: Figure 13.22 Target Write Cycle In Normal Mode (Single)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL At configuration access REQOUT GNTIN [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.22 Target Write Cycle in Normal Mode (Single) Rev.
Page 624: Figure 13.23 Target Memory Read Cycle In Host Bus Bridge Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.23 Target Memory Read Cycle in Host Bus Bridge Mode (Burst) Rev.
Page 625: Figure 13.24 Target Memory Write Cycle In Host Bus Bridge Mode (Burst)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY STOP Disconnect LOCK Locked IDSEL [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.24 Target Memory Write Cycle in Host Bus Bridge Mode (Burst) Rev.
Page 626: Figure 13.25 Master Write Cycle In Host Bus Bridge Mode (Burst, With Stepping)
Section 13 PCI Controller (PCIC) Address/Data Stepping Timing By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the PCIC drives the AD bus over 2 clocks. This function can be used when there is a heavy load on the PCI bus and the AD bus does not achieve the stipulated logic level in one clock.
Page 627: Figure 13.26 Target Memory Read Cycle In Host Bus Bridge Mode (Burst, With Stepping)
Section 13 PCI Controller (PCIC) PCICLK AD[31:0] Addr DPn-1 CBE[3:0] (C/BE[3:0]) PCIFRAME IRDY DEVSEL TRDY [Legend] Addr: PCI space address nth data Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.26 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with stepping) Rev.
Page 628: Usage Notes
Section 13 PCI Controller (PCIC) 13.5 Usage Notes 13.5.1 Notes on PCIC Target Reading When the PCIC is used in target mode and all the three conditions below are satisfied, data may be lost during a PCIC target read. 1. PFCS bit in PCICR = 1 (32-byte pre-fetch enabled) 2.
Page 629 Section 13 PCI Controller (PCIC) To prevent a device that does not execute REQ negation and FRAME assertion simultaneously (figure 13.27) from being a bus master, preventive measure 1 or 2 below should be taken. 1. Use pseudo-round-robin mode. Pseudo-round-robin mode should be set (BMAM bit in PCICR = 1) as the PCI bus arbitration scheme.
Page 630 Section 13 PCI Controller (PCIC) Rev. 1.00 Oct. 01, 2007 Page 564 of 1956 REJ09B0256-0100...
Page 631: Section 14 Direct Memory Access Controller (Dmac)
Section 14 Direct Memory Access Controller (DMAC) Section 14 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules.
Page 632: Figure 14.1 Block Diagram Of Dmac
Section 14 Direct Memory Access Controller (DMAC) • Active levels for both the DMA transfer request acceptance signal (DACKn) and DMA transfer end signal (TENDn) can be set. (n = 0 to 3) Figure 14.1 shows the block diagram of the DMAC. DMAC channels 0 to 5 SARm On-chip memory...
Page 633: Input/Output Pins
Section 14 Direct Memory Access Controller (DMAC) 14.2 Input/Output Pins The external pins for the DMAC are described below. Table 14.1 lists the configuration of the pins that are connected to external device. The DMAC has pins for four channels (channel 0 to 3) for external bus use.
Page 634 Section 14 Direct Memory Access Controller (DMAC) Channel Pin Name Function Description DREQ2* DMA transfer request Input DMA transfer request input from external device to channel 2 DACK2* DMA transfer request Output Strobe output from channel 2 to acknowledge external device which has output, regarding DMA transfer request TEND2* DMA transfer end...
Page 635: Register Descriptions
Section 14 Direct Memory Access Controller (DMAC) 14.3 Register Descriptions Table 14.2 shows the configuration of registers of the DMAC. Table 14.3 shows the state of registers in each processing mode. Table 14.2 Register Configuration of DMAC Channel Name Abbrev. P4 Address Area 7 Address Access Size*...
Page 636 Section 14 Direct Memory Access Controller (DMAC) Channel Name Abbrev. P4 Address Area 7 Address Access Size* DMA source address register B0 SARB0 H'FF60 8120 H'1F60 8120 DMA destination address register B0 DARB0 H'FF60 8124 H'1F60 8124 DMA transfer count register B0 TCRB0 H'FF60 8128 H'1F60 8128...
Page 637: Table 14.3 State Of Registers In Each Operating Mode
Section 14 Direct Memory Access Controller (DMAC) Table 14.3 State of Registers in Each Operating Mode Channel Abbreviation Power-on Reset Manual Reset Sleep Stand by SAR0 Undefined Undefined Retained Retained DAR0 Undefined Undefined Retained Retained TCR0 Undefined Undefined Retained Retained CHCR0 H'4000 0000 H'4000 0000...
Page 638: Dma Source Address Registers (Sar0 To Sar5)
Section 14 Direct Memory Access Controller (DMAC) Channel Abbreviation Power-on Reset Manual Reset Sleep Stand by SARB1 Undefined Undefined Retained Retained DARB1 Undefined Undefined Retained Retained TCRB1 Undefined Undefined Retained Retained SARB2 Undefined Undefined Retained Retained DARB2 Undefined Undefined Retained Retained TCRB2 Undefined...
Page 639: Dma Source Address Registers (Sarb0 To Sarb3)
Section 14 Direct Memory Access Controller (DMAC) 14.3.2 DMA Source Address Registers (SARB0 to SARB3) SARB is 32-bit readable/writable registers that specify the source address of a DMA transfer that is set in SAR again in repeat/reload mode. Data to be written from the CPU to SAR is also written to SARB.
Page 640: Dma Destination Address Registers (Darb0 To Darb3)
Section 14 Direct Memory Access Controller (DMAC) 14.3.4 DMA Destination Address Registers (DARB0 to DARB3) DARB is 32-bit readable/writable registers that specify the destination address of a DMA transfer that is set in DAR again in repeat/reload mode. Data to be written from the CPU to DAR is also written to DARB.
Page 641: Dma Transfer Count Registers (Tcrb0 To Tcrb3)
Section 14 Direct Memory Access Controller (DMAC) 14.3.6 DMA Transfer Count Registers (TCRB0 to TCRB3) TCRB is 32-bit readable/writable registers. Data to be written from the CPU to TCR is also written to TCRB. While the HE function is used, TCRB are used as the initial value hold registers to detect HE.
Page 642: Dma Channel Control Registers (Chcr0 To Chcr5)
Section 14 Direct Memory Access Controller (DMAC) 14.3.7 DMA Channel Control Registers (CHCR0 to CHCR5) CHCR is 32-bit readable/writable registers that control the DMA transfer mode. Bit: LCKN RPT[2:0] DVMD TS[2] Initial value: R/W: R/W R/(W)* R/W Bit: DM[1:0] SM[1:0] RS[3:0] TS[1:0] Initial value:...
Page 643 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions 27 to 25 RPT[2:0] DMA Setting Renewal Specify These bits are enabled in CHCR0 to CHCR3. 000: Normal mode 001: Repeat mode SAR/DAR/TCR used as repeat area 010: Repeat mode DAR/TCR used as repeat area 011: Repeat mode SAR/TCR used as repeat mode...
Page 644 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions DMA Transfer Size Specify With TS1 and TS0, this bit specifies the DMA transfer size. When the transfer source or transfer destination is a register of an on-chip peripheral module with a transfer size set, a proper transfer size for the register should be set.
Page 645 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions R/(W)* Half End Flag After HIE (bit 18) is set to 1 and the number of transfers become half of TCR (1 bit shift to right) which is set before transfer starts, HE becomes 1.
Page 646 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions Acknowledge Mode Selects whether DACK is output in data read cycle or in data write cycle. This bit is valid only in CHCR0 to CHCR3. 0: DACK output in read cycle 1: DACK output in write cycle Acknowledge Level Specifies whether the DACK signal output is high active...
Page 647 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions 13, 12 SM[1:0] Source Address Mode Specify whether the DMA source address is incremented, decremented, or left fixed. 00: Fixed source address 01: Source address is incremented +1 in byte units transfer +2 in word units transfer +4 in longword units transfer +16 in 16-byte units transfer...
Page 648 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions DREQ Level and DREQ Edge Select Specify the detecting method of the DREQ pin input and the detecting level. These bits are valid only in CHCR0 to CHCR3. In channels 0 to 3, also, if the transfer request source is specified as an on-chip peripheral module or if an auto- request is specified, these bits are invalid.
Page 649 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions R/(W)* Transfer End Flag Shows that DMA transfer ends. The TE bit is set to 1 when data transfer ends when TCR becomes to 0. The TE bit is not set to 1 in the following cases. •...
Page 650: Dma Operation Register (Dmaor)
Section 14 Direct Memory Access Controller (DMAC) 14.3.8 DMA Operation Register (DMAOR) DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. DMAOR is a common register for channel 0 to 5.
Page 651 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions 9, 8 PR[1:0] Priority Mode 1, 0 Select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 01: CH0 >...
Page 652 Section 14 Direct Memory Access Controller (DMAC) Initial Bit Name Value Descriptions NMIF R/(W)* NMI Flag Indicates that an NMI interrupt occurred. If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. When the NMI is input, the DMA transfer in progress can be done in at least one transfer unit.
Page 653: Dma Extended Resource Selectors (Dmars0 To Dmars2)
Section 14 Direct Memory Access Controller (DMAC) 14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2) DMARS is 16-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3, and DMARS2 specifies for channels 4 and 5.
Page 654 Section 14 Direct Memory Access Controller (DMAC) • DMARS1 Bit: C3MID[5:0] C3RID[1:0] C2MID[5:0] C2RID[1:0] Initial value: R/W: Initial Bit Name Value Descriptions 15 to 10 C3MID[5:0] 000000 Transfer request module ID for DMA channel 3 (MID) See table 14.4. 9, 8 C3RID[1:0] 00 Transfer request register ID0 for DMA channel 3 (RID) See table 14.4.
Page 655: Table 14.4 Transfer Request Sources
Section 14 Direct Memory Access Controller (DMAC) Table 14.4 Transfer Request Sources Peripheral Setting Value for One Function Module Channel (MID and RID)  CMT channel 0 H'03 B'0000 00 B'11  CMT channel 1 H'07 B'0000 01 B'11  CMT channel 2 H'0B B'0000 10...
Page 656 Section 14 Direct Memory Access Controller (DMAC) Peripheral Setting Value for One Function Module Channel (MID and RID) SIOF0 H'B1 B'1011 00 B'01 Transmit H'B2 B'1011 00 B'10 Receive SIOF1 H'B5 B'1011 01 B'01 Transmit H'B6 B'1011 01 B'10 Receive SIOF2 H'C1 B'1100 00...
Page 657: Operation
Section 14 Direct Memory Access Controller (DMAC) 14.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request.
Page 658: Table 14.6 Selecting External Request Detection With Dl, Ds Bits
Section 14 Direct Memory Access Controller (DMAC) Table 14.6 Selecting External Request Detection with DL, DS Bits CHCRn (n=0 to 3) Detection of External Request Low level detection (initial value; DREQ) Falling edge detection High level detection Rising edge detection When DREQ is accepted, the DREQ pin becomes request accept disabled state.
Page 659: Table 14.8 Selecting On-Chip Peripheral Module Request Modes With Bits Rs[3:0]
Section 14 Direct Memory Access Controller (DMAC) When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive data register.
Page 660 Section 14 Direct Memory Access Controller (DMAC) DMA Transfer CHCR DMARS Request DMA Transfer RS[3:0] Source Request Signal Source Destination Mode SSI1 Transmit mode : DMRQ = 1 Cycle 1000 011101 SSITDR transmitter (Transmit data empty steal request) SSI1 Receive mode : DMRQ = 1 SSIRDR Cycle receiver...
Page 661: Channel Priority
Section 14 Direct Memory Access Controller (DMAC) 14.4.2 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it transfers data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are selected by the bits PR[1:0] in DMAOR. Fixed Mode In this mode, the priority levels among the channels remain fixed.
Page 662: Figure 14.2 Round-Robin Mode
Section 14 Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Channel 0 becomes bottom priority Priority order CH1 > CH2 > CH3 > CH4 > CH5 > CH0 after transfer (2) When channel 1 transfers Channel 1 becomes bottom...
Page 663: Figure 14.3 Changes In Channel Priority In Round-Robin Mode
Section 14 Direct Memory Access Controller (DMAC) Figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1.
Page 664: Dma Transfer Types
Section 14 Direct Memory Access Controller (DMAC) 14.4.3 DMA Transfer Types DMA transfer type is dual address mode transfer. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. Dual Address Modes In dual address mode, both the transfer source and destination are accessed by an address. The source and destination can be located externally or internally.
Page 665: Figure 14.5 Example Of Dma Transfer Timing In Dual Address Mode (Source: Ordinary Memory, Destination: Ordinary Memory)
Section 14 Direct Memory Access Controller (DMAC) Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. CHCR can specify whether the DACK is output in read cycle or write cycle. Figure 14.5 shows an example of DMA transfer timing in dual address mode.
Page 666: Figure 14.6 Dma Transfer Timing Example In Cycle-Steal Normal Mode 1
Section 14 Direct Memory Access Controller (DMAC) Bus Modes There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB and LCKN bits in CHCR. And cycle steal mode has normal and intermittent modes that are specified by the CMS bits in DMAOR.
Page 667: Figure 14.7 Dma Transfer Timing Example In Cycle-Steal Normal Mode 2
Section 14 Direct Memory Access Controller (DMAC) DREQ Busmastership retured to CPU once SuperHyway DMAC DMAC DMAC DMAC bus cycle Read Write Read Write Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2 (DREQ Low Level Detection)  Intermittent mode 16 (DMAOR.CMS = 10, CHCR.LCKN = 0 or 1, CHCR.TB = 0), intermittent mode 64 (DMAOR.CMS = 11, CHCR.LCKN = 0 or 1, CHCR.TB = 0) In intermittent mode of cycle steal, the DMAC returns the SuperHyway bus mastership to other bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte...
Page 668: Figure 14.9 Dma Transfer Timing Example In Burst Mode (Dreq Low Level Detection)
Section 14 Direct Memory Access Controller (DMAC) • Burst Mode (LCKN = 0, TB = 1) In burst mode, once the DMAC obtains the SuperHyway bus mastership, the transfer is performed continuously without releasing the bus mastership until the transfer end condition is satisfied.
Page 669: Table 14.9 Dma Transfer Matrix In Auto-Request Mode (All Channels)
Section 14 Direct Memory Access Controller (DMAC) Table 14.9 DMA Transfer Matrix in Auto-Request Mode (all channels) Transfer Destination On-chip peripheral Transfer Source LBSC space DDRIF space PCIC space module* L RAM LBSC space DDRIF space PCIC space On-chip peripheral module* L RAM [Legend]...
Page 670: Table 14.10 Dma Transfer Matrix In External Request Mode (Only Channels 0 To 3)
Section 14 Direct Memory Access Controller (DMAC) Table 14.10 DMA Transfer Matrix in External Request Mode (only channels 0 to 3) Transfer Destination On-chip peripheral Transfer Source LBSC space DDRIF space PCIC space module* L RAM LBSC space Yes* Yes* DDRIF space Yes* Yes*...
Page 671: Table 14.11 Dma Transfer Matrix In On-Chip Peripheral Module Request Mode
Section 14 Direct Memory Access Controller (DMAC) Table 14.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode Transfer Destination On-chip peripheral Transfer Source LBSC space DDRIF space PCIC space module* L RAM LBSC space DDRIF space PCIC space On-chip peripheral module* L RAM [Legend]...
Page 672: Dma Transfer Flow
Section 14 Direct Memory Access Controller (DMAC) DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1 DMA CH0 and CH1 DMA CH1 DMA CH1 Burst mode Burst mode Burst mode CH0 transfer source CH1 transfer source Priority: CH0 >...
Page 673: Figure 14.11 Dma Transfer Flowchart
Section 14 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR, SARB, DARB, TCRB, DMARS) DE, DME = 1 and TE, AE, NMIF = 0? Transfer request occurs? Bus mode, DREQ detection system, transfer request mode Transfer (1 transfer unit);...
Page 674: Repeat Mode Transfer
Section 14 Direct Memory Access Controller (DMAC) 14.4.5 Repeat Mode Transfer In a repeat mode transfer, a DMA transfer is repeated without specifying the transfer settings every time before executing a transfer. Using a repeat mode transfer with the half end function allows a double buffer transfer executed virtually.
Page 675: Reload Mode Transfer
Section 14 Direct Memory Access Controller (DMAC) 5. Hereafter, steps 2 and 4 are repeated until the DME or DE bit is cleared to 0, or an NMI interrupt is generated. Note that if the HE bit is not cleared in the procedure 3 or if the TE bit is not cleared in the procedure 4, then the transfer is stopped according to the condition of both the HE and the TE bits are set to 1.
Page 676: Dreq Pin Sampling Timing
Section 14 Direct Memory Access Controller (DMAC) 14.4.7 DREQ Pin Sampling Timing Figures 14.13 to 14.16 show the sample timing of the DREQ input in each bus mode, respectively. CKOUT DMAC Bus cycle DREQ (Rising edge) 1st acceptance 2nd acceptance DRAK (Low-active) DACK...
Page 677: Figure 14.15 Example Of Dreq Input Detection In Burst Mode Edge Detection
Section 14 Direct Memory Access Controller (DMAC) CLKOUT Bus cycle DMAC DMAC Burst acceptance DREQ (Rising edge) DRAK (Low-active) DACK (Low-active) : Non-sensitive period Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection CLKOUT Bus cycle DMAC DREQ (Overrun 0, Low-level)
Page 678: Figure 14.17 Dma Transfer End Signal (Cycle Steal Mode Level Detection)
Section 14 Direct Memory Access Controller (DMAC) Figure 14.17 shows the timing of the TEND output. CLKOUT Last DMA transfer Bus cycle DMAC DMAC DREQ DACK (Active-high) TEND (Active-high) Figure 14.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection) Note that the DACK output and TEND output are divided to align the data when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units.
Page 679: Figure 14.18 Example Of Bsc Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access To 16-Bit Device)
Section 14 Direct Memory Access Controller (DMAC) CLKOUT Address Data DACKn (Active-low) TENDn (Active-low) WAIT Note: TEND is asserted during the last transfer unit of the DMA transfer. When the transfer unit is divided into several bus cycles and CS is negated between bus cycles, TEND is also divided.
Page 680: Usage Notes
Section 14 Direct Memory Access Controller (DMAC) 14.5 Usage Notes Pay attentions to the following notes when the DMAC is used. 14.5.1 Module Stop While DMAC is in operation, modules should not be stopped by setting MSTPCR (transition to the module standby state). When modules are stopped, transfer contents cannot be guaranteed. 14.5.2 Address Error When a DMA address error is occurred, after execute the following procedure, and then start a...
Page 681: Dack And Tend Output Divisions
Section 14 Direct Memory Access Controller (DMAC) 14.5.4 DACK and TEND Output Divisions The DACK and TEND output are divided to align the data unit like the CSn output when a DMA transfer unit is divided with multiple bus cycles, for example when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units, and the CSn output is negated between these bus cycles.
Page 682 Section 14 Direct Memory Access Controller (DMAC) The transfer destination is the LBSC space and the DACK and TEND are output during the write cycle: Set B'001 to B'111 (i.e., other than 000) to the IWW bits in CSnBCR Note: * The transfer source is the LBSC space and the DACK is output during the read cycle or the transfer destination is the LBSC space and the DACK is output during the write cycle.
Page 683: Table 14.12 Register Setting For Sram, Burst Rom, Byte Control Sram Interface
Section 14 Direct Memory Access Controller (DMAC) Table 14.12 Register Setting for SRAM, Burst ROM, Byte Control SRAM Interface. Register Setting of CSn is not negated Bus Width DMA Transfer Bus Cycle CSnBCR.IWRRD, [bit] Access Size Number IWRRS or IWW CSnWCR.ADS and ADH Byte Word...
Page 684: Table 14.13 Register Setting For Pcmcia Interface
Section 14 Direct Memory Access Controller (DMAC) Table 14.13 Register Setting for PCMCIA Interface Bus Width DMA Transfer Bus Cycle Register Setting of CSn is not negated [bit] Access Size Number CSnWCR.ADS and ADH Byte Word Longword 16-Byte B'000 32-Byte Byte Word Longword...
Page 685: Dma Transfer To Dmac Prohibited
Section 14 Direct Memory Access Controller (DMAC) 14.5.7 DMA Transfer to DMAC Prohibited Do not perform DMA transfer with the DMAC register specified as the transfer source or transfer destination. 14.5.8 NMI Interrupt When an NMI interrupt occurs, the DMA transfer is stopped. After returning from the NMI interrupt routine, set all channels again, and then restart the DMA transfer.
Page 686 Section 14 Direct Memory Access Controller (DMAC) Rev. 1.00 Oct. 01, 2007 Page 620 of 1956 REJ09B0256-0100...
Page 687: Section 15 External Cpu Interface (Excpu)
Section 15 External CPU Interface (EXCPU) Section 15 External CPU Interface (EXCPU) The DDR-SDRAM space in this LSI and internal registers of this LSI can be accessed by a CPU externally connected to the LSI (hereinafter, simply referred to as “external CPU”). Access by an external CPU is implemented using the MPX protocol.
Page 688: Input/Output Pins
Section 15 External CPU Interface (EXCPU) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the EXCPU. Table 15.1 Pin Configuration Pin Name Symbol Description EX_CS0 Chip select 0 Input Indicates access to the DDR-SDRAM space EX_CS1 Chip select 1 Input Indicates access to an internal register of this EX_BS...
Page 689: Register Descriptions
Section 15 External CPU Interface (EXCPU) 15.3 Register Descriptions Table 15.2 shows the EXCPU register configuration. Table 15.3 shows the register states in each operating mode. Table 15.2 Register Configuration Abbrevia- Area P4 Area 7 Access Register Name tion Address Address Size External CPU control register...
Page 690: External Cpu Control Register (Excctrl)
Section 15 External CPU Interface (EXCPU) 15.3.1 External CPU Control Register (EXCCTRL) EXCCTRL indicates whether an external CPU is connected and sets the type of the external CPU. Bit: − − − − − − − − − − − −...
Page 691: External Cpu Memory Space Select Register (Excmsetr)
Section 15 External CPU Interface (EXCPU) 15.3.2 External CPU Memory Space Select Register (EXCMSETR) EXCMSETR sets the base address used when the internal memory space of this LSI is accessed by the external CPU. Bit: − − − − − −...
Page 692: External Cpu Interrupt Output Control Register (Excinor)
Section 15 External CPU Interface (EXCPU) 15.3.3 External CPU Interrupt Output Control Register (EXCINOR) EXCINOR is used to generate an interrupt to the external CPU from this LSI. Bit: − − − − − − − − − − − −...
Page 693: Operation
Section 15 External CPU Interface (EXCPU) 15.4 Operation With this LSI, a CPU externally connected to the LSI (an external CPU) is allowed to access the DDR-SDRAM space or internal registers of the LSI by using the MPX protocol. The external CPU becomes ready to access the space in this LSI after this sequence: an access request (BREQ) from the external CPU is accepted by the LBSC, the local bus is released, and an access acknowledgement (BACK) is returned to the external CPU.
Page 694: Table 15.4 Access And Data Alignment For Little Endian
Section 15 External CPU Interface (EXCPU) Data Alignment Conversion for the External CPU For the external CPU, the EXCPU performs data alignment conversion with the same endian as this LSI. This conversion supports both big endian, where the upper byte is placed at the smaller address, and little endian, where the lower byte is placed at the smaller address.
Page 695: Table 15.5 Access And Data Alignment For Big Endian
Section 15 External CPU Interface (EXCPU) Table 15.5 Access and Data Alignment for Big Endian EX_AD31 to EX_AD23 to EX_AD15 to EX_AD7 to EX_AD24 EX_AD16 EX_AD8 EX_AD0 Byte access to address 0 Data 7 to data 0 Byte access to address 1 Data 7 to data 0 Byte access to address 2 Data 7 to data 0...
Page 696: Figure 15.2 External Cpu Access (Single Access)
Section 15 External CPU Interface (EXCPU) Timing Charts of External CPU Access External CPU access through the EXCPU is done through handshaking of the access request (BREQ) and access acknowledge (BACK) signals. Figures 15.2 and 15.3 show the access timing of the EXCPU and external CPU. Read access CLKOUT BREQ...
Page 697: Figure 15.3 External Cpu Access (Burst Access)
Section 15 External CPU Interface (EXCPU) Read access CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDWR High EX_AD[31:0] EX_RDY Write access CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDWR EX_AD[31:0] EX_RDY Figure 15.3 External CPU Access (Burst Access) Configuration of Connection to the External CPU Figure 15.4 shows the configuration of the connection between the external CPU and this LSI.
Page 698: Figure 15.4 Configuration Of Connection With External Cpu
Section 15 External CPU Interface (EXCPU) This LSI MD10 SH7750/7751 EXCPU BS/EX_BS CS2/EX_CS1 CS1/EX_CS0 RD/FRAME/EX_FRAME RD/FRAME RDWR/EX_RDWR RDWR D31/EX_AD31 to DATA31 to D0/EX_AD0 DATA0 A25/EX_SIZE2 to DATA31 to A23/EX_SIZE0 DATA29 RDY/EX_RDY EX_INT LBSC BREQ BSREQ BACK BSACK Figure 15.4 Configuration of Connection with External CPU Rev.
Page 699: Section 16 Clock Pulse Generator (Cpg)
Section 16 Clock Pulse Generator (CPG) Section 16 Clock Pulse Generator (CPG) The CPG generates clocks provided to the on-chip peripheral modules and external bus interface of this LSI, and controls the power-down mode function. The CPG consists of an oscillator, PLL circuits, frequency dividers, and control circuits.
Page 700: Figure 16.1 Block Diagram Of Cpg
Section 16 Clock Pulse Generator (CPG) A block diagram of the CPG is shown in figure 16.1. DDR clock （DDRck0） Divider 2 （DDRck90） ×1/4 （DDRck180） PLL cicuit 3 （DDRck270） ×４ PLL circuit 2 CLKOUT ×1 Bus clock Divider 1 （Bck） ×1/4 CPU clock Crystal...
Page 701 Section 16 Clock Pulse Generator (CPG) The functions of the blocks in the CPG are as follows. PLL Circuit 1 PLL circuit 1 multiples the frequency of the crystal oscillator or the clock input from the EXTAL pin by the ratio of ×16. The multiplication ratio is selected by the combination of mode control pins MD0, MD1, and MD2.
Page 702: Input/Output Pins
Section 16 Clock Pulse Generator (CPG) Module Stop Registers 0, 1(MSTPCR0 and MSTPCR1) The module stop registers have control bits for running/stopping the individual peripheral modules. (10) Standby Control Register (STBCR) The standby control register has bits for controlling the power-down modes. 16.2 Input/Output Pins Table 16.1 lists the CPG pin configuration.
Page 703: Clock Operating Mode
Section 16 Clock Pulse Generator (CPG) 16.3 Clock Operating Mode Table 16.2 shows the relationship between the mode control pin (MD0, MD1, and MD2) combinations and the clock operating mode after a power-on reset. Table 16.2 Clock Operating Modes External pin Clock EXTAL combination*...
Page 704: Register Descriptions
Section 16 Clock Pulse Generator (CPG) 16.4 Register Descriptions Table 16.3 shows the CPG register configuration. Table 16.4 shows the register states in each operating mode. Table 16.3 Register Configuration Abbrevia- Area P4 Area 7 Access Register Name tion Address Address Size Frequency control register...
Page 705: Frequency Control Register (Frqcr)
Section 16 Clock Pulse Generator (CPG) 16.4.1 Frequency Control Register (FRQCR) FRQCR is a 32-bit read-only register used to confirm the division ratios for the CPU clock (Ick), SHwy clock (SHck), peripheral clocks (Pck0, Pck1), and the bus clock (Bck) after a power-on reset.
Page 706 Section 16 Clock Pulse Generator (CPG) Initial Bit Name Value Description — Reserved This bit is always read as 0. 2 to 0 P1FC[2:0] 101 Peripheral Clock 1 (Pck1) Frequency Division Ratio 101: ×1/16 Rev. 1.00 Oct. 01, 2007 Page 640 of 1956 REJ09B0256-0100...
Page 707: Pll Control Register (Pllcr)
Section 16 Clock Pulse Generator (CPG) 16.4.2 PLL Control Register (PLLCR) PLLCR is a 32-bit readable/writable register that enables or disables clock output from the CLKOUT pin. PLLCR can be accessed only in longwords. Bit: − − − − − −...
Page 708: Notes On Board Design
R = 0 Ω Avoid crossing signal lines EXTAL XTAL SH7763 Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 16.2 Notes on Using Crystal Resonator Notes on Inputting External Clock via EXTAL Pin Make no connection to the XTAL pin.
Page 709: Figure 16.3 Notes On Using Pll Or Dll Oscillator Circuit
4.7Ω CPB11 CPB12 CPB11 = CPB21 = CPB31 = 0.1µF CPB12 = CPB22 = CPB32 = 1µF 0.1µF 1µF VSS-PLL1 RCB2 VDD-PLL2 4.7 Ω CPB21 CPB22 SH7763 0.1µF 1µF VSS-PLL2 RCB3 VDD-PLL3 4.7 Ω CPB31 CPB32 1.25V 0.1µF 1µF VSS-PLL3 Figure 16.3 Notes on Using PLL or DLL Oscillator Circuit...
Page 710 Section 16 Clock Pulse Generator (CPG) Rev. 1.00 Oct. 01, 2007 Page 644 of 1956 REJ09B0256-0100...
Page 711: Section 17 Watchdog Timer And Reset (Wdt)
Section 17 Watchdog Timer and Reset (WDT) Section 17 Watchdog Timer and Reset (WDT) The reset and watchdog timer (WDT) control circuit comprises the reset control unit and WDT control unit which control the power-on reset sequence and a reset for on-chip peripheral modules and external devices.
Page 712: Figure 17.1 System Block Diagram
Section 17 Watchdog Timer and Reset (WDT) Figure 17.1 is a system block diagram. Watchdog timer and Reset PRESET Reset control circuit Internal reset request STATUS[1:0] MRESET Interrupt INTC control circuit Internal reset request WDTCSR WDTCNT WDTBCNT Peripheral clock Comparator Comparator WDTST WDTBST...
Page 713: Input/Output Pins
Section 17 Watchdog Timer and Reset (WDT) 17.2 Input/Output Pins Table 17.1 shows the pin configuration of the reset control unit. Table 17.1 Pin Configuration Pin name Function Description PRESET Power-on reset input Input Power-on reset occurs at low-level MRESET Manual reset input Input Manual reset occurs at low-level...
Page 714: Register Descriptions
Section 17 Watchdog Timer and Reset (WDT) 17.3 Register Descriptions Table 17.2 shows the registers of the reset and watchdog timer. Table 17.3 shows the register state in each operating mode. Table 17.2 Register Configuration Access Register Name Abbreviation R/W P4 Address Area 7 Address Size...
Page 715: Watchdog Timer Stop Time Register (Wdtst)
Section 17 Watchdog Timer and Reset (WDT) 17.3.1 Watchdog Timer Stop Time Register (WDTST) WDTST is a readable/writable 32-bit register that specifies the time until a watchdog timer overflows. The time until WDTCNT overflows becomes the minimum value when set H'001 to the bits 11 to 0, and the maximum value when set H'000 to the bits 11 to 0.
Page 716: Watchdog Timer Control/Status Register (Wdtcsr)
Section 17 Watchdog Timer and Reset (WDT) 17.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a readable/writable 32-bit register that comprises the timer mode-selecting bit and overflow flags. Use a longword access to write to the WDTCSR, with H'A5 in the bits 31 to 24. The reading value of bits 31 to 24 is always H'00.
Page 717 Section 17 Watchdog Timer and Reset (WDT) Initial Bit Name Value Description RSTS Reset Select Specifies the kind of reset to be performed when WDTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. 0: Power-on reset 1: Manual reset WOVF Watchdog Timer Overflow Flag...
Page 718: Watchdog Timer Base Stop Time Register (Wdtbst)
Section 17 Watchdog Timer and Reset (WDT) 17.3.3 Watchdog timer Base Stop Time Register (WDTBST) WDTBST is a readable/writable 32-bit register that clears WDTBCNT. Use a longword access to clear the WDTBCNT, with H'A5 in the bits 31 to 24. The reading value of bits WDTBST is always H'0000 0000.
Page 719: Watchdog Timer Counter (Wdtcnt)
Section 17 Watchdog Timer and Reset (WDT) 17.3.4 Watchdog Timer Counter (WDTCNT) WDTCNT is a 32-bit read-only register that comprises 12-bit watchdog timer counter and counts up on the WDTBCNT overflow signal. When WDTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt is generated in interval timer mode.
Page 720: Operation
Section 17 Watchdog Timer and Reset (WDT) 17.4 Operation 17.4.1 Reset request Power-on reset and manual reset are available. These sources are follows. Power-on reset 1. Reset sources • Input low level via PRESET pin. • The WDTCNT overflows when the WT/IT bit in the WDTCSR is 1, and the RSTS bit is 0. •...
Page 721: Using Watchdog Timer Mode
Section 17 Watchdog Timer and Reset (WDT) Manual reset 1. Reset sources • Input low level via MRESET pin. • When a general exception other than a user break occurs while the BL bit is set to 1 in SR •...
Page 722: Using Interval Timer Mode
Section 17 Watchdog Timer and Reset (WDT) 4. During operation in watchdog timer mode, clear to the WDTCNT or WDTBCNT periodically so that WDTCNT does not overflow. See section 17.4.5, Clearing WDT Counter for WDT counter clear method. 5. When the WDTCNT overflows, the WDT sets the WOVF flag in WDTCSR to 1, and generates a reset of the type specified by the RSTS bit.
Page 723: Figure 17.2 Wdt Counting Up Operation
Section 17 Watchdog Timer and Reset (WDT) WDT mode: Interval timer mode: Clear counter after WDTCNT Clear counter when overflowed value reset operation Setting value of WDTST Counting up with overflow signal of WDTBCNT H'0000 0000 Time WDTBCNT Clear counter value when overflowed H'0003 FFFF...
Page 724: Clearing Wdt Counter
Section 17 Watchdog Timer and Reset (WDT) WDTBCNT is an 18-bit up-counter operated on the peripheral clock0 (Pck0). WDTBCNT is cleared when H'55 is set to the bits 31 to 24 in WDTBST. If the peripheral clock frequency is 66.6 MHz, the WDTBCNT overflow time is approximately ×...
Page 725: Status Pin Change Timing During Reset
Section 17 Watchdog Timer and Reset (WDT) 17.5 Status Pin Change Timing during Reset 17.5.1 Power-On Reset by PRESET A power-on reset is to initialize the on-chip PLL circuit when this LSI goes to the power-on reset state by the PERSET pin low level input and then it is necessary to ensure the synchronization settling time of the PLL circuit.
Page 726: Figure 17.3 Status Output During Power-On
Section 17 Watchdog Timer and Reset (WDT) EXTAL input CLKOUT output PRESET input TRST input STATUS[1:0] HH (reset) LL (normal) output EXTAL input PLL oscillation Reset holding stabilization time settling time time Figure 17.3 STATUS Output during Power-on Rev. 1.00 Oct. 01, 2007 Page 660 of 1956 REJ09B0256-0100...
Page 727: Figure 17.4 Status Output By Reset Input During Normal Operation
Section 17 Watchdog Timer and Reset (WDT) PRESET input during normal operation It is necessary to ensure the PLL oscillation settling time when the PRESET input during normal operation. EXTAL input CLKOUT output PRESET input STATUS[1:0] LL (normal) HH (reset) LL (normal) output PLL oscillation...
Page 728: Power-On Reset By Watchdog Timer Overflow
Section 17 Watchdog Timer and Reset (WDT) 17.5.2 Power-On Reset by Watchdog Timer Overflow The power-on reset time (watchdog timer reset holding time) by the watchdog timer overflowed is 3774 clock cycles of the EXTAL pin input clock and thereafter equal to or more than 45 clock cycles of the peripheral clock (Pck0).
Page 729: Figure 17.7 Status Output By Watchdog Timer Overflow Power-On Reset During Sleep Mode
Section 17 Watchdog Timer and Reset (WDT) Power-On Reset by Watchdog timer Overflowed in Sleep Mode EXTAL input CLKOUT output WDT overflow signal STATUS[1:0] HH (reset) LL (normal) output WDT reset WDT reset stabilization time holding time Figure 17.7 STATUS Output by Watchdog timer overflow Power-On Reset during Sleep Mode Rev.
Page 730: Manual Reset By Watchdog Timer Overflow
Section 17 Watchdog Timer and Reset (WDT) 17.5.3 Manual Reset by Watchdog Timer Overflow The manual reset time (watchdog timer manual reset holding time) by the watchdog timer overflowed is equal to or more than 3774 clock cycles of the EXTAL pin input clock. The transition time from watchdog timer overflowed to manual reset state (watchdog timer reset setup time) is 1 clock cycle of the EXTAL input and thereafter equal to or more than 5 clock cycles of the peripheral clock (Pck0).
Page 731: Figure 17.9 Status Output By Watchdog Timer Overflow Manual Reset During Sleep Mode
Section 17 Watchdog Timer and Reset (WDT) Manual Reset by Watchdog timer Overflowed in Sleep Mode EXTAL input CLKOUT output WDT overflow signal STATUS[1:0] HL (sleep) HH (reset) LL (normal) output WDT reset WDT reset stabilization time holding time Figure 17.9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep Mode Rev.
Page 732 Section 17 Watchdog Timer and Reset (WDT) Rev. 1.00 Oct. 01, 2007 Page 666 of 1956 REJ09B0256-0100...
Page 733: Section 18 Power-Down Mode
Section 18 Power-Down Mode Section 18 Power-Down Mode In power-down modes, operations of the CPU and some of the on-chip peripheral modules are stopped to reduce power consumption. 18.1 Features • Supports sleep mode and module standby mode • Supports RTC power supply backup mode where the power supply for only the RTC is held and other power supplies are turned off •...
Page 734: Table 18.1 States In Power-Down Modes
Section 18 Power-Down Mode Table 18.1 lists the states of the CPU and on-chip peripheral modules in each mode. Table 18.1 States in Power-Down Modes State On-Chip Peripheral Power- Module On-Chip DDR- Down Transition CPG CPU Memory SDRAM Mode Condition Others Cancellation Sleep...
Page 735: Input/Output Pins
Section 18 Power-Down Mode 4. Hi-Z state, except for the RTC module interface pins 5. Undefined, except for DDR-SDRAM interface pins 6. AR: auto-refresh: SR: self-refresh 7. S1 and S0 are the output states on the STATUS1 and STATUS0 pins, respectively. 8.
Page 736: Register Descriptions
Section 18 Power-Down Mode 18.3 Register Descriptions Table 18.3 shows the register configuration for power-down modes. Table 18.4 shows the register states in each operating mode. Table 18.3 Register Configuration Area P4 Area 7 Access Register Name Abbreviation R/W Address Address Size Standby control register...
Page 737: Standby Control Register (Stbcr)
Section 18 Power-Down Mode 18.3.1 Standby Control Register (STBCR) STBCR is a 32-bit readable/writable register that selects a power-down mode to be entered after a SLEEP instruction is executed. STBCR can be accessed only in longwords. Bit: − − − −...
Page 738: Module Stop Register 0 (Mstpcr0)
Section 18 Power-Down Mode 18.3.2 Module Stop Register 0 (MSTPCR0) MSTPCR0 is a 32-bit readable/writable register that can individually start or stop the module assigned to each bit. MSTPCR0 can be accessed only in longwords. Bit: — — — — —...
Page 739: Module Stop Register 1 (Mstpcr1)
Section 18 Power-Down Mode 18.3.3 Module Stop Register 1 (MSTPCR1) MSTPCR1 is a 32-bit readable/writable register that can individually start or stop the module assigned to each bit. MSTPCR1 can be accessed only in longwords. Bit: — STIF1 STIF0 SSI3 SSI2 SSI1 SSI0...
Page 740 Section 18 Power-Down Mode Initial Bit Name Value Description STIF1 STIF1 Module Stop Bit When set to 1, the clock supply to the STIF1 module is halted. 0: STIF1 operates 1: Clock supply to STIF1 is halted STIF0 STIF0 Module Stop Bit When set to 1, the clock supply to the STIF0 module is halted.
Page 741 Section 18 Power-Down Mode Initial Bit Name Value Description IIC1 IIC1 Module Stop Bit When set to 1, the clock supply to the IIC1 module is halted. 0: IIC1 operates 1: Clock supply to IIC1 is halted IIC0 IIC0 Module Stop Bit When set to 1, the clock supply to the IIC0 module is halted.
Page 742 Section 18 Power-Down Mode Initial Bit Name Value Description SCIF1 SCIF1 Module Stop Bit When set to 1, the clock supply to the SCIF1 module is halted. 0: SCIF1 operates 1: Clock supply to SCIF1 is halted SCIF0 SCIF0 Module Stop Bit When set to 1, the clock supply to the SCIF0 module is halted.
Page 743 Section 18 Power-Down Mode Initial Bit Name Value Description TMU1 TMU1 Module Stop Bit When set to 1, the clock supply to the TMU1 module is halted. 0: TMU1 operates 1: Clock supply to TMU1 is halted TMU0 TMU0 Module Stop Bit When set to 1, the clock supply to the TMU0 module is halted.
Page 744: Sleep Mode
Section 18 Power-Down Mode 18.4 Sleep Mode 18.4.1 Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of the CPU registers remain unchanged.
Page 745: Software Standby Mode
Section 18 Power-Down Mode 18.5 Software Standby Mode 18.5.1 Transition to Software Standby Mode Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the program execution state to software standby mode. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
Page 746: Module Standby Mode
Section 18 Power-Down Mode 18.6 Module Standby Mode 18.6.1 Transition to Module Standby Mode Setting the bits in the module stop register to 1 halts the clock supply to the corresponding on-chip peripheral modules. This function can be used to reduce power consumption in normal mode. Modules in module standby mode keep the state immediately before the transition to the module standby mode.
Page 747: Ddr-Sdram Power Supply Backup
Section 18 Power-Down Mode 18.7 DDR-SDRAM Power Supply Backup 18.7.1 Control of Self-Refresh and Initialization To preserve the contents of the DDR-SDRAM with battery backup, make sure that the DDR- SDRAM is in the self-refresh mode before turning off the system power supply. When the system power supply is turned on, initialization of the DDR-SDRAM or cancellation of the self-refresh mode must be performed according to whether the DDR-SDRAM has been in self-refresh mode or has not been initialized.
Page 748: Ddr-Sdram Backup Sequence When Turning Off System Power Supply
Section 18 Power-Down Mode Transition to self-refresh System power System power Power-on M_CKE asserted mode completed supply supply reset by SMS bits in SCR turned off turned on canceled PRESET Delay time of LSI internal reset DDRIF reset (1.2 V, 3.3 V) M_CKE M_BKPRST Figure 18.1 DDR-SDRAM Interface Operation when...
Page 749: Figure 18.2 Sequence For Turning Off System Power Supply After Entering Self-Refresh Mode
Section 18 Power-Down Mode After the system power supply is turned on, the M_CKE output may remain unstable until the clock is supplied after the LSI power supply has become stable. Therefore, use the M_BKPRST signal to keep the M_CKE signal input of the DDR-SDRAM low until the power-on reset is canceled.
Page 750: Rtc Power Supply Backup
Section 18 Power-Down Mode 18.8 RTC Power Supply Backup 18.8.1 Transition to RTC Power Supply Backup Mode When entering the RTC power supply backup mode with the VDD power supply (1.2 V) turned off, the VDD power supply should be turned off while the XRTCSTBI signal is held low. By turning off the VDD power supply, the currents that might be generated in the VDD (1.2 V) operating region can be eliminated to reduce power consumption.
Page 751: Status Pin Signal Change Timing
Section 18 Power-Down Mode System power supply System power supply turned off turned on High-level VDD-RTC RTC battery backup state RTC standby XRTCSTBI Power-on reset canceled PRESET (1) Oscillation stabilization time at power-on (2) Reset delay time at the RTC Figure 18.3 Sequence for Turning VDD Power Supply (1.2 V) On/Off 18.9 STATUS Pin Signal Change Timing...
Page 752 Section 18 Power-Down Mode Rev. 1.00 Oct. 01, 2007 Page 686 of 1956 REJ09B0256-0100...
Page 753: Section 19 Timer Unit (Tmu)
Section 19 Timer Unit (TMU) Section 19 Timer Unit (TMU) This LSI includes an on-chip 32-bit timer unit (TMU), which has six channels (channels 0 to 5). 19.1 Features The TMU has the following features. • Auto-reload type 32-bit down-counter provided for each channel •...
Page 754: Figure 19.1 Block Diagram Of Tmu
Section 19 Timer Unit (TMU) Figure 19.1 shows a block diagram of the TMU. RESET, TCLK RTCCLK TUNI0, 1, 3, Pck/4, Pck/16, STBY etc. 4, and 5 Pck/64* TUNI2 TUNI2 TCLK operation Prescaler controller controller To each To channels channel 0 to 2 TOCR TSTR...
Page 755: Input/Output Pins
Section 19 Timer Unit (TMU) 19.2 Input/Output Pins Table 19.1 shows the TMU pin configuration. Table 19.1 Pin Configuration Pin Name Function Description TMU_TCLK Clock input Input Channel 0, 1 and 2 external clock input pin/channel 2 input capture control input pin Rev.
Page 756: Register Descriptions
Section 19 Timer Unit (TMU) 19.3 Register Descriptions Table 19.2 shows register configuration. Table 19.3 shows the register states in each operating mode. Table 19.2 Register Configuration Channel Register Name Abbrev. R/W P4 Address Area 7 Address Size 0,1,2 Timer output control register TOCR H'FFD8 0000 H'1FD8 0000...
Page 757: Table 19.3 Register States In Each Operating Mode
Section 19 Timer Unit (TMU) Table 19.3 Register States in Each Operating Mode Power-on Channel Register Name Abbrev. Reset Manual Reset Sleep Standby 0,1,2 Timer output control register TOCR H'00 H'00 Retained Retained Common Timer start register 0 TSTR0 H'00 H'00 Retained Retained...
Page 758: Timer Output Control Register (Tocr)
Section 19 Timer Unit (TMU) 19.3.1 Timer Output Control Register (TOCR) TOCR is an 8-bit read-only register that specifies whether external pin TMU_TCLK is used as the external clock or input capture control input pin. BIt: — — — — —...
Page 759: Timer Start Register (Tstr)
Section 19 Timer Unit (TMU) 19.3.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether TCNT in each channel is operated or stopped. • TSTR0 BIt: — — — — — STR2 STR1 STR0 Initial value: R/W: Initial Bit Name...
Page 760 Section 19 Timer Unit (TMU) • TSTR1 BIt: — — — — — STR5 STR4 STR3 Initial value: R/W: Initial Bit Name Value Description 7 to 3 — All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 761: Timer Constant Register (Tcorn) (N = 0 To 5)
Section 19 Timer Unit (TMU) 19.3.3 Timer Constant Register (TCORn) (n = 0 to 5) The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value.
Page 762: Timer Control Registers (Tcrn) (N = 0 To 5)
Section 19 Timer Unit (TMU) 19.3.5 Timer Control Registers (TCRn) (n = 0 to 5) The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating TCNT underflow is set to 1.
Page 763 Section 19 Timer Unit (TMU) Initial Bit Name Value Description ICPE1* Input Capture Control ICPE0* These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used.
Page 764: Input Capture Register 2 (Tcpr2)
Section 19 Timer Unit (TMU) Initial Bit Name Value Description TPSC2 Timer Prescaler 2 to 0 TPSC1 These bits select the TCNT count clock. TPSC0 000: Counts on Pck0/4 001: Counts on Pck0/16 010: Counts on Pck0/64 011: Counts on Pck0/256 100: Counts on Pck0/1024 101: Setting prohibited 110: Counts on on-chip RTC output clock...
Page 765: Operation
Section 19 Timer Unit (TMU) 19.4 Operation Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). Each TCNT performs count-down operation. The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function.
Page 766: Figure 19.2 Example Of Count Operation Setting Procedure
Section 19 Timer Unit (TMU) Select operation Select the count clock with the TPSC2 to TPSC0 bits Select count clock in TCR. When the external clock (TCLK) is selected, specify the external clock edge with the CKEG1 and CKEG0 bits in TCR. Underflow interrupt Specify whether an interrupt is to be generated on generation setting...
Page 767: Figure 19.3 Tcnt Auto-Reload Operation
Section 19 Timer Unit (TMU) Auto-Reload Count Operation Figure 19.3 shows the TCNT auto-reload operation. TCNT value TCOR value set in TCNT on underflow TCOR H'0000 0000 Time STR0 to STR5 Figure 19.3 TCNT Auto-Reload Operation TCNT Count Timing • Operating on internal clock Any of five count clocks (Pck0/4, Pck0/16, Pck0/64, Pck0/256, or Pck0/1024) scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR.
Page 768: Figure 19.5 Count Timing When Operating On External Clock
Section 19 Timer Unit (TMU) • Operating on external clock In channels 0, 1, and 2, the external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR. The detected edge (rising, falling, or both edges) can be selected with the CKEG1 and CKEG0 bits in TCR.
Page 769: Input Capture Function
Section 19 Timer Unit (TMU) 19.4.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use bits TPSC2 to TPSC0 in TCR to set an internal clock as the timer operating clock. 2.
Page 770: Interrupts
Section 19 Timer Unit (TMU) 19.5 Interrupts There are seven TMU interrupt sources: underflow interrupts and the input capture interrupt when the input capture function is used. Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when both the UNF bit and the interrupt enable bit (UNIE) for that channel are set to 1.
Page 771: Usage Notes
Section 19 Timer Unit (TMU) 19.6 Usage Notes 19.6.1 Register Writes When writing to a TMU register, timer count operation must be stopped by clearing the start bit (STR5 to STR0) for the relevant channel in TSTR. Note that TSTR can be written to, and the UNF and ICPF bits in TCR can be cleared while the count is in progress.
Page 772 Section 19 Timer Unit (TMU) Rev. 1.00 Oct. 01, 2007 Page 706 of 1956 REJ09B0256-0100...
Page 773: Section 20 16-Bit Timer Pulse Unit (Tpu)
Section 20 16-Bit Timer Pulse Unit (TPU) Section 20 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises four 16-bit timer channels. 20.1 Features • Maximum 4-pulse output  A total of 16 timer general registers (TGRA to TGRD × 4 ch.) are provided (four each for channels).
Page 774: Table 20.1 Tpu Functions
Section 20 16-Bit Timer Pulse Unit (TPU) Table 20.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Count clock Pck0/1 Pck0/1 Pck0/1 Pck0/1 Pck0/4 Pck0/4 Pck0/4 Pck0/4 Pck0/16 Pck0/16 Pck0/16 Pck0/16 Pck0/64 Pck0/64 Pck0/64 Pck0/64   TPU_TI2A TPU_TI3A ...
Page 775: Figure 20.1 Block Diagram Of Tpu
Section 20 16-Bit Timer Pulse Unit (TPU) Figure 20.1 shows a block diagram of the TPU. Pck0/1 Pck0/4 Counter Clock Edge Pck0 Divider Pck0/16 selection selection Pck0/64 Output control TPU_TO0 Note 1 Channel 0 clear TGRA Buffer TGRB Comparator TGRC TGRD Channel 1 Same as channel 0...
Page 776: Input/Output Pins
Section 20 16-Bit Timer Pulse Unit (TPU) 20.2 Input/Output Pins Table 20.2 summarizes the TPU related external pins. Table 20.2 TPU Pin Configurations Channel Name Pin Name Function Output compare TPU_TO0 Output TGR0A output compare output/PWM output match 0 Output compare TPU_TO1 Output TGR1A output compare output/PWM output match 1...
Page 777: Register Descriptions
Section 20 16-Bit Timer Pulse Unit (TPU) 20.3 Register Descriptions Table 20.3 shows the TPU register configuration. Table 20.4 shows the register state in each operating mode. Table 20.3 Register Configuration Area P4 Area 7 Access Register Name Abbreviation Address* Address* Size Timer start register...
Page 778 Section 20 16-Bit Timer Pulse Unit (TPU) Area P4 Area 7 Access Register Name Abbreviation Address* Address* Size Timer interrupt enable register_2 TIER_2 H'FFE2 809C H'1FE2 809C 16 Timer status register_2 TSR_2 H'FFE2 80A0 H'1FE2 80A0 16 Timer counter_2 TCNT_2 H'FFE2 80A4 H'1FE2 80A4 16 Timer general register A_2 TGRA_2...
Page 779: Table 20.4 Register State In Each Operating Mode
Section 20 16-Bit Timer Pulse Unit (TPU) Table 20.4 Register State in Each Operating Mode Power-On Manual Register Name Abbreviation Reset Reset Sleep Standby Timer start register TSTR H'0000 H'0000 Retained Retained Timer control register_0 TCR_0 H'0000 H'0000 Retained Retained Timer mode register_0 TMDR_0 H'0000...
Page 780 Section 20 16-Bit Timer Pulse Unit (TPU) Power-On Manual Register Name Abbreviation Reset Reset Sleep Standby Timer general register C_2 TGRC_2 H'FFFF H'FFFF Retained Retained Timer general register D_2 TGRD_2 H'FFFF H'FFFF Retained Retained Timer control register_3 TCR_3 H'0000 H'0000 Retained Retained Timer mode register_3...
Page 781: Timer Control Registers (Tcr)
Section 20 16-Bit Timer Pulse Unit (TPU) 20.3.1 Timer Control Registers (TCR) The TCR registers are 16-bit registers that control the TCNT channels. The TPU has four TCR registers, one for each of channels 0 to 3. The TCR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby.
Page 782: Table 20.5 Tpu Clock Sources
Section 20 16-Bit Timer Pulse Unit (TPU) Initial Bit Name Value Description 4, 3 CKEG[1:0] 00 Clock Edge These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g.
Page 783: Table 20.6 Tpsc[2:0] (1)
Section 20 16-Bit Timer Pulse Unit (TPU) Table 20.6 TPSC[2:0] (1) Channel TPSC[2] TPSC[1] TPSC[0] Description Internal clock: counts on Pck0/1 (Initial value) Internal clock: counts on Pck0/4 Internal clock: counts on Pck0/16 Internal clock: counts on Pck0/64 Reserved (setting prohibited) Table 20.6 TPSC[2:0] (2) Channel TPSC[2]...
Page 784: Table 20.6 Tpsc[2:0] (4)
Section 20 16-Bit Timer Pulse Unit (TPU) Table 20.6 TPSC[2:0] (4) Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pck0/1 (Initial value) Internal clock: counts on Pck0/4 Internal clock: counts on Pck0/16 Internal clock: counts on Pck0/64 External clock: counts on TPU_TI3A pin input Reserved (setting prohibited) Note: Don't care...
Page 785: Timer Mode Registers (Tmdr)
Section 20 16-Bit Timer Pulse Unit (TPU) 20.3.2 Timer Mode Registers (TMDR) The TMDR registers are 16-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has four TMDR registers, one for each channel. The TMDR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby.
Page 786 Section 20 16-Bit Timer Pulse Unit (TPU) Initial Bit Name Value Description  Reserved This bit is always read as 0 and cannot be modified. 2 to 0 MD[2:0] Modes These bits are used to set the timer operating mode. 000: Normal operation 001: Reserved (setting prohibited) 010: PWM mode...
Page 787: Timer I/O Control Registers (Tior)
Section 20 16-Bit Timer Pulse Unit (TPU) 20.3.3 Timer I/O Control Registers (TIOR) The TIOR registers are 16-bit registers that control the TPU_TO pin. The TPU has four TIOR registers, one for each channel. The TIOR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby.
Page 788: Table 20.7 Ioa[2:0]
Section 20 16-Bit Timer Pulse Unit (TPU) Table 20.7 IOA[2:0] Channels IOA[2] IOA[1] IOA[0] Description 0 to 3 Always 0 output (Initial value) Initial output is 0 0 output at TGRA compare match* output for 1 output at TGRA compare match TPU_TO pin Toggle output TGRA at compare match* Always 1 output...
Page 789: Timer Interrupt Enable Registers (Tier)
Section 20 16-Bit Timer Pulse Unit (TPU) 20.3.4 Timer Interrupt Enable Registers (TIER) The TIER registers are 16-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has four TIER registers, one for each channel. The TIER registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode or module standby.
Page 790 Section 20 16-Bit Timer Pulse Unit (TPU) Initial Bit Name Value Description TG1EC TGR Interrupt Enable C Enables or disables interrupt requests by the TGFC bit when the TGFC bit in TSR is set to 1 (TCNT and TGRC compare match).
Page 791: Timer Status Registers (Tsr)
Section 20 16-Bit Timer Pulse Unit (TPU) 20.3.5 Timer Status Registers (TSR) The TSR registers are 16-bit registers that indicate the status of each channel. The TPU has four TSR registers, one for each channel. The TSR registers are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode or module standby mode.
Page 792 Section 20 16-Bit Timer Pulse Unit (TPU) Initial Bit Name Value R/W Description TCFV R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) TGFD...
Page 793: Timer Counters (Tcnt)
Section 20 16-Bit Timer Pulse Unit (TPU) Initial Bit Name Value R/W Description TGFA R/(W)* Output Compare Flag A Status flag that indicates the occurrence of TGRA compare match. [Clearing conditions] When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] When TCNT = TGRA Note:...
Page 794: Timer Start Register (Tstr)
Section 20 16-Bit Timer Pulse Unit (TPU) 20.3.8 Timer Start Register (TSTR) TSTR is a 16-bit readable/writable register that selects TCNT operation/stoppage for channels 0 to 3. TSTR is initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby.
Page 795: Operation
Section 20 16-Bit Timer Pulse Unit (TPU) 20.4 Operation 20.4.1 Overview Operation in each mode is outlined below. Normal Operation Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Buffer Operation When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR.
Page 796: Basic Functions
Section 20 16-Bit Timer Pulse Unit (TPU) 20.4.2 Basic Functions Counter Operation When one of bits CST[0:3] is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. Example of count operation setting procedure Figure 20.2 shows an example of the count operation setting procedure.
Page 797: Figure 20.3 Free-Running Counter Operation
Section 20 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 798: Figure 20.4 Periodic Counter Operation
Section 20 16-Bit Timer Pulse Unit (TPU) Figure 20.4 illustrates periodic counter operation. Counter cleared by TGRA TCNT value compare match H'0000 Time CST bit Flag cleared by software TGFA Figure 20.4 Periodic Counter Operation Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin (TPU_TO pin) using TGRA compare match.
Page 799: Figure 20.6 Example Of 0 Output/1 Output Operation
Section 20 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 20.6 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Page 800: Buffer Operation
Section 20 16-Bit Timer Pulse Unit (TPU) 20.4.3 Buffer Operation Buffer operation, enables TGRC and TGRD to be used as buffer registers. Table 20.8 shows the register combinations used in buffer operation. Table 20.8 Register Combinations in Buffer Operation Timer General Register Buffer Register TGRA TGRC...
Page 801: Figure 20.9 Example Of Buffer Operation Setting Procedure
Section 20 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure Figure 20.9 shows an example of the buffer operation setting procedure. [1] Designate TGR for buffer operation with bits Buffer operation BFA and BFB in TMDR. [2] Set rewriting timing from the buffer register with Set buffer operation bit BFWT in TMDR.
Page 802: Figure 20.10 Example Of Buffer Operation
Section 20 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Figure 20.10 shows an operation example in which PWM mode has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A (TPU_TO pin), and 0 output at counter clearing.
Page 803: Pwm Modes
Section 20 16-Bit Timer Pulse Unit (TPU) 20.4.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, or 1, output can be selected as the output level in response to compare match of each TGRA. Designating TGRB compare match as the counter clearing source enables the period to be set in that register.
Page 804: Figure 20.11 Example Of Pwm Mode Setting Procedure
Section 20 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure Figure 20.11 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 805: Figure 20.12 Example Of Pwm Mode Operation (1)
Section 20 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation Figure 20.12 shows an example of PWM mode operation. In this example, TGRB compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRA output value.
Page 806: Phase Counting Mode
Section 20 16-Bit Timer Pulse Unit (TPU) 20.4.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 2, and 3. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 807: Figure 20.14 Example Of Phase Counting Mode Setting Procedure
Section 20 16-Bit Timer Pulse Unit (TPU) Example of Phase Counting Mode Setting Procedure Figure 20.14 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to Phase counting mode MD0 in TMDR. [2] Set the external pin function in pin function controller (PFC).
Page 808: Figure 20.15 Example Of Phase Counting Mode 1 Operation
Section 20 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Phase counting mode 1 Figure 20.15 shows an example of phase counting mode 1 operation, and table 20.10 summarizes the TCNT up/down-count conditions.
Page 809: Figure 20.16 Example Of Phase Counting Mode 2 Operation
Section 20 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 20.16 shows an example of phase counting mode 2 operation, and table 20.11 summarizes the TCNT up/down-count conditions. TPU_ TI2A (Channel 2) TPU_ TI3A (Channel 3) TPU_ TI2B (Channel 2) TPU_ TI3B (Channel 3) TCNT value Up-count...
Page 810: Figure 20.17 Example Of Phase Counting Mode 3 Operation
Section 20 16-Bit Timer Pulse Unit (TPU) Phase counting mode 3 Figure 20.17 shows an example of phase counting mode 3 operation, and table 20.12 summarizes the TCNT up/down-count conditions. TPU_ TI2A (channel 2) TPU_ TI3A (channel 3) TPU_ TI2B (channel 2) TPU_ TI3B (channel 3) TCNT value Down-count...
Page 811: Figure 20.18 Example Of Phase Counting Mode 4 Operation
Section 20 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 20.18 shows an example of phase counting mode 4 operation, and table 20.13 summarizes the TCNT up/down-count conditions. TPU_ TI2A (channel 2) TPU_ TI3A (channel 3) TPU_ TI2B (channel 2) TPU_ TI3B (channel 3) TCNT value Down-count...
Page 812: Usage Notes
Section 20 16-Bit Timer Pulse Unit (TPU) 20.5 Usage Notes Note that the kinds of operation and contention described below can occur during TPU operation. Input Clock Restrictions The input clock pulse width must be at least 2 states in the case of single-edge detection, and at least 3 states in the case of both-edge detection.
Page 813: Section 21 Compare Match Timer (Cmt)
Section 21 Compare Match Timer (CMT) Section 21 Compare Match Timer (CMT) This LSI includes a 32-bit compare match timer (CMT) of five channels (channel 0 to channel 4). 21.1 Features • 16 bits/32 bits can be selected. • Each channel is provided with an auto-reload up counter. •...
Page 814: Figure 21.1 Block Diagram Of Cmt
Section 21 Compare Match Timer (CMT) Figure 21.1 shows a block diagram of the CMT. CMSTR Pck0 Pre-scaller CMCNT_0 CMCOR_0 Internal interrupt CMCSR_0 Interrupt control DMA transfer Pre-scaller CMCNT_1 CMCOR_1 Internal interrupt CMCSR_1 Interrupt control DMA transfer Pre-scaller CMCNT_2 CMCOR_2 Internal interrupt CMCSR_2 Interrupt control...
Page 815: Register Descriptions
Section 21 Compare Match Timer (CMT) 21.2 Register Descriptions Table 21.2 shows the CMT register configuration. Table 21.3 shows the register state in each operating mode. Table 21.1 Register Configuration Area P4 Area 7 Access Register Name Abbreviation R/W Address* Address* Size Compare match timer start register...
Page 816: Table 21.2 Register State In Each Operating Mode
Section 21 Compare Match Timer (CMT) Table 21.2 Register State in Each Operating Mode Power-On Manual Register Name Abbreviation Reset Reset Sleep Standby Compare match timer CMSTR H'0000 H'0000 Retained Retained start register Compare match timer CMCSR_0 H'0000 H'0000 Retained Retained control/status register_0 Compare match timer...
Page 817: Compare Match Timer Start Register (Cmstr)
Section 21 Compare Match Timer (CMT) 21.2.1 Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether the compare match timer counter (CMCNT) is operated or halted. Bit:         ...
Page 818: Compare Match Timer Control/Status Register (Cmcsr)
Section 21 Compare Match Timer (CMT) 21.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates the occurrence of compare matches, enables interrupts and DMA transfer request, and sets the counter input clocks. Do not change bits other than bits CMF and OVF during the compare match timer counter (CMCNT) operation.
Page 819 Section 21 Compare Match Timer (CMT) Initial Bit Name Value Description 13 to 10  All 0 Reserved These bits are always read as 0. The write value should always be 0. Compare Match Timer Counter Size Selects whether the compare match timer counter (CMCNT) is used as a 16-bit counter or a 32-bit counter.
Page 820: Compare Match Timer Counter (Cmcnt)
Section 21 Compare Match Timer (CMT) Initial Bit Name Value Description 2 to 0 CKS[2:0] All 0 Clock Select These bits select the clock input to CMCNT. When the STRn (n: 4 to 0) bit in CMSTR is set to 1, CMCNT begins incrementing with the clock selected by these bits.
Page 821: Operation
Section 21 Compare Match Timer (CMT) 21.3 Operation 21.3.1 Counter Operation The CMT starts the operation of the counter by writing a 1 to the STRn bit in CMSTR of a channel that has been selected for operation. Complete all of the settings before starting the operation.
Page 822: Counter Size
Section 21 Compare Match Timer (CMT) Value in CMCNT CMCOR H'00000000 Time CMF=1 OVF=1 (When an overflow is detected) Figure 21.3 Counter Operation (Free-Running Operation) 21.3.2 Counter Size In this module, the size of the counter is selectable as either 16 or 32 bits. This is selected by the CMS bit in CMCSR.
Page 823: Dma Transfer Requests And Internal Interrupt Requests To Cpu
Section 21 Compare Match Timer (CMT) 21.3.4 DMA Transfer Requests and Internal Interrupt Requests to CPU The setting of bits CMR1 and CMR0 in CMCSR selects the sending of a request for a DMA transfer or for an internal interrupt to the CPU at a compare match. A DMA transfer request has different specifications according to the CMT channel as described below.
Page 824 Section 21 Compare Match Timer (CMT) Rev. 1.00 Oct. 01, 2007 Page 758 of 1956 REJ09B0256-0100...
Page 825: Section 22 Realtime Clock (Rtc)
Section 22 Realtime Clock (RTC) Section 22 Realtime Clock (RTC) This LSI includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 22.1 Features The RTC has the following features. • Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years.
Page 826: Block Diagram
Section 22 Realtime Clock (RTC) 22.1.1 Block Diagram Figure 22.1 shows a block diagram of the RTC. RTC clock output Reset 16.384 kHz RTC crystal RTC operation Prescaler 32.768 kHz oscillator control unit 128 kHz RCR1 RCR2 Counter unit RCR3 Interr upt R64CNT control unit...
Page 827: Input/Output Pins
Section 22 Realtime Clock (RTC) 22.2 Input/Output Pins Table 22.1 shows the RTC pins. Table 22.1 RTC Pins Pin Name Abbreviation Function RTC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillator RTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillator Dedicated RTC power Vdd-RTC —...
Page 828: Register Descriptions
Section 22 Realtime Clock (RTC) 22.3 Register Descriptions Table 22.2 shows the RTC register configuration. Table 22.3 shows the register state in each operating mode. Table 22.2 Register Configuration Area P4 Area 7 Access Register Name Abbreviation R/W Address* Address* Size 64 Hz counter R64CNT...
Page 829: Table 22.3 Register State In Each Operating Mode
Section 22 Realtime Clock (RTC) Table 22.3 Register State in Each Operating Mode Abbrevia- Initial Power-On Manual Name tion Value Reset Reset Sleep Standby 64 Hz counter R64CNT Undefined Counts Counts Counts Counts Second counter RSECCNT Undefined Counts Counts Counts Counts Minute counter RMINCNT...
Page 830: Register Descriptions
Section 22 Realtime Clock (RTC) 22.4 Register Descriptions 22.4.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.
Page 831: Minute Counter (Rmincnt)
Section 22 Realtime Clock (RTC) 22.4.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter.
Page 832: Day-Of-Week Counter (Rwkcnt)
Section 22 Realtime Clock (RTC) 22.4.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter.
Page 833: Day Counter (Rdaycnt)
Section 22 Realtime Clock (RTC) 22.4.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter.
Page 834: Month Counter (Rmoncnt)
Section 22 Realtime Clock (RTC) 22.4.7 Month Counter (RMONCNT) RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded month value in the RTC. It counts on the carry generated once per month by the day counter.
Page 835: Second Alarm Register (Rsecar)
Section 22 Realtime Clock (RTC) 22.4.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value.
Page 836: Hour Alarm Register (Rhrar)
Section 22 Realtime Clock (RTC) 22.4.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value.
Page 837: Day Alarm Register (Rdayar)
Section 22 Realtime Clock (RTC) Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: — — — — Day-of-week code Initial value: — — —...
Page 838: Month Alarm Register (Rmonar)
Section 22 Realtime Clock (RTC) 22.4.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value.
Page 839 Section 22 Realtime Clock (RTC) Initial Bit Name Value Description Undefined R/W Carry Flag This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again.
Page 840: Rtc Control Register 2 (Rcr2)
Section 22 Realtime Clock (RTC) Initial Bit Name Value Description Undefined R/W Alarm Flag Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values.
Page 841 Section 22 Realtime Clock (RTC) Initial Bit Name Value Description Undefined R/W Periodic Interrupt Flag Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. 0: Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF...
Page 842 Section 22 Realtime Clock (RTC) Initial Bit Name Value Description 30-Second Adjustment Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute.
Page 843: Rtc Control Register (Rcr3) And Year-Alarm Register (Ryrar)
Section 22 Realtime Clock (RTC) 22.4.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC's BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value.
Page 844: Operation
Section 22 Realtime Clock (RTC) 22.5 Operation Examples of the use of the RTC are shown below. 22.5.1 Time Setting Procedures Figure 22.2 shows examples of the time setting procedures. Set RCR2.RESET to 1. Stop clock Clear RCR2.START to 0. Reset frequency divider Set second/minute/hour/day/ In any order.
Page 845: Time Reading Procedures
Section 22 Realtime Clock (RTC) 22.5.2 Time Reading Procedures Figure 22.3 shows examples of the time reading procedures. Clear RCR1.CIE to 0. Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag is not cleared).
Page 846: Alarm Function
Section 22 Realtime Clock (RTC) 22.5.3 Alarm Function The use of the alarm function is illustrated in figure 22.4. Clock running Clear RCR1.AIE to prevent erroneous interrupts. Disable alarm interrupts Set alarm time Clear alarm flag Be sure to reset the flag as it may have been set during alarm time setting.
Page 847: Interrupts
Section 22 Realtime Clock (RTC) 22.6 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1.
Page 848: Interrupt Source And Request Generating Order
Section 22 Realtime Clock (RTC) This LSI EXTAL2 XTAL2 VDD-RTC VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2.
Page 849: Section 23 Gigabit Ethernet Controller (Gether)
Section 23 Gigabit Ethernet Controller (GETHER) Section 23 Gigabit Ethernet Controller (GETHER) This LSI has an on-chip Gigabit Ethernet controller (GETHER) conforming to the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY- LSI) complying with this standard enables the GETHER to perform transmission and reception of Ethernet/IEEE802.3 frames.
Page 850: Figure 23.1 Configuration Of Gether
Section 23 Gigabit Ethernet Controller (GETHER) Transmit/receive FIFO (for transmission: 2 Kbytes, for reception: 8 Kbytes) Figure 23.1 shows the configuration of the GETHER. SuperHyway (SHwy) bridge bus GETHER E-DMAC0 E-DMAC1 DMA tansfer processing DMA transfer processing Descriptor access Descriptor access Receive FIFO Transmit FIFO Receive FIFO...
Page 851: Input/Output Pins
Section 23 Gigabit Ethernet Controller (GETHER) 23.2 Input/Output Pins Table 23.1 lists the pin configuration of the GETHER. Table 23.1 Pin Configuration Name Port Abbreviation Function Transmit clock ET0_TX-CLK Input ET0_TX-EN, ET0_ETXD3 to ET0_ETXD0, ET0_TX-ER timing reference signal Transmit enable ET0_TX-EN Output Indicates that transmit data is ready on...
Page 852 Section 23 Gigabit Ethernet Controller (GETHER) Name Port Abbreviation Function RMII RMII0_MDC Output Reference clock signal for information management transfer via RMII0_MDIO in RMII mode data clock RMII RMII0_MDIO Bidirectional signal for exchange of management management information between STA data I/O and PHY in RMII mode RMII RMII0M0_MDC...
Page 853 Section 23 Gigabit Ethernet Controller (GETHER) Name Port Abbreviation Function RMII transmit RMII0_TXD0 Output 2-bit transmit data in RMII mode data RMII transmit RMII0_TXD1 Output 2-bit transmit data in RMII mode data Transmit clock ET1_TX-CLK Input ET1_TX-EN, ET1_ETXD3 to ET1_ETXD0, ET1_TX-ER timing reference signal Receive clock ET1_RX-CLK...
Page 854 Section 23 Gigabit Ethernet Controller (GETHER) Name Port Abbreviation Function RMII RMII1_MDIO Bidirectional signal for exchange of management management information between STA data I/O and PHY in RMII mode Link status ET1_LINKSTA Input Inputs link status from PHY-LSI Wake-On-LAN ET1_WOL Output Signal indicating reception of Magic Packet...
Page 855 Section 23 Gigabit Ethernet Controller (GETHER) Name Port Abbreviation Function RMII transmit RMII1M_TXD0 Output 2-bit transmit data in RMII mode(mirror data (mirror pin) pin) RMII transmit RMII1_TXD1 Output 2-bit transmit data in RMII mode (mirror data (mirror pin) pin) 125-MHz Common REF125CK Input Transmit clock generation signal in GMII...
Page 856: Register Descriptions
Section 23 Gigabit Ethernet Controller (GETHER) 23.3 Register Descriptions Table 23.2 shows the configuration of registers of the GETHER. Table 23.3 shows the state of registers in each processing mode. The last number of the abbreviation of a register, except for registers related to the CAM entry tables, corresponds to the number of the two Ethernet interface ports (port 0 or port 1).
Page 857 Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Abbreviation Size Carrier extension error counter CEECR0 H'FEE0 0770 H'1EE0 0770 register Multicast address frame receive MAFCR0 H'FEE0 0778 H'1EE0 0778 counter register Automatic PAUSE frame register APR0 H'FEE0 0554 H'1EE0 0554...
Page 858 Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Abbreviation Size Residual-bit frame receive counter RFCR1 H'FEE0 0F60 H'1EE0 0F60 register CERCR1 H'FEE0 0F68 H'1EE0 0F68 Carrier extension loss counter register Carrier extension error counter CEECR1 H'FEE0 0F70 H'1EE0 0F70...
Page 859 Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Abbreviation Size H'FEE0 1838 H'1EE0 1838 Relay function set register (common) TSU_FWSLC Qtag addition/deletion set register TSU_QTAG0 R/W H'FEE0 1840 H'1EE0 1840 (port 0 to 1) Qtag addition/deletion set register TSU_QTAG1 R/W H'FEE0 1844...
Page 860 Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Abbreviation Size CAM entry table 13H register H'FEE0 1968 H'1EE0 1968 TSU_ADRH13 CAM entry table 14H register H'FEE0 1970 H'1EE0 1970 TSU_ADRH14 CAM entry table 15H register H'FEE0 1978 H'1EE0 1978 TSU_ADRH15...
Page 861 Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Abbreviation Size CAM entry table 12L register H'FEE0 1964 H'1EE0 1964 TSU_ADRL12 CAM entry table 13L register H'FEE0 196C H'1EE0 196C TSU_ADRL13 CAM entry table 14L register H'FEE0 1974 H'1EE0 1974 TSU_ADRL14...
Page 862 Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Abbreviation Size TXNLCR1 H'FEE0 18A0 H'1EE0 18A0 Transmit frame counter register (port 1) (normal transmission only) Transmit frame counter register TXALCR1 H'FEE0 18A4 H'1EE0 18A4 (port 1) (normal and erroneous transmission) Receive frame counter register RXNLCR1...
Page 863 Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Size Abbreviation RDFFR0 H'FEE0 003C H'1EE0 003C Receive descriptor final flag register Transmit descriptor fetch address TDFAR0 H'FEE0 0014 H'1EE0 0014 register Transmit descriptor finished TDFXR0 H'FEE0 0018 H'1EE0 0018 address register...
Page 864: Table 23.3 Register States In Each Operating Mode
Section 23 Gigabit Ethernet Controller (GETHER) P4 Area Area 7 Access Name Address Address Abbreviation Size TDFXR1 H'FEE0 0818 H'1EE0 0818 Transmit descriptor finished address register TDFFR1 H'FEE0 081C H'1EE0 081C Transmit descriptor final flag register FCFTR1 H'FEE0 0C68 H'1EE0 0C68 Overflow alert FIFO threshold register RPADIR1 H'FEE0 0C60...
Page 865 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation Automatic PAUSE frame register APR0 Retained Retained H'00000000 H'00000000 Manual PAUSE frame register MPR0 Retained Retained H'00000000 H'00000000 Automatic PAUSE frame retransmit TPAUSER0 Retained Retained H'00000000 H'00000000 count register PFTCR0 Retained Retained...
Page 866 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation Automatic PAUSE frame retransmit TPAUSER1 Retained Retained H'00000000 H'00000000 count register PFTCR1 Retained Retained PAUSE frame transmit counter register H'00000000 H'00000000 PFRCR1 Retained Retained PAUSE frame receive counter register H'00000000 H'00000000 GETHER mode register GECMR1...
Page 867 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation CAM entry table busy register TSU_ Retained Retained H'00000000 H'00000000 ADSBSY CAM entry table enable register TSU_TEN Retained Retained H'00000000 H'00000000 CAM entry table POST1 register Retained Retained TSU_POST1 H'00000000 H'00000000...
Page 868 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation CAM entry table 18H register TSU_ Retained Retained H'00000000 H'00000000 ADRH18 CAM entry table 19H register TSU_ Retained Retained H'00000000 H'00000000 ADRH19 CAM entry table 20H register TSU_ Retained Retained H'00000000 H'00000000...
Page 869 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation CAM entry table 7L register Retained Retained TSU_ADRL7 H'00000000 H'00000000 CAM entry table 8L register Retained Retained TSU_ADRL8 H'00000000 H'00000000 CAM entry table 9L register Retained Retained TSU_ADRL9 H'00000000 H'00000000 CAM entry table 10L register TSU_...
Page 870 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation CAM entry table 24L register TSU_ Retained Retained H'00000000 H'00000000 ADRL24 CAM entry table 25L register TSU_ Retained Retained H'00000000 H'00000000 ADRL25 CAM entry table 26L register TSU_ Retained Retained H'00000000 H'00000000...
Page 871 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation Relay frame counter register (port 0 FWNLCR1 Retained Retained H'00000000 H'00000000 to 1) (normal relay only) Relay frame counter register (port 0 FWALCR1 Retained Retained H'00000000 H'00000000 to 1) (normal and erroneous relay) E-DMAC start register EDSR0...
Page 872 Section 23 Gigabit Ethernet Controller (GETHER) Power-On Manual Name Reset Reset Sleep Standby Abbreviation E-DMAC transmit request register EDTRR1 Retained Retained H'00000000 H'00000000 E-DMAC receive request register EDRRR1 Retained Retained H'00000000 H'00000000 Transmit descriptor list start address TDLAR1 Retained Retained H'00000000 H'00000000 register Receive descriptor list start address...
Page 873: Software Reset Register (Arstr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.1 Software Reset Register (ARSTR) ARSTR resets all blocks (E-MAC, TSU, and E-DMAC) in the GETHER. By writing 1 to the ARST bit in this register, a software reset is issued to all blocks of the GETHER (for 256 cycles of external bus clock Bck).
Page 874: E-Mac Mode Register (Ecmr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.2 E-MAC Mode Register (ECMR) ECMR is a 32-bit readable/writable register that specifies the operating mode of the GETHER. The settings in this register are normally made in the initialization process following a reset. The operating mode setting must not be changed while the transmitting and receiving functions are enabled.
Page 875 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RCSC Checksum Calculation Specifies whether to perform automatic calculation (hardware calculation) of the checksum of the receive frame data unit. 0: Checksum is not automatically calculated 1: Checksum is automatically calculated Note that the checksum calculation of a frame with a VLAN tag is not supported.
Page 876 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description PAUSE Frame Usage with TIME = 0 Enable/Lost Carrier Error Detection Enable. PAUSE Frame Usage with TIME = 0 Enable (In full- duplex mode) 0: Control of a PAUSE frame whose TIME parameter value is 0 is disabled.
Page 877 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description Operating Mode for Receiving Port Flow Control 0: PAUSE frame detection is disabled 1: Flow control for the receiving port is enabled Operating Mode for Transmitting Port Flow Control 0: Flow control for the transmitting port is disabled (Automatic PAUSE frame is not transmitted) 1: Flow control for the transmitting port is enabled...
Page 878 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description Reception Enable If a switch is made from receiving function enabled (RE = 1) to disabled (RE = 0) while a frame is being received, the receiving function will be enabled until reception of the corresponding frame is completed.
Page 879 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description Promiscuous Mode Setting this bit enables all Ethernet frames to be received. All Ethernet frames means all receivable frames, irrespective of differences or enabled/disabled status (destination address, broadcast address, multicast bit, etc.).
Page 880: E-Mac Status Register (Ecsr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.3 E-MAC Status Register (ECSR) ECSR is a 32-bit readable/writable register that indicates the status in the E-MAC. This status can be notified to the CPU by interrupts. When 1 is written to the PFROI, LCHNG, MPD, and ICD bits, the corresponding flags can be cleared.
Page 881 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description PHYI ET_PHY-INT Interrupt Indicates the state of the ET_PHY-INT pin input from the PHY-LSI. 0: ET_PHY-INT pin is not asserted 1: ET_PHY-INT pin is asserted The signal polarity of the ET_PHY-INT pin can be set by PIPR.
Page 882: E-Mac Interrupt Permission Register (Ecsipr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.4 E-MAC Interrupt Permission Register (ECSIPR) ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR. Bit: ...
Page 883: Phy Interface Register (Pir)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.5 PHY Interface Register (PIR) PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI internal registers via the GMII/MII/RMII. Bit:          ...
Page 884: Mac Address High Register (Mahr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.6 MAC Address High Register (MAHR) MAHR is a 32-bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled.
Page 885: Mac Address Low Register (Malr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.7 MAC Address Low Register (MALR) MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled.
Page 886: Receive Frame Length Register (Rflr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.8 Receive Frame Length Register (RFLR) RFLR is a 32-bit readable/writable register that specifies the maximum frame length (in bytes) that can be received by this LSI. The settings in this register must not be changed while the receiving function is enabled.
Page 887: Phy Status Register (Psr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.9 PHY Status Register (PSR) PSR is a read-only register that can read interface signals from the PHY-LSI. Bit:                ...
Page 888: Phy_Int Polarity Register (Pipr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.10 PHY_INT Polarity Register (PIPR) PIPR is used to set the polarity of the ET_PHY-INT pin. Bit:                 Initial value: R/W: Bit: ...
Page 889: Transmit Retry Over Counter Register (Trocr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.11 Transmit Retry Over Counter Register (TROCR) TROCR is a 16-bit counter that indicates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed, this register is incremented by 1.
Page 890: Delayed Collision Detect Counter Register (Cdcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.12 Delayed Collision Detect Counter Register (CDCR) CDCR is a 16-bit counter that indicates the number of all delayed collisions that occurred on the line after the start of data transmission. When the value in this register reaches H'0000FFFF, count-up is halted.
Page 891: Lost Carrier Counter Register (Lccr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.13 Lost Carrier Counter Register (LCCR) LCCR is a 16-bit counter that indicates the number of times the carrier was lost during data transmission. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1.
Page 892: Crc Error Frame Receive Counter Register (Cefcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.14 CRC Error Frame Receive Counter Register (CEFCR) CEFCR is a 16-bit counter that indicates the number of times a frame with a CRC error was received. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1.
Page 893: Frame Receive Error Counter Register (Frecr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.15 Frame Receive Error Counter Register (FRECR) FRECR is a 16-bit counter that indicates the number of frames for which a receive error was generated by the ET_RX-ER pin input from the PHY-LSI. FRECR is incremented each time the ET_RX-ER pin becomes active.
Page 894: Too-Short Frame Receive Counter Register (Tsfrcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.16 Too-Short Frame Receive Counter Register (TSFRCR) TSFRCR is a 16-bit counter that indicates the number of frames received with a length fewer than 64 bytes. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1.
Page 895: Too-Long Frame Receive Counter Register (Tlfrcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.17 Too-Long Frame Receive Counter Register (TLFRCR) TLFRCR is a 16-bit counter that indicates the number of frames received with a length exceeding the value specified by the receive frame length register (RFLR). When the value in this register reaches H'0000FFFF, count-up is halted.
Page 896: Residual-Bit Frame Receive Counter Register (Rfcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.18 Residual-Bit Frame Receive Counter Register (RFCR) RFCR is a 16-bit counter that indicates the number of frames received containing residual bits (less than an 8-bit unit). When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1.
Page 897: Carrier Extension Loss Counter Register (Cercr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.19 Carrier Extension Loss Counter Register (CERCR) CERCR is a 16-bit counter that indicates the number of frames received with the carrier extension lost. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1.
Page 898: Carrier Extension Error Counter Register (Ceecr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.20 Carrier Extension Error Counter Register (CEECR) CEECR is a 16-bit counter that indicates the number of frames received with an illegal carrier extension. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1.
Page 899: Multicast Address Frame Receive Counter Register (Mafcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.21 Multicast Address Frame Receive Counter Register (MAFCR) MAFCR is a 16-bit counter that indicates the number of frames received with a specified multicast address. When the value in this register reaches H'0000FFFF, count-up is halted. This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1.
Page 900: Automatic Pause Frame Register (Apr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.22 Automatic PAUSE Frame Register (APR) APR is used to set the TIME parameter value of an automatic PAUSE frame. When an automatic PAUSE frame is transmitted, the value set in this register is used as the TIME parameter of the PAUSE frame.
Page 901: Manual Pause Frame Register (Mpr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.23 Manual PAUSE Frame Register (MPR) MPR is used to set the TIME parameter value of a manual PAUSE frame. When a manual PAUSE frame is transmitted, the value set in this register is used as the TIME parameter of the PAUSE frame.
Page 902: Automatic Pause Frame Retransmit Count Register (Tpauser)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.24 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) TPAUSER is used to set the upper limit for the number of times to retransmit an automatic PAUSE frame. The settings in this register must not be changed while the transmitting function is enabled.
Page 903: Pause Frame Transmit Counter Register (Pftcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.25 PAUSE Frame Transmit Counter Register (PFTCR) PFTCR is a 16-bit counter that indicates the number of times a PAUSE frame is transmitted. This register is cleared to 0 when it is read. Bit: ...
Page 904: Pause Frame Receive Counter Register (Pfrcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.26 PAUSE Frame Receive Counter Register (PFRCR) PFRCR is a 16-bit counter that indicates the number of times a PAUSE frame is received. This register is cleared to 0 when it is read. Bit: ...
Page 905: Gether Mode Register (Gecmr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.27 GETHER Mode Register (GECMR) GECMR is used to set the operating mode of the GETHER. Bit:                 Initial value: R/W: Bit: SPEED...
Page 906: Burst Cycle Count Upper-Limit Register (Bculr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.28 Burst Cycle Count Upper-Limit Register (BCULR) BCULR sets the upper limit for the number of burst cycles. Bit:                ...
Page 907: Tsu Counter Reset Register (Tsu_Ctrst)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.29 TSU Counter Reset Register (TSU_CTRST) TSU_CTRST clears the transmit, receive, and relay frame counters to 0. Bit:                 Initial value: R/W: Bit:...
Page 908: Relay Enable Register (Port 0 To 1) (Tsu_Fwen0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.30 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) TSU_FWEN0 enables or disables relay operations from the E-MAC-0 to E-MAC-1 (writing to the relay FIFO). Bit:         ...
Page 909: Relay Enable Register (Port 1 To 0) (Tsu_Fwen1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.31 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) TSU_FWEN1 enables or disables relay operations from the E-MAC-1 to E-MAC-0 (writing to the relay FIFO). Bit:         ...
Page 910: Relay Fifo Size Select Register (Tsu_Fcm)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.32 Relay FIFO Size Select Register (TSU_FCM) TSU_FCM selects the size of the relay FIFO in the TSU, used for relay operations between the E- MAC-0 and E-MAC-1. Bit:      ...
Page 911: Relay Fifo Overflow Alert Set Register (Port 0) (Tsu_Bsysl0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.33 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) The TSU has an alert function, which informs the E-MAC-0 and E-MAC-1 that writing to the relay FIFO will be disabled when the data volume written in the relay FIFO during relay operations exceeds a certain threshold.
Page 912 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description 5 to 0 BSYSL0[5:0] 111111 These bits set the threshold of the port 0-to-1 relay FIFO size in 256-byte units when the TSU alerts the E- MAC-0 that writing in the relay FIFO will be disabled during relay operations.
Page 913: Relay Fifo Overflow Alert Set Register (Port 1) (Tsu_Bsysl1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.34 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) The TSU has an alert function, which informs the E-MAC-0 and E-MAC-1 that writing to the relay FIFO will be disabled when the data volume written in the relay FIFO during relay operations exceeds a certain threshold.
Page 914 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description 5 to 0 BSYSL1[5:0] All 1 These bits set the threshold of the port 1-to-0 relay FIFO size in 256-byte units when the TSU alerts the E- MAC-1 that writing in the relay FIFO will be disabled during relay operations.
Page 915: Transmit/Relay Priority Control Mode Register (Port 0) (Tsu_Prisl0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.35 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0) TSU_PRISL0 sets the priority control mode when the transmission request from the E-DMAC to E-MAC-0 comes into collision with port 1 to 0 relay operations. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Page 916 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description 7 to 0 PRISL0[7:0] All 0 These bits set the threshold of the port 1-to-0 relay FIFO size in 64-byte units in the event of switching to relay priority when bits PRIMD0[2:0] are set to H'4 or H'5.
Page 917: Transmit/Relay Priority Control Mode Register (Port 1) (Tsu_Prisl1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.36 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1) TSU_PRISL1 sets the priority control mode when the transmission request from the E-DMAC to E-MAC-1 comes into collision with port 0 to 1 relay operations. This register must not be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Page 918 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description 7 to 0 PRISL1[7:0] All 0 These bits set the threshold of the port 0-to-1 relay FIFO size in 64-byte units in the event of switching to relay priority when bits PRIMD1[2:0] are set to H'4 or H'5.
Page 919: Receive/Relay Function Set Register (Port 0 To 1) (Tsu_Fwsl0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.37 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0) TSU_FWSL0 sets the processing method (enable or disable relay operation) of each frame in port 0 reception and port 0 to 1 relay operations. For multicast frames and frames whose destinations are other than this LSI, the processing method in relay operations can be determined by referring to the CAM evaluation results.
Page 920 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description FW20 Sets the processing method when frames from port 0 are multicast frames. 0: CAM hit: Frames are relayed to port 1 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 1 FW10 Sets the processing method when frames from port 0...
Page 921: Receive/Relay Function Set Register (Port 1 To 0) (Tsu_Fwsl1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.38 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1) TSU_FWSL1 sets the processing method (enable or disable relay operation) of each frame in port 1 reception and port 1 to 0 relay operations. For multicast frames and frames whose destinations are other than this LSI, the processing method in relay operations can be determined by referring to the CAM evaluation results.
Page 922 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description FW21 Sets the processing method when frames from port 1 are multicast frames. 0: CAM hit: Frames are relayed to port 0 CAM mishit: Frames are not relayed 1: CAM hit: Frames are not relayed CAM mishit: Frames are relayed to port 0 FW11 Sets the processing method when frames from port 1...
Page 923: Relay Function Set Register (Common) (Tsu_Fwslc)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.39 Relay Function Set Register (Common) (TSU_FWSLC) When the CAM is used, the referred area in the CAM entry table (partially or wholly) can be specified by the TSU_POST1 to TSU_POST4 registers. TSU_FWSLC enables settings by the TSU_POST1 to TSU_POST4 registers.
Page 924 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description  11 to 0 All 0 Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Oct. 01, 2007 Page 858 of 1956 REJ09B0256-0100...
Page 925: Qtag Addition/Deletion Set Register (Port 0 To 1) (Tsu_Qtag0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.40 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAG0) TSU_QTAG0 sets the functions adding Qtag to the normal Ethernet frames (no Qtag) to convert them into IEEE802.1Q frames (with Qtag) and deleting Qtag from IEEE802.1Q frames (with Qtag) to convert them into normal Ethernet frames (no Qtag) during port 0 to 1 relay operations.
Page 926: Qtag Addition/Deletion Set Register (Port 1 To 0) (Tsu_Qtag1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.41 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAG1) TSU_QTAG1 sets the functions adding Qtag to the normal Ethernet frames (no Qtag) to convert them into IEEE802.1Q frames (with Qtag) and deleting Qtag from IEEE802.1Q frames (with Qtag) to convert them into normal Ethernet frames (no Qtag) during port 1 to 0 relay operations.
Page 927: Relay Status Register (Tsu_Fwsr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.42 Relay Status Register (TSU_FWSR) TSU_FWSR is a 32-bit readable/writable register that indicates the status during relay operations. By setting the relay status interrupt mask register (TSU_FWINMK), this status can be notified to the CPU as an interrupt source. The status bit set to 1 will be cleared to 0 by writing 1 to the corresponding bit.
Page 928 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RINT50 E-MAC-0 Residual-Bit Frame Receive Set to 1 when a frame containing residual bits (less than an 8-bit unit) is received in the E-MAC-0. RINT40 E-MAC-0 Too-Long Frame Receive Set to 1 when a frame exceeding the value set by RFLR0 is received in the E-MAC-0.
Page 929 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RINT31 E-MAC-1 Too-Short Frame Receive Set to 1 when a frame with a length of less than 64 bytes is received in the E-MAC-1. RINT21 E-MAC-1 Frame Receive Error Set to 1 when a receive error is detected on the ET1_RX-ER pin input from the PHY-LSI in the E-MAC- RINT11...
Page 930: Relay Status Interrupt Mask Register (Tsu_Fwinmk)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.43 Relay Status Interrupt Mask Register (TSU_FWINMK) TSU_FWINMK is a 32-bit readable/writable register that sets the interrupt mask for status bits in TSU_FWSR. Bit: OVFM RBSYM RINTM RINTM RINTM RINTM RINTM RINTM   ...
Page 931 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RINTM30 E-MAC-0 Too-Short Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled RINTM20 E-MAC-0 Frame Receive Error Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled RINTM10 E-MAC-0 CRC Error Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled ...
Page 932 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RINTM21 E-MAC-1 Frame Receive Error Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled RINTM11 E-MAC-1 CRC Error Frame Receive Interrupt Mask 0: Interrupts disabled 1: Interrupts enabled Rev. 1.00 Oct. 01, 2007 Page 866 of 1956 REJ09B0256-0100...
Page 933: Added Qtag Value Set Register (Port 0 To 1) (Tsu_Adqt0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0) TSU_ADQT0 sets the Qtag data to be added in the conversion of normal Ethernet frames (no Qtag) to IEEE802.1Q frames (with Qtag) in port 0 to 1 relay operations (if bits QTAG0[2:0] in TSU_QTAG0 are set to H'3 or H'7 when using the Qtag adding function).
Page 934: Added Qtag Value Set Register (Port 1 To 0) (Tsu_Adqt1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.45 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1) TSU_ADQT1 sets the Qtag data to be added in the conversion of normal Ethernet frames (no Qtag) to IEEE802.1Q frames (with Qtag) in port 1 to 0 relay operations (if bits QTAG1[2:0] in TSU_QTAG1 are set to H'3 or H'7 when using the Qtag adding function).
Page 935: Vlantag Set Register (Port 0) (Tsu_Vtag0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.46 VLANtag Set Register (Port 0) (TSU_VTAG0) TSU_VTAG0 enables or disables the frame receive/discard evaluation function based on the VLAN number in port 0 relay operations, and also sets the VLAN number. Bit: VTAG ...
Page 936: Vlantag Set Register (Port 1) (Tsu_Vtag1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.47 VLANtag Set Register (Port 1) (TSU_VTAG1) TSU_VTAG1 enables or disables the frame receive/discard evaluation function based on the VLAN number in port 1 relay operations, and also sets the VLAN number. Bit: VTAG ...
Page 937: Cam Entry Table Busy Register (Tsu_Adsbsy)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.48 CAM Entry Table Busy Register (TSU_ADSBSY) When CAM entry table registers (TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31) are set by register writing, the ADSBSY bit in this register is set to 1 (when the process of reflecting the contents of the CAM entry table registers in the CAM controller is completed inside the TSU, the ADSBSY bit is automatically restored to 0).
Page 938: Cam Entry Table Enable Register (Tsu_Ten)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.49 CAM Entry Table Enable Register (TSU_TEN) TSU_TEN enables or disables the settings of TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31. Bit: TEN0 TEN1 TEN2 TEN3 TEN4 TEN5 TEN6 TEN7 TEN8 TEN9 TEN10 TEN11 TEN12 TEN13 TEN14 TEN15 Initial value: R/W: Bit:...
Page 939 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description TEN5 CAM Entry Table 5 (TSU_ADRH5 and TSU_ADRL5) Setting 0: Disabled 1: Enabled TEN6 CAM Entry Table 6 (TSU_ADRH6 and TSU_ADRL6) Setting 0: Disabled 1: Enabled TEN7 CAM Entry Table 7 (TSU_ADRH7 and TSU_ADRL7) Setting 0: Disabled 1: Enabled...
Page 940 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description TEN13 CAM Entry Table 13 (TSU_ADRH13 and TSU_ADRL13) Setting 0: Disabled 1: Enabled TEN14 CAM Entry Table 14 (TSU_ADRH14 and TSU_ADRL14) Setting 0: Disabled 1: Enabled TEN15 CAM Entry Table 15 (TSU_ADRH15 and TSU_ADRL15) Setting 0: Disabled 1: Enabled...
Page 941 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description TEN21 CAM Entry Table 21 (TSU_ADRH21 and TSU_ADRL21) Setting 0: Disabled 1: Enabled TEN22 CAM Entry Table 22 (TSU_ADRH22 and TSU_ADRL22) Setting 0: Disabled 1: Enabled TEN23 CAM Entry Table 23 (TSU_ADRH23 and TSU_ADRL23) Setting 0: Disabled 1: Enabled...
Page 942 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description TEN29 CAM Entry Table 29 (TSU_ADRH29 and TSU_ADRL29) Setting 0: Disabled 1: Enabled TEN30 CAM Entry Table 30 (TSU_ADRH30 and TSU_ADRL30) Setting 0: Disabled 1: Enabled TEN31 CAM Entry Table 31 (TSU_ADRH31 and TSU_ADRL31) Setting 0: Disabled 1: Enabled...
Page 943: Cam Entry Table Post1 Register (Tsu_Post1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.50 CAM Entry Table POST1 Register (TSU_POST1) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST1 specifies the conditions for referring to TSU_ADRH0 to TSU_ADRH7 and TSU_ADRL0 to TSU_ADRL7.
Page 944 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 23 to 20 POST2[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 2. By setting multiple bits to 1, multiple conditions can be selected. POST2[3]: CAM entry table 2 is referred to in port 0 reception.
Page 945 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 11 to 8 POST5[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 5. By setting multiple bits to 1, multiple conditions can be selected. POST5[3]: CAM entry table 5 is referred to in port 0 reception.
Page 946: Cam Entry Table Post2 Register (Tsu_Post2)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.51 CAM Entry Table POST2 Register (TSU_POST2) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST2 specifies the conditions for referring to TSU_ADRH8 to TSU_ADRH15 and TSU_ADRL8 to TSU_ADRL15.
Page 947 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 23 to 20 POST10[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 10. By setting multiple bits to 1, multiple conditions can be selected. POST10[3]: CAM entry table 10 is referred to in port 0 reception.
Page 948 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 11 to 8 POST13[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 13. By setting multiple bits to 1, multiple conditions can be selected. POST13[3]: CAM entry table 13 is referred to in port 0 reception.
Page 949: Cam Entry Table Post3 Register (Tsu_Post3)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.52 CAM Entry Table POST3 Register (TSU_POST3) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST3 specifies the conditions for referring to TSU_ADRH16 to TSU_ADRH23 and TSU_ADRL16 to TSU_ADRL23.
Page 950 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 23 to 20 POST18[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 18. By setting multiple bits to 1, multiple conditions can be selected. POST18[3]: CAM entry table 18 is referred to in port 0 reception.
Page 951 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 11 to 8 POST21[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 21. By setting multiple bits to 1, multiple conditions can be selected. POST21[3]: CAM entry table 21 is referred to in port 0 reception.
Page 952: Cam Entry Table Post4 Register (Tsu_Post4)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.53 CAM Entry Table POST4 Register (TSU_POST4) When using the CAM, the conditions for referring to each CAM entry table can be specified by using the TSU_POST1 to TSU_POST4 registers. TSU_POST4 specifies the conditions for referring to TSU_ADRH24 to TSU_ADRH31 and TSU_ADRL24 to TSU_ADRL31.
Page 953 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 23 to 20 POST26[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 26. By setting multiple bits to 1, multiple conditions can be selected. POST26[3]: CAM entry table 26 is referred to in port 0 reception.
Page 954 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value R/W Description 11 to 8 POST29[3:0] All 0 R/W These bits set the conditions for referring to CAM entry table 29. By setting multiple bits to 1, multiple conditions can be selected. POST29[3]: CAM entry table 29 is referred to in port 0 reception.
Page 955: Cam Entry Table 0H To 31H Registers (Tsu_Adrh0 To Tsu_Adrh31)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.54 CAM Entry Table 0H to 31H Registers (TSU_ADRH0 to TSU_ADRH31) TSU_ADRH0 to TSU_ADRH31 are entry tables referred to by the CAM in reception and relay. Each of these registers sets the upper 32 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses can be registered.
Page 956: Cam Entry Table 0L To 31L Registers (Tsu_Adrl0 To Tsu_Adrl31)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.55 CAM Entry Table 0L to 31L Registers (TSU_ADRL0 to TSU_ADRL31) TSU_ADRL0 to TSU_ADRL31 are entry tables referred to by the CAM in reception and relay. Each of these registers sets the lower 16 bits of the 48-bit MAC address. Maximum 32 entries of MAC addresses can be registered.
Page 957: Transmit Frame Counter Register (Port 0) (Normal Transmission Only)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.56 Transmit Frame Counter Register (Port 0) (Normal Transmission Only) (TXNLCR0) TXNLCR0 is a 32-bit counter indicating the number of frames successfully transmitted in the E- MAC-0. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register.
Page 958: Transmit Frame Counter Register (Port 0) (Normal And Erroneous Transmission) (Txalcr0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.57 Transmit Frame Counter Register (Port 0) (Normal and Erroneous Transmission) (TXALCR0) TXALCR0 is a 32-bit counter indicating the number of frames transmitted in the E-MAC-0, including the number of frames erroneously transmitted. When the value in this register reaches H'FFFFFFFF, count-up is halted.
Page 959: Receive Frame Counter Register (Port 0) (Normal Reception Only) (Rxnlcr0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.58 Receive Frame Counter Register (Port 0) (Normal Reception Only) (RXNLCR0) RXNLCR0 is a 32-bit counter indicating the number of frames successfully received in the E- MAC-0. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register.
Page 960: Receive Frame Counter Register (Port 0) (Normal And Erroneous Reception)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.59 Receive Frame Counter Register (Port 0) (Normal and Erroneous Reception) (RXALCR0) RXALCR0 is a 32-bit counter indicating the number of frames received in the E-MAC-0, including the number of frames erroneously received. When the value in this register reaches H'FFFFFFFF, count-up is halted.
Page 961: Relay Frame Counter Register (Port 1 To 0) (Normal Relay Only)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.60 Relay Frame Counter Register (Port 1 to 0) (Normal Relay Only) (FWNLCR0) FWNLCR0 is a 32-bit counter indicating the number of frames successfully relayed in port 1 to 0 relay operations. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register.
Page 962: Relay Frame Counter Register (Port 1 To 0) (Normal And Erroneous Transmission) (Fwalcr0)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.61 Relay Frame Counter Register (Port 1 to 0) (Normal and Erroneous Transmission) (FWALCR0) FWALCR0 is a 32-bit counter indicating the number of frames relayed in port 1 to 0 relay operations, including the number of frames erroneously relayed. When the value in this register reaches H'FFFFFFFF, count-up is halted.
Page 963: Transmit Frame Counter Register (Port 1) (Normal Transmission Only) (Txnlcr1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.62 Transmit Frame Counter Register (Port 1) (Normal Transmission Only) (TXNLCR1) TXNLCR1 is a 32-bit counter indicating the number of frames successfully transmitted in the E- MAC-1. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register.
Page 964: Transmit Frame Counter Register (Port 1) (Normal And Erroneous Transmission) (Txalcr1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.63 Transmit Frame Counter Register (Port 1) (Normal and Erroneous Transmission) (TXALCR1) TXALCR1 is a 32-bit counter indicating the number of frames transmitted in the E-MAC-1, including the number of frames erroneously transmitted. When the value in this register reaches H'FFFFFFFF, count-up is halted.
Page 965: Receive Frame Counter Register (Port 1) (Normal Reception Only) (Rxnlcr1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.64 Receive Frame Counter Register (Port 1) (Normal Reception Only) (RXNLCR1) RXNLCR1 is a 32-bit counter indicating the number of frames successfully received in the E- MAC-1. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register.
Page 966: Receive Frame Counter Register (Port 1) (Normal And Erroneous Reception) (Rxalcr1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.65 Receive Frame Counter Register (Port 1) (Normal and Erroneous Reception) (RXALCR1) RXALCR1 is a 32-bit counter indicating the number of frames received in the E-MAC-1, including the number of frames erroneously received. When the value in this register reaches H'FFFFFFFF, count-up is halted.
Page 967: Relay Frame Counter Register (Port 0 To 1) (Normal Relay Only) (Fwnlcr1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.66 Relay Frame Counter Register (Port 0 to 1) (Normal Relay Only) (FWNLCR1) FWNLCR1 is a 32-bit counter indicating the number of frames successfully relayed in port 0 to 1 relay operations. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter is cleared to 0 by reading from this register.
Page 968: Relay Frame Counter Register (Port 0 To 1) (Normal And Erroneous Transmission) (Fwalcr1)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.67 Relay Frame Counter Register (Port 0 to 1) (Normal and Erroneous Transmission) (FWALCR1) FWALCR1 is a 32-bit counter indicating the number of frames relayed in port 0 to 1 relay operations, including the number of frames erroneously relayed. When the value in this register reaches H'FFFFFFFF, count-up is halted.
Page 969: E-Dmac Start Register (Edsr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.68 E-DMAC Start Register (EDSR) EDSR specifies activation of the transmitting unit and receiving unit of the E-DMAC. This register can only be written to, and the read values are invalid. Bit:   ...
Page 970: E-Dmac Mode Register (Edmr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.69 E-DMAC Mode Register (EDMR) EDMR is a 32-bit readable/writable register that specifies E-DMAC resetting and the transmit/receive descriptor length. This register is to be set before the transmitting or receiving function is enabled (before the TR bit in EDTRR or the RR bit in EDRRR is set to 1). However, the SWRR and SWRT bits can be written to even after the transmitting or receiving function is enabled.
Page 971 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description  31 to 7 All 0 Reserved These bits are always read as 0. The write value should always be 0. Transmit/Receive Frame Endian Sets the endian mode for DMA transfer of frame data between the transmit/receive FIFO and transmit/receive buffer.
Page 972: E-Dmac Transmit Request Register (Edtrr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.70 E-DMAC Transmit Request Register (EDTRR) EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After writing 11 to bits TR[1:0] in this register, the E-DMAC reads the transmit descriptor at the address specified by TDLAR.
Page 973: E-Dmac Receive Request Register (Edrrr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.71 E-DMAC Receive Request Register (EDRRR) EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. After writing 1 to the RR bit in this register, the E-DMAC reads the receive descriptor at the address specified by RDLAR.
Page 974: Transmit Descriptor List Start Address Register (Tdlar)
Section 23 Gigabit Ethernet Controller (GETHER) Note: If the receiving function is disabled during frame reception, write-back is not performed successfully to the receive descriptor. Following pointers to read a receive descriptor become abnormal and the E-DMAC cannot operate successfully. In this case, to make E-DMAC reception enabled again, execute a software reset by the SWRT and SWRR bits in EDMR0 (EDMR1).
Page 975: Receive Descriptor List Start Address Register (Rdlar)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.73 Receive Descriptor List Start Address Register (RDLAR) RDLAR is a 32-bit readable/writable register that specifies the start address of the receive descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bits in EDMR.
Page 976: E-Mac/E-Dmac Status Register (Eesr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.74 E-MAC/E-DMAC Status Register (EESR) EESR is a 32-bit readable/writable register that shows communications status information on the E-DMAC in combination with the E-MAC. The information in this register is reported in the form of interrupt sources.
Page 977 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description TC[1] Frame Transmission Complete Indicates, in combination with the TC[0] bit, that all the data specified by the transmit descriptor has been transmitted from the E-MAC. This bit is set to 1 on assuming the completion of transmission.
Page 978 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RABT Receive Abort Detect Indicates that the E-MAC aborts receiving a frame because of failures during frame reception. 0: Frame reception has not been aborted or no reception directive 1: Frame reception has been aborted RFCOF Receive Frame Counter Overflow...
Page 979 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description Transmit Descriptor Empty Indicates that the transmit descriptor valid bit (TACT) of a transmit descriptor read by the E-DMAC is not set if the previous descriptor does not represent the end of a frame in multi-buffer frame processing based on single- frame/multi-descriptor operation.
Page 980 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RFOF Receive FIFO Overflow Indicates that the receive FIFO has overflowed during frame reception. 0: Overflow has not occurred 1: Overflow has occurred  15 to 11 All 0 Reserved These bits are always read as 0.
Page 981 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description CELF Carrier Extension Loss Indicates that the carrier extension has been lost in 1- Gigabit/half-duplex transfer. This means that the sum of a frame and carrier extension is smaller than SLOT_TIME (4096 bits).
Page 982: E-Mac/E-Dmac Status Interrupt Permission Register (Eesipr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.75 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR) EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the E-MAC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the corresponding bit.
Page 983 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description ROCIP Receive Overflow Frame Write-Back Complete Interrupt Enable 0: Receive overflow frame write-back complete interrupt is disabled 1: Receive overflow frame write-back complete interrupt is enabled TABTIP Transmit Abort Detect Interrupt Enable 0: Transmit abort detect interrupt is disabled 1: Transmit abort detect interrupt is enabled RABTIP...
Page 984 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RDEIP Receive Descriptor Empty Interrupt Enable 0: Receive descriptor empty interrupt is disabled 1: Receive descriptor empty interrupt is enabled RFOFIP Receive FIFO Overflow Interrupt Enable 0: Overflow interrupt is disabled 1: Overflow interrupt is enabled ...
Page 985 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RTLFIP Receive Too-Long Frame Interrupt Enable 0: Receive too-long frame interrupt is disabled 1: Receive too-long frame interrupt is enabled RTSFIP Receive Too-Short Frame Interrupt Enable 0: Receive too-short frame interrupt is disabled 1: Receive too-short frame interrupt is enabled PREIP PHY-LSI Receive Error Interrupt Enable...
Page 986: Transmit/Receive Status Copy Enable Register (Trscer)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.76 Transmit/Receive Status Copy Enable Register (TRSCER) TRSCER specifies whether the information for the transmit and receive state reported by bits 17, 16, and 10 to 0 in the E-MAC/E-DMAC status register (EESR) is to be reflected in the TFE or RFE bit of the corresponding descriptor.
Page 987 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description  15 to 11 All 0 Reserved These bits are always read as 0. The write value should always be 0. DLCCE DLC Bit Copy Directive 0: Reflects the DLC bit status in the TFE bit of the transmit descriptor 1: Occurrence of the corresponding source is not reflected in the TFE bit of the transmit descriptor...
Page 988 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description RRFCE RRF Bit Copy Directive 0: Reflects the RRF bit status in the RFE bit of the receive descriptor 1: Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor RTLFCE RTLF Bit Copy Directive 0: Reflects the RTLF bit status in the RFE bit of the...
Page 989: Receive Missed-Frame Counter Register (Rmfcr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.77 Receive Missed-Frame Counter Register (RMFCR) RMFCR is a 16-bit counter that indicates the number of frames that could not be saved in the receive buffer and so were discarded during reception. When the receive FIFO overflows, the receive frames in the FIFO are discarded.
Page 990: Transmit Fifo Threshold Register (Tftr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.78 Transmit FIFO Threshold Register (TFTR) TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the first transmission is started. The actual threshold is 4 times the set value. The E-MAC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is full, or when one frame of data write is performed.
Page 991: Fifo Depth Register (Fdr)
Section 23 Gigabit Ethernet Controller (GETHER) Note: When starting transmission before one frame of data write has completed, take care no underflow occurs. 23.3.79 FIFO Depth Register (FDR) FDR is a 32-bit readable/writable register that specifies the sizes of the transmit and receive FIFOs.
Page 992: Receiving Method Control Register (Rmcr)
Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description 4 to 0 RFD[4:0] All 1 Receive FIFO Size Specifies 256 bytes to 8 Kbytes in 256-byte units as the size of the receive FIFO whose maximum size is 8 Kbytes.
Page 993: Receive Descriptor Fetch Address Register (Rdfar)
Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description Receive Enable Control Sets whether to continue frame reception. 0: Upon completion of reception of one frame, the E- DMAC writes the receive status to the descriptor and clears the RR bit in EDRRR to 0. 1: Upon completion of reception of one frame, the E- DMAC writes (writes back) the receive status to the descriptor.
Page 994: Receive Descriptor Finished Address Register (Rdfxr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.82 Receive Descriptor Finished Address Register (RDFXR) RDFXR stores the start address of the receive descriptor for which the E-DMAC has just completed the write-back processing. Up to which receive descriptor has been processed by the E- DMAC can be recognized by monitoring addresses displayed in this register.
Page 995: Receive Descriptor Final Flag Register (Rdffr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.83 Receive Descriptor Final Flag Register (RDFFR) RDFFR indicates whether the receive descriptor for which the E-DMAC has just completed the write-back processing and whose start address is stored in RDFXR is at the end of the receive descriptor queue (descriptor list).
Page 996: Transmit Descriptor Fetch Address Register (Tdfar)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.84 Transmit Descriptor Fetch Address Register (TDFAR) TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the transmit descriptor. Which transmit descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register.
Page 997: Transmit Descriptor Finished Address Register (Tdfxr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.85 Transmit Descriptor Finished Address Register (TDFXR) TDFXR stores the start address of the transmit descriptor for which the E-DMAC has just completed the write-back processing. Up to which transmit descriptor has been processed by the E-DMAC can be recognized by monitoring addresses displayed in this register.
Page 998: Transmit Descriptor Final Flag Register (Tdffr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.86 Transmit Descriptor Final Flag Register (TDFFR) TDFFR indicates whether the transmit descriptor for which the E-DMAC has just completed the write-back processing and whose start address is stored in TDFXR is at the end of the transmit descriptor queue (descriptor list).
Page 999: Overflow Alert Fifo Threshold Register (Fcftr)
Section 23 Gigabit Ethernet Controller (GETHER) 23.3.87 Overflow Alert FIFO Threshold Register (FCFTR) FCFTR is a 32-bit readable/writable register that sets the flow control of the E-MAC. The threshold can be set by the size of the receive FIFO data (bits RFD[7:0]) and the number of receive frames (bits RFF[4:0]).
Page 1000 Section 23 Gigabit Ethernet Controller (GETHER) Initial Bit Name Value Description  15 to 8 All 0 Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 RFD[7:0] H'FF Receive FIFO Overflow Alert Signal Output Threshold H'00: When (256 −...

Renesas SH7763 Hardware Manual

Section 2 Programming Model

Section 3 Instruction Set

Section 4 Pipelining

Section 5 Exception Handling

Section 6 Memory Management Unit (MMU)

Section 7 Caches

Section 8 L Memory

Section 9 Interrupt Controller (INTC)

Section 10 Superhyway Bus Bridge (SBR)

Section 11 Local Bus State Controller (LBSC)

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Summary of Contents for Renesas SH7763