Renesas SH-4A User Manual page 70

Table 1.4 Measurement Items (cont)
Classification Type
Operand bus Access
performance miss count
(cont) (cont)
Waited
cycle
46
Measurement Item
Number of operand
cache miss (WRITE)
Number of U-RAM
read-buffer miss
Waited cycles for
operand fetch
(READ)
Waited cycles for
operand fetch
(WRITE)
Waited cycles for
operand cache miss
(READ)
Waited cycles for
operand cache miss
(WRITE)
Number of waited
cycles by an I-L
memory access for
operand fetch
(READ)
Number of waited
cycles by an I-L
memory access for
operand fetch
(WRITE)
Option Note
CMW The number of cache misses by
an operand cache access (write)
(number of accesses to the
outside of the CPU core due to
a cache miss).
Write-through accesses are not
counted.
Cache misses are not counted
by the PREF instruction.
UBM This function is disabled for the
MPU that the U memory is not
incorporated.
WOR The number of wait cycles by a
memory access (read) of an
operand.
WOW The number of wait cycles by a
memory access (write) of an
operand.
WCMR The number of wait cycles by an
operand cache miss (read)
(however, the number of wait
cycles of cache FIII is included
due to contention).
WCMW The number of wait cycles by an
operand cache miss (write).
WILR The number of waited cycles by
an I-L memory access (read) of
an operand.
WILW The number of waited cycles by
an I-L memory access (write) of
an operand.