Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series (CPU Core SH-2) Rev.6.00 2003.5.26...
Page 3 Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/ SH7040 Series (CPU Core SH-2) SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Group Hardware Manual REJ09B0044-0600O...
Page 4 The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Page 5 This hardware manual describes the SH7040 series hardware. Refer to the programming manual for a detailed description of the instruction set. Related Manual SH7040 series instructions SH-1/SH-2/SH-DSP Programming Manual Please consult your Renesas Technology sales representative for details for development environment system.
Page 7: Specifications
List of Items Revised or Added for This Version Section Page Description Notes on the SH7040 Series Specifications 1.1.1 SH7040 Series Accuracy Mask On-chip External Operating Electrical (5Vversion) Type Abbreviation Version Bus Width Package Temp Frequency Voltage Type Name Characteristics Features ±15LSB ZTAT...
Page 8 Section Page Description 11.2.3 DMA Description amended Transfer Count The data for the upper 8 bits of a DMATCR is 0 when read. Registers 0–3 (DMATCR0– DMATCR3) 11.2.4 DMA Description amended Channel Control • Bits 31–21—Reserved bits: Data are 0 when read.
Page 9 Section Page Description 12.9.2 Block Note added Diagram TIOC3B * Figure 12.125 POE TIOC3D * Block Diagram TIOC4A * TIOC4C * TIOC4B * TIOC4D * Note: * Includes multiplexed pins. 12.11.5 Usage Section added Notes 14.2.8 Bit Rate Table amended Register (BRR) 27.0336 Bit Rate...
Page 10 Section Page Description 15.4.9 A/D 33 MHz deleted Conversion Time Table 15.8 Operating Frequency and CKS Bit Settings 15.6 Notes on Use Figure amended Figure 15.14 Example of a AVcc Protection Circuit for the Analog Input Pins AVref This LSI 100Ω...
Page 11 Section Page Description 21.2.2 Socket Figure amended Adapter Pin 2 nF Correspondence and Memory Map Figure 21.3 SH7042 Pin and HN27C101 Pin Correspondence (120-Pin Version) 100 Ω 0.1 µF Figure 21.4 SH7043 Figure amended Pin and HN27C101 2 nF Pin Correspondence (144-Pin Version) 100 Ω...
Page 12 Section Page Description 22.7.2 Program- Figure amended Verify Mode Start Figure 22.13 Set SWE bit in FLMCR1 Program/Program Wait 10 µs Verify Flow Store 32-byte program data in reprogram data area n = 1 m = 0 Write 32-byte data in reprogram data area in RAM to flash memory consecutively Enable WDT Set PSU1(2) bit in FLMCR1(2)
Page 13 Section Page Description 22.7.4 Erase-Verify Figure amended Mode Start Figure 22.14 Set SWE bit in FLMCR1 Erase/Erase-Verify Wait 10 µs Flowchart n = 1 Set EBR1(2) Enable WDT Set ESU1(2) bit in FLMCR1(2) Wait 200 µs Start erase Set E1(2) bit in FLMCR1(2) Wait 5 ms Clear E1(2) bit in FLMCR1(2) Halt erase...
Page 14 Section Page Description 25.2 DC Note amended Characteristics *2 5 mA in the A mask version, except for F-ZTAT products. Table 25.2 DC Characteristics 25.3.2 Control Note amended Signal Timing Note: * The RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are Table 25.5 Control asynchronous inputs, but when thesetup times shown here Signal Timing...
Page 15 Section Page Description 25.3.3 Bus Timing Figure amended Figure 25.14 DRAM Tcw1 Tcw2 Cycle (Normal Mode, 3 Waits, TPC=1, Column RCD=1) CASD1 Figure amended 25.3.5 Multifunction Timer Pulse Unit Timing Figure 25.23 MTU I/O Timing TOCD Figure 25.24 MTU Figure amended Clock Input Timing TCKS 25.3.11 Measuring...
Page 16 Section Page Description 25.4 A/D Converter Table amended Characteristics Non-linearity error Table 25.16 A/D Offset error * Converter Timing (A mask) Full scale error * Quantize error * 26.2 DC Table amended Characteristics × ≥ V × 0.9V (min) – Schmitt PA2, PA5, PA6–...
Page 17 Section Page Description 26.3.3 Bus Timing Figure amended Figure 26.13 DRAM Tcw1 Tcw2 Cycle (Normal Mode, 2 Waits, TPC = 1, Column address RCD = 1) CASD1 CASD1 Figure 26.14 DRAM Figure amended Cycle (Normal Mode, Tcw1 Tcw2 3 Waits, TPC = 1, RCD = 1) Column address CASD1...
Page 18 Section Page Description Appendix B Block Note added Diagrams On-chip flash memory * Figure B.19 PB4/IRQ2/POE2/ CASH,PB3/IRQ1/ POE1/CASL Block Diagram (F-ZTAT Version) Note: * Only when n = 4. Appendix C Pin Table amended States Pin modes Table C.1 Pin Pin Function Reset Power-Down Bus Right...
Page 19 Section Page Description Appendix C Pin Table amended States Pin modes Table C.1 Pin Pin Function Reset Power-Down Bus Right Standby in Bus Modes During Reset, Class Pin Name Power-OnManual Standby Sleep Release Right Release Power-Down, and TIOC0A–TIOC0D, Bus Right Release TIOC1A–TIOC1D, TIOC2A–TIOC2D, Modes (144 Pin)
Page 20 Section Page Description Appendix C Pin Table amended States Pin modes Table C.2 Pin Pin Function Reset Power-Down Bus Right Standby in Bus Modes During Reset, Class Pin Name Power-On Manual Standby Sleep Release Right Release Power-Down, and Clock Bus Right Release System Modes (112 Pin, control...
Page 21 Section Page Description Appendix C Pin Table amended States Pin modes Table C.2 Pin Pin Function Reset Power-Down Bus Right Standby in Bus Modes During Reset, Class Pin Name Power-On Manual Standby Sleep Release Right Release Power-Down, and POE0–POE3 Port Bus Right Release control Modes (112 Pin,...
Page 22 Section Page Description 876, Appendix E Product Table amended Code Lineup Product Mask Product Code Mark Code Package Order Model No.* Type Version Table E.1 SH7040, SH7040A Mask ROM A MASK HD6437040AF28 HD6437040A (***)F28 QFP2020-112 HD6437040A***F verion HD6437040AVF16 HD6437040A(***)VF16 QFP2020-112 HD6437040A***F SH7041, SH7042, HD6437040AVX16...
Page 23: Table Of Contents
Contents Section 1 SH7040 Series Overview ................SH7040 Series Overview....................1.1.1 SH7040 Series Features..................Block Diagram........................11 Pin Arrangement and Pin Functions .................. 13 1.3.1 Pin Arrangment..................... 13 1.3.2 Pin Arrangement by Mode ................... 16 1.3.3 Pin Functions ......................37 The F-ZTAT Version Onboard Programming..............
Page 24 4.2.2 External Clock Input Method ................82 Prescaler..........................83 Oscillator Halt Function..................... 83 Usage Notes ........................83 4.5.1 Oscillator Usage Notes ..................83 4.5.2 Notes on Board Design..................84 4.5.3 Spread Spectrum Clock Generator Usage Notes ..........85 Section 5 Exception Processing ..................
Page 25 6.2.3 IRQ Interrupts....................... 102 6.2.4 On-Chip Peripheral Module Interrupts..............103 6.2.5 Interrupt Exception Vectors and Priority Rankings ..........103 Description of Registers..................... 108 6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH)........... 108 6.3.2 Interrupt Control Register (ICR) ................109 6.3.3 IRQ Status Register (ISR) ..................110 Interrupt Operation......................
Page 26 Section 8 Data Transfer Controller (DTC) ..............133 Overview..........................133 8.1.1 Features......................... 133 8.1.2 Block Diagram...................... 134 8.1.3 Register Configuration ..................135 Register Description ......................135 8.2.1 DTC Mode Register (DTMR) ................135 8.2.2 DTC Source Address Register (DTSAR)............. 138 8.2.3 DTC Destination Address Register (DTDAR).............
Page 27 9.4.4 Cache Hit after Cache Miss .................. 162 Section 10 Bus State Controller (BSC) ................. 163 10.1 Overview..........................163 10.1.1 Features......................... 163 10.1.2 Block Diagram...................... 164 10.1.3 Pin Configuration ....................165 10.1.4 Register Configuration ..................166 10.1.5 Address Map......................167 10.2 Description of Registers.....................
Page 28 11.1.2 Block Diagram...................... 215 11.1.3 Pin Configuration ....................216 11.1.4 Register Configuration ..................217 11.2 Register Descriptions......................218 11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........... 218 11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) ........219 11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......220 11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)........
Page 29 12.2.1 Timer Control Register (TCR) ................283 12.2.2 Timer Mode Register (TMDR)................288 12.2.3 Timer I/O Control Register (TIOR) ..............290 12.2.4 Timer Interrupt Enable Register (TIER)............... 306 12.2.5 Timer Status Register (TSR) ................309 12.2.6 Timer Counters (TCNT)..................312 12.2.7 Timer General Register (TGR)................
Page 30 12.7.7 Contention between TGR Write and Input Capture ..........395 12.7.8 Contention between Buffer Register Write and Input Capture ......396 12.7.9 Contention between TGR Write and Compare Match ......... 397 12.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..397 12.7.11 Counter Value during Complementary PWM Mode Stop ........
Page 31 13.1 Overview..........................455 13.1.1 Features......................... 455 13.1.2 Block Diagram...................... 456 13.1.3 Pin Configuration ....................456 13.1.4 Register Configuration ..................457 13.2 Register Descriptions......................457 13.2.1 Timer Counter (TCNT)..................457 13.2.2 Timer Control/Status Register (TCSR) ..............458 13.2.3 Reset Control/Status Register (RSTCSR) ............460 13.2.4 Register Access.....................
Page 32 14.4 SCI Interrupt Sources and the DMAC/DTC..............532 14.5 Notes on Use ........................533 14.5.1 TDR Write and TDRE Flags ................533 14.5.2 Simultaneous Multiple Receive Errors..............533 14.5.3 Break Detection and Processing................534 14.5.4 Sending a Break Signal..................534 14.5.5 Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only)........................
Page 33 16.1.4 Register Configuration ..................570 16.2 Register Descriptions......................571 16.2.1 A/D Data Register A–D (ADDRA0–ADDRD0, ADDRA1–ADDRD1) .... 571 16.2.2 A/D Control/Status Register (ADCSR0, ADCSR1)..........572 16.2.3 A/D Control Register (ADCR0, ADCR1) ............574 16.3 Interface with CPU ......................575 16.4 Operation ........................... 576 16.4.1 Single Mode (SCAN=0) ..................
Page 34 18.3.1 Port A I/O Register H (PAIORH)................. 608 18.3.2 Port A I/O Register L (PAIORL) ................. 609 18.3.3 Port A Control Register H (PACRH) ..............609 18.3.4 Port A Control Registers L1, L2 (PACRL1 and PACRL2) ......... 612 18.3.5 Port B I/O Register (PBIOR)................617 18.3.6 Port B Control Registers (PBCR1 and PBCR2)...........
Page 35 Section 21 128kB PROM ....................669 21.1 Overview..........................669 21.2 PROM Mode........................670 21.2.1 PROM Mode Settings................... 670 21.2.2 Socket Adapter Pin Correspondence and Memory Map ........670 21.3 PROM Programming ......................674 21.3.1 Programming Mode Selection ................674 21.3.2 Write/Verify and Electrical Characteristics............675 21.3.3 Cautions on Writing .....................
Page 36 22.8.3 Error Protection ....................720 22.9 Flash Memory Emulation in RAM ..................722 22.10 Note on Flash Memory Programming/Erasing ..............724 22.11 Flash Memory Programmer Mode..................724 22.11.1 Socket Adapter Pin Correspondence Diagrams ........... 725 22.11.2 Programmer Mode Operation................728 22.11.3 Memory Read Mode.....................
Page 37 25.3.9 High-speed A/D Converter Timing (excluding A mask) ........774 25.3.10 Mid-speed Converter Timing (A mask) ............... 776 25.3.11 Measuring Conditions for AC Characteristics ............. 778 25.4 A/D Converter Characteristics................... 779 Section 26 Electrical Characteristics (3.3V, 16.7 MHz Version) ......781 26.1 Absolute Maximum Ratings ....................
Page 39: Section 1 Sh7040 Series Overview
These versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. Notes: *1 ZTAT (Zero Turn-Around Time) is a registered trademark of Renesas Technology Corp. *2 F-ZTAT (Flexible ZTAT) is a trademark of Renesas Technology Corp.
Page 40  Instruction length: 16-bit fixed length for improved code efficiency  Load-store architecture (basic operations are executed between registers)  Delayed branch instructions reduce pipeline disruption during branch  Instruction set based on C language • Instruction execution time: one instruction/cycle (35 ns/instruction at 28.7-MHz operation) •...
Page 41  Outputs chip-select signals for each area  During DRAM space access: • Outputs RAS and CAS signals for DRAM • Can generate a RAS precharge time assurance Tp cycle • DRAM burst access function  Supports high-speed access mode for DRAM •...
Page 42 • 16 independent comparators • 8 types of counter input clock • Input capture function • Pulse output mode  One shot, toggle, PWM, phase-compensated PWM, reset-synchronized PWM • Multiple counter synchronization function • Phase-compensated PWM output mode  Non-overlapping waveform output for 6-phase inverter control ...
Page 43  Total: 82 • QFP 144 (SH7041, SH7043, SH7045)  Input/output: 98  Input: 8  Total: 106 A/D Converter: • 10 bits × 8 channels • Conversion upon external trigger possible • Sample and hold function: two on-chip units (two channels can be sampled simultaneously) •...
Page 45 Notes on the SH7040 Series Specifications (For details, see each section in this manual) Mask On-chip External Accuracy Operating Electrical Type Abbreviation Version Bus Width (5V Version) Package Temp Frequency Voltage Type Name INTC DMAC Converter Characteristics ZTAT SH7042 128 kB 16 bits ±15LSB QFP2020-112...
Page 47 Notes on the SH7040 Series Specifications (For details, see each section in this manual) Mask On-chip External Accuracy Operating Electrical Type Abbreviation Version Bus Width (5V Version) Package Temp Frequency Voltage Type Name INTC DMAC Converter Characteristics MASK SH7044 A mask 256 kB 16 bits ±4LSB...
Page 49: Block Diagram
Block Diagram Figure 1.1 is a block diagram of the SH7040 Series QFP-112 pin and TQFP-120 pin. Figure 1.2 is a block diagram of the SH7040 Series QFP-144 pin. RES/V WDTOVF PC15/A15 PC14/A14 PC13/A13 Flash ROM/PROM/ PC12/A12 RAM/cache mask ROM 4 kbytes/1 kbyte PC11/A11 256kbytes/...
Page 50 PC15/A15 PC14/A14 PC13/A13 PC12/A12 PC11/A11 PC10/A10 PC9/A9 PC8/A8 PC7/A7 PC6/A6 RES/V WDTOVF PC5/A5 PC4/A4 PC3/A3 PC2/A2 Flash ROM/PROM/ RAM/cache mask ROM PC1/A1 4 kbytes/1 kbyte 256 kbytes/ EXTAL 128 kbytes/64 kbytes PC0/A0 XTAL PD31/D31/ADTRG PLLVCC PD30/D30/IRQOUT PLLCAP PLLVSS PD29/D29/CS3 /FWP Data transfer PD28/D28/CS2 controller...
Page 51: Pin Arrangement And Pin Functions
Pin Arrangement and Pin Functions 1.3.1 Pin Arrangment Figure 1.3 shows the pin arrangement for the QFP-112 (top view). PE0/TIOC0A/DREQ0 PD12/D12 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PD13/D13 PE3/TIOC0D/DRAK1 PD14/D14 PD15/D15 PE4/TIOC1A PA0/RXD0 PF0/AN0 PA1/TXD0 PF1/AN1 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PF2/AN2 PF3/AN3 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PF4/AN4 PF5/AN5 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PF6/AN6...
Page 52 Figure 1.4 shows the pin arrangement for the TFP-120 (top view). RES/(Vpp * ) PE14/TIOC4C/DACK0/AH PA15/CK PE15/TIOC4D/DACK1/IRQOUT PLLVss PC0/A0 PLLCAP PC1/A1 PLLVcc PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 EXTAL PC7/A7 PC8/A8 PC9/A9 XTAL TQFP-120 PC10/A10 PD0/D0 PC11/A11 PD1/D1 PC12/A12 PD2/D2 PC13/A13 PD3/D3 PC14/A14 PC15/A15...
Page 53 Figure 1.5 shows the pin arrangement for the QFP-144 (top view). PD16/D16/IRQ0 PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PD17/D17/IRQ1 PE2/TIOC0C/DREQ1 PD18/D18/IRQ2 PD19/D19/IRQ3 PE3/TIOC0D/DRAK1 PD20/D20/IRQ4 PE4/TIOC1A PD21/D21/IRQ5 PE5/TIOC1B PD22/D22/IRQ6 PE6/TIOC2A PD23/D23/IRQ7 PF0/AN0 PF1/AN1 PD24/D24/DREQ0 PF2/AN2 PD25/D25/DREQ1 PF3/AN3 PD26/D26/DACK0 PF4/AN4 PD27/D27/DACK1 PF5/AN5 PD28/D28/CS2 PD29/D29/CS3 PF6/AN6 QFP-144 PF7/AN7 PA6/TCLKA/CS2 AV ref...
Page 54: Pin Arrangement By Mode
1.3.2 Pin Arrangement by Mode Table 1.2 Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) Pin No. MCU Mode PROM Mode PE14/TIOC4C/DACK0/AH PE15/TIOC4D/DACK1/IRQOUT PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PB2/IRQ0/POE0/RAS...
Page 55 Table 1.2 Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) (cont) Pin No. MCU Mode PROM Mode PB6/IRQ4/A18/BACK PB7/IRQ5/A19/BREQ PB8/IRQ6/A20/WAIT PB9/IRQ7/A21/ADTRG PA14/RD WDTOVF PA13/WRH PA12/WRL PA11/CS1 PA10/CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQI PA4/TXD1 PA3 /RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 PD15/D15 PD14/D14 PD13/D13 PD12/D12...
Page 56 Table 1.2 Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) (cont) Pin No. MCU Mode PROM Mode PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 XTAL EXTAL PLLVCC PLLCAP PLLVSS PA15/CK PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1...
Page 57 Table 1.2 Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) (cont) Pin No. MCU Mode PROM Mode PE4/TIOC1A PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES...
Page 58 Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) TQFP120 Pin No. MCU Mode PROM Mode PE14/TIOC4C/DACK0/AH PE15/TIOC4D/DACK1/IRQOUT PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PB2/IRQ0/POE0/RAS PB3/IRQ1/POE1/CASL PB4/IRQ2/POE2/CASH PB5/IRQ3/POE3/RDWR...
Page 59 Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) (cont) TQFP120 Pin No. MCU Mode PROM Mode PB6/IRQ4/A18/BACK PB7/IRQ5/A19/BREQ PB8/IRQ6/A20/WAIT PB9/IRQ7/A21/ADTRG PA14/RD WDTOVF PA13/WRH PA12/WRL PA11/CS1 PA10/CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 PA3/RXD2 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 PD15/D15 PD14/D14 PD13/D13 PD12/D12...
Page 60 Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) (cont) TQFP120 Pin No. MCU Mode PROM Mode PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 XTAL EXTAL PLLV PLLCAP PLLV PA15/CK PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0...
Page 61 Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) (cont) TQFP120 Pin No. MCU Mode PROM Mode PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES...
Page 62 Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) Pin No. MCU Mode PROM Mode PA23/WRHH PE14/TIOC4C/DACK0/AH PA22/WRHL PA21/CASHH PE15/TIOC4D/DACK1/IRQOUT PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PA20/CASHL PA19/BACK/DRAK1...
Page 63 Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No. MCU Mode PROM Mode PB2/IRQ0/POE0/RAS PB3/IRQ1/POE1/CASL PA18/BREQ/DRAK0 PB4/IRQ2/POE2/CASH PB5/IRQ3/POE3/RDWR PB6/IRQ4/A18/BACK PB7/IRQ5/A19/BREQ PB8/IRQ6/A20/WAIT PB9/IRQ7/A21/ADTRG PA14/RD WDTOVF PD31/D31/ADTRG PD30/D30/IRQOUT PA13/WRH PA12/WRL PA11/CS1 PA10/CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PD29/D29/CS3 PD28/D28/CS2 PD27/D27/DACK1 PD26/D26/DACK0...
Page 64 Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No. MCU Mode PROM Mode PD24/D24/DREQ0 PD23/D23/IRQ7 PD22/D22/IRQ6 PD21/D21/IRQ5 PD20/D20/IRQ4 PD19/D19/IRQ3 PD18/D18/IRQ2 PD17/D17/IRQ1 PD16/D16/IRQ0 PD15/D15 PD14/D14 PD13/D13 PD12/D12 PD11/D11 PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5 /D5 PD4/D4 PD3/D3 PD2/D2...
Page 65 Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No. MCU Mode PROM Mode PD1/D1 PD0/D0 XTAL EXTAL PA16/AH PA17/WAIT PLLVCC PLLCAP PLLVSS PA15/CK PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PF0/AN0 PF1/AN1 PF2/AN2...
Page 66 Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No. MCU Mode PROM Mode PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVref PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0 /IREQ0 PA3/RXD1 PA4/TXD1 PA5 /SCK1/DREQ1/IREQ1 PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B /MRES...
Page 67 Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) PinNo. Writer mode PE14/TIOC4C/DACK0/AH PE15/TIOC4D/DACK1/IRQOUT PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PB2/IRQ0/POE0/RAS PB3/IRQ1/POE1/CASL PB4/IRQ2/POE2/CASH PB5/IRQ3/POE3/RDWR PB6/IRQ4/A18/BACK PB7/IRQ5/A19/BREQ PB8/IRQ6/A20/WAIT PB9/IRQ7/A21/ADTRG...
Page 68 Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) (cont) PinNo. Writer mode PA14/RD WDTOVF PA13/WRH PA12/WRL PA11/CS1 PA10/CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 PA3/RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 PD15/D15 PD14/D14 PD13/D13 PD12/D12 PD11/D11 PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5...
Page 69 Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) (cont) PinNo. Writer mode PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 XTAL XTAL EXTAL EXTAL (FWP) * PLLV PLLV PLLCAP PLLCAP PLLV PLLV PA15/CK PE0/TIOCA/DREQ0 PE1/TIOCB/DRAK0 PE2/TIOCC/DREQ1 PE3/TIOCD/DRAK1 PE4/TIOC1A PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5...
Page 70 Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) (cont) PinNo. Writer mode PF6/AN6 PF7/AN7 PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES...
Page 71 Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) PinNo. Writer mode PA23/WRHH PE14/TIOC4C/DACK0/AH PA22/WRHL PA21/CASHH PE15/TIOC4D/DACK1/IRQOUT PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PA20/CASHL PA19/BACK/DRAK1 PB2/IRQ0/POE0/RAS PB3/IRQ1/POE1/CASL PA18/BREQ/DRAK0 PB4/IRQ2/POE2/CASH PB5/IRQ3/POE3/RDWR...
Page 72 Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) (cont) PinNo. Writer mode PB6/IRQ4/A18/BACK PB7/IRQ5/A19/BREQ PB8/IRQ6/A20/WAIT PB9/IRQ7/A21/ADTRG PA14/RD WDTOVF PD31/D31/ADTRG PD30/D30/IRQOUT PA13/WRH PA12/WRL PA11/CS1 PA10/CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PD29/D29/CS3 PD28/D28/CS2 PD27/D27/DACK1 PD26/D26/DACK0 PD25/D25/DREQ1 PD24/D24/DREQ0 PD23/D23/IRQ7 PD22/D22/IRQ6 PD21/D21/IRQ5 PD20/D20/IRQ4 PD19/D19/IRQ3 PD18/D18/IRQ2 PD17/D17/IRQ1...
Page 73 Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) (cont) PinNo. Writer mode PD15/D15 PD14/D14 PD13/D13 PD12/D12 PD11/D11 PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 XTAL XTAL EXTAL EXTAL (FWP) * PA16/AH PA17/WAIT PLLV PLLV PLLCAP PLLCAP PLLV...
Page 74 Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) (cont) PinNo. Writer mode PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVref PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES...
Page 75: Pin Functions
1.3.3 Pin Functions Table 1.7 lists the pin functions. Table 1.7 Pin Functions Classification Symbol Name Function Power supply Supply Connects to power supply. Connect all V pins to the system supply. No operation will occur if there are any open pins. Ground Connects to ground.
Page 76 Table 1.7 Pin Functions (cont) Classification Symbol Name Function Operating MD0–MD3 Mode set Determines the operating mode. Do mode control not change input value during operation. Flash memory Protects flash memory from being write protect written or deleted. Interrupts Non-maskable Non-maskable interrupt request pin.
Page 77 Table 1.7 Pin Functions (cont) Classification Symbol Name Function CASL Bus control Lower column Timing signal for DRAM column (cont) address strobe address strobe. Output when the lower 8 bits of data are accessed. RDWR DRAM DRAM write strobe signal. read/write Address hold Address hold timing signal for...
Page 78 Table 1.7 Pin Functions (cont) Classification Symbol Name Function Bus control TIOC3A MTU input Channel 3 input capture input/output multifunction capture/output compare output/PWM output pins. TIOC3B timer/pulse unit compare TIOC3C (cont) (channel 3) TIOC3D TIOC4A MTU input Channel 4 input capture input/output capture/output compare output/PWM output pins.
Page 79 Table 1.7 Pin Functions (cont) Classification Symbol Name Function POE0– I/O ports Port output Input pin for port pin drive control POE3 enable when general use ports are established as output. PA0– General purpose General purpose input/output port PA15 port pins.
Page 80: The F-Ztat Version Onboard Programming
The F-ZTAT Version Onboard Programming There are 2 modes on the F-ZTAT version: a mode that writes and overwrites programs using the special writer and a mode that writes and overwrites programs onboard the application system. When rebooting after setting each mode pin and FWP pin during the reset condition, the microcomputer will transfer to one of the modes indicated in figure 1.6.
Page 81 <Host> Write control program Application program <SH7044/45> RXD1 TXD1 SCI 1 Boot program <Flash memory> <RAM> Write control program area Application program Boot program area Figure. 1.7 Data Transfer during Boot Mode...
Page 83: Section 2 Cpu
Section 2 CPU Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0–R15. General registers are used for data processing and address calculation.
Page 84: Control Registers
2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules.
Page 85: System Registers
2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure.
Page 86: Data Formats
Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4).
Page 87: Instruction Features
Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Instruction Features 2.3.1 RISC-Type Instruction Set All instructions are RISC type.
Page 88 Table 2.3 Delayed Branch Instructions SH7040 Series CPU Description Example of Conventional CPU Executes an ADD before TRGET ADD.W R1,R0 branching to TRGET R1,R0 TRGET Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation operations are executed in two to three cycles.
Page 89 Table 2.5 Immediate Data Accessing Classification SH7040 Series CPU Example of Conventional CPU 8-bit immediate #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 ....DATA.W H'1234 32-bit immediate MOV.L @(disp,PC),R0 MOV.L #H'12345678,R0 ....DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table.
Page 90: Addressing Modes
2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Addresses Calculation Equation Direct register The effective address is register Rn. (The operand — addressing is the contents of register Rn.) Indirect register The effective address is the content of register Rn.
Page 91 Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Addresses Calculation Equation Indirect register The effective address is Rn plus a 4-bit Byte: Rn + @(disp:4, addressing with displacement (disp). The value of disp is zero- disp displacement extended, and remains the same for a byte...
Page 92 Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Addresses Calculation Equation Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR + R0 GBR addressing GBR + R0 PC relative The effective address is the PC value plus an 8-bit Word: PC + @(disp:8,...
Page 93 Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Addresses Calculation Equation PC + disp × 2 PC relative The effective address is the PC value sign-extended disp:8 addressing with an 8-bit displacement (disp), doubled, and added to the PC value.
Page 94: Instruction Format
2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: • xxxx: Instruction code • mmmm: Source register •...
Page 95 Table 2.9 Instruction Formats (cont) Source Operand Destination Instruction Formats Operand Example nm format mmmm: Direct nnnn: Direct Rm,Rn register register mmmm: Direct nnnn: Indirect MOV.L Rm,@Rn register register xxxx nnnn mmmm xxxx mmmm: Indirect MACH, MACL MAC.W post-increment @Rm+,@Rn+ register (multiply/ accumulate) nnnn * : Indirect...
Page 96 Table 2.9 Instruction Formats (cont) Source Operand Destination Instruction Formats Operand Example d format dddddddd: R0 (Direct register) MOV.L Indirect GBR @(disp,GBR),R0 with xxxx xxxx dddd dddd displacement R0(Direct dddddddd: Indirect MOV.L register) GBR with R0,@(disp,GBR) displacement dddddddd: PC R0 (Direct register) MOVA relative with @(disp,PC),R0 displacement...
Page 97: Instruction Set By Classification
Instruction Set by Classification Table 2.10 Classification of Instructions Operation No. of Classification Types Code Function Instructions Data transfer Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer MOVA Effective address transfer MOVT T bit transfer SWAP Swap of upper and lower bytes XTRCT Extraction of the middle of registers connected...
Page 98 Table 2.10 Classification of Instructions (cont) Operation No. of Classification Types Code Function Instructions Logic Logical AND operations Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR Shift ROTL One-bit left rotation ROTR One-bit right rotation ROTCL...
Page 99 Table 2.10 Classification of Instructions (cont) Operation No. of Classification Types Code Function Instructions System CLRT T bit clear control CLRMAC MAC register clear Load to control register Load to system register No operation Return from exception processing SETT T bit set SLEEP Shift into power-down mode Storing control register data...
Page 100 Table 2.11 Instruction Code Format Item Format Explanation Instruction OP: Operation code OP.Sz SRC,DEST Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement * MSB ↔ LSB Instruction mmmm: Source register code...
Page 101 Table 2.12 Data Transfer Instructions Execu- tion Instruction Instruction Code Operation Cycles #imm → Sign extension → — #imm,Rn 1110nnnniiiiiiii (disp × 2 + PC) → Sign — MOV.W @(disp,PC),Rn 1001nnnndddddddd extension → Rn (disp × 4 + PC) → Rn —...
Page 102 Table 2.12 Data Transfer Instructions (cont) Execu- tion Instruction Instruction Code Operation Cycles Rm → (R0 + Rn) — MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 (R0 + Rm) → Sign — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 extension →...
Page 103 Table 2.13 Arithmetic Operation Instructions Execu- tion Instruction Instruction Code Operation Cycles T Bit Rn + Rm → Rn — Rm,Rn 0011nnnnmmmm1100 Rn + imm → Rn — #imm,Rn 0111nnnniiiiiiii Rn + Rm + T → Rn, Carry ADDC Rm,Rn 0011nnnnmmmm1110 Carry →...
Page 104 Table 2.13 Arithmetic Operation Instructions (cont) Execu- tion Instruction Instruction Code Operation Cycles T Bit 2 to 4 * Signed operation of Rn — DMULS.L Rm,Rn 0011nnnnmmmm1101 × Rm → MACH, MACL 32 × 32 → 64 bit 2 to 4 * Unsigned operation of —...
Page 105 Table 2.13 Arithmetic Operation Instructions (cont) Execu- tion Instruction Instruction Code Operation Cycles T Bit Rn–Rm → Rn — Rm,Rn 0011nnnnmmmm1000 Rn–Rm–T → Rn, Borrow SUBC Rm,Rn 0011nnnnmmmm1010 Borrow → T Rn–Rm → Rn, Overflow SUBV Rm,Rn 0011nnnnmmmm1011 Underflow → T Note: * The normal minimum number of execution cycles.
Page 106 Table 2.14 Logic Operation Instructions Execu- tion Instruction Instruction Code Operation Cycles T Bit Rn & Rm → Rn — Rm,Rn 0010nnnnmmmm1001 R0 & imm → R0 — #imm,R0 11001001iiiiiiii (R0 + GBR) & imm → — AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) ~Rm →...
Page 107 Table 2.15 Shift Instructions Execu- tion Instruction Instruction Code Operation Cycles T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 LSB → Rn → T ROTR 0100nnnn00000101 T ← Rn ← T ROTCL 0100nnnn00100100 T → Rn → T ROTCR 0100nnnn00100101 T ←...
Page 108 Table 2.16 Branch Instructions Exec. Instruction Instruction Code Operation Cycles If T = 0, disp × 2 + PC → PC; if T = 3/1 * — label 10001011dddddddd 1, nop Delayed branch, if T = 0, disp × 2 + 2/1 * —...
Page 109 Table 2.17 System Control Instructions Exec. Instruction Instruction Code Operation Cycles T Bit 0 → T CLRT 0000000000001000 0 → MACH, MACL — CLRMAC 0000000000101000 Rm → SR Rm,SR 0100mmmm00001110 Rm → GBR — Rm,GBR 0100mmmm00011110 Rm → VBR — Rm,VBR 0100mmmm00101110 (Rm) →...
Page 110: Processing States
Table 2.17 System Control Instructions (cont) Exec. Instruction Instruction Code Operation Cycles T Bit Rn–4 → Rn, MACH → (Rn) — STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACL → (Rn) — STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, PR → (Rn) —...
Page 111 From any state From any state when when RES = 0 RES = 1 and MRES = 0 Power-on reset state Manual reset state RES = 0 Reset states RES = 1 RES = 1 MRES = 1 When an interrupt source or DMA address error occurs Exception processing state Bus request...
Page 112: Power-Down State
For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area.
Page 113 CPU returns to ordinary program execution state through the exception processing state after the oscillator stabilization time has elapsed. In this mode, power consumption drops markedly, since the oscillator stops (table 2.18). Table 2.18 Power-Down State State On-Chip On-Chip Cache or Transition Peripheral On-Chip...
Page 115: Section 3 Operating Modes
Section 3 Operating Modes Operating Modes, Types, and Selection This LSI has five operating modes and three clock modes, determined by the setting of the mode pins (MD3–MD0). Do not change the mode pin settings during LSI operation (while power is on). (In the F-ZTAT version, however, MD1 can be changed in the power-on reset state.) Table 3.1 indicates the setting method for the operating mode.
Page 116: Explanation Of Operating Modes
Table 3.2 indicates the setting method for the clock mode. Table 3.2 Clock Mode Setting Clock Mode PLL ON × 1 PLL ON × 2 PLL ON × 4 Reserved (PROM mode only) Explanation of Operating Modes Table 3.3 describes the operating modes. Table 3.3 Operating Modes Mode...
Page 117: Pin Configuration
Pin Configuration Table 3.4 describes the function of each operating mode related pin. Table 3.4 Operating Mode Pin Function Name Input/Output Function XTAL Input Connects to a crystal oscillator EXTAL Input Connects to a crystal oscillator, or used for external clock input pin PLLCAP Input Connects to a capacitor for PLL circuit operation...
Page 119: Clock Pulse Generator (Cpg)
Section 4 Clock Pulse Generator (CPG) Overview The SH7040 Series has an on-chip clock pulse generator (CPG) that generates the system clock (φ), as well as the internal clock (φ/2 to φ/8192). The CPG consists of an oscillator, a PLL, and a prescaler.
Page 120: External Clock Input Method
EXTAL 4–10 MHz XTAL = 18–22 pF (Recommended value) Figure 4.2 Connection of the Crystal Oscillator (Example) Table 4.1 Damping Resistance Values (Recommended Values) Frequency (MHz) Parameter Rd (Ω) Crystal Oscillator: Figure 4.3 shows an equivalent circuit of the crystal oscillator. Use a crystal oscillator with the characteristics listed in table 4.2.
Page 121: Prescaler
When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to delay until after the oscillation stabilization time (upon power-on) or after release from standby, in order to ensure the PLL stabilization time. EXTAL External clock input 4–10 MHz...
Page 122: Notes On Board Design
4.5.2 Notes on Board Design When connecting a crystal oscillator, observe the following precautions: • To prevent induction from interfering with correct oscillation, do not route any signal lines near the oscillator circuitry. • When designing the board, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins.
Page 123: Spread Spectrum Clock Generator Usage Notes
External circuitry such as that shown in figure 4.6 is recommended around the PLL. R1: 3 kΩ C1: 470 pF PLLCAP Rp: 200 Ω PLLV CPB: 0.1 µF * PLLV CB: 0.1 µF * Note: * CB and CPB are laminated ceramic capacitors (Recommended values) Figure 4.6 Cautions for Use of PLL Oscillator Circuit Place oscillation stabilization capacitor C1 and resistor R1 near the PLLCAP pin, and ensure that...
Page 125: Section 5 Exception Processing
Section 5 Exception Processing Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority shown.
Page 126: Exception Processing Operations
5.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and the Start of Exception Processing Exception Source Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high.
Page 127: Exception Processing Vector Table
5.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated.
Page 128: Resets
Table 5.3 Exception Processing Vector Table (cont) Vector Exception Sources Numbers Vector Table Address Offset Interrupts IRQ0 H'00000100–H'00000103 IRQ1 H'00000104–H'00000107 IRQ2 H'00000108–H'0000010B IRQ3 H'0000010C–H'0000010F IRQ4 H'00000110–H'00000113 IRQ5 H'00000114–H'00000117 IRQ6 H'00000118–H'0000011B IRQ7 H'0000011C–H'0000011F On-chip peripheral H'00000120–H'00000124 module * H'000003FC–H'000003FF Note: * The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, Interrupt Controller (INTC), and table 6.3, Interrupt Exception Processing Vectors and Priorities.
Page 129: Power-On Reset
Table 5.5 Types of Resets Conditions for Transition to Reset Status Internal Status MRES Type On-Chip Peripheral Module Power-on reset — Initialized Initialized Manual reset High Initialized Not initialized 5.2.1 Power-On Reset When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 t (when the...
Page 130: Address Errors
reset mode. (Keep at low level for at least the longest bus cycle.) See Appendix C, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high.
Page 131: Address Error Exception Processing
5.3.1 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2.
Page 132: Interrupt Priority Level
5.4.1 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and priority 16 the highest.
Page 133: Trap Instructions
Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment Trap instructions TRAPA — Illegal slot Undefined code placed Delayed branch instructions: JMP, JSR, instructions immediately after a delayed BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, branch instruction (delay slot) BRAF and instructions that rewrite the Instructions that rewrite the PC: JMP, JSR,...
Page 134: General Illegal Instructions
5.5.3 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code.
Page 135: Stack Status After Exception Processing Ends
Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 5.11. Table 5.11 Types of Stack Status after Exception Processing Ends Types Stack Status Address error Address of instruction 32 bits after executed instruction 32 bits Trap instruction...
Page 136: Notes On Use
Notes on Use 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four.
Page 137: Interrupt Controller (Intc)
Section 6 Interrupt Controller (INTC) Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 Features The INTC has the following features:...
Page 138 IRQOUT IRQ0 IRQ1 IRQ2 Input CPU/ Priority IRQ3 control ranking IRQ4 request judg- Com- IRQ5 Interrupt judg- ment parator request IRQ6 ment IRQ7 (Interrupt request) (Interrupt request) I3 I2 I1 I0 DMAC (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request)
Page 139: Pin Configuration
6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation Function Non-maskable interrupt input pin Input of non-maskable interrupt request signal IRQ0–IRQ7 Interrupt request input pins Input of maskable interrupt request signals IRQOUT Interrupt request output pin Output of notification signal when an interrupt has occurred 6.1.4...
Page 140: Interrupt Sources
Interrupt Sources There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 6.2.1 NMI Interrupts The NMI interrupt has priority 16 and is always accepted.
Page 141: On-Chip Peripheral Module Interrupts
6.2.4 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: • Direct memory access controller (DMAC) • Multifunction timer/pulse unit (MTU) • Compare match timer (CMT) • Serial communications interface (SCI) • A/D converter (A/D) •...
Page 142 Table 6.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Interrupt Priority Vector Table Priority Corre- within IPR Vector Address (Initial sponding Setting Default Interrupt Source Offset Value) IPR (Bits) Range Priority H'0000002C– — — High H'0000002F User break H'00000030– —...
Page 143 Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Interrupt Priority Vector Table Priority Corre- within IPR Vector Address (Initial sponding Setting Default Interrupt Source Offset Value) IPR (Bits) Range Priority MTU0 TGI0A H'00000160– 0–15 (0) IPRD High High H'00000163 (15–12)
Page 144 Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Interrupt Priority Vector Table Priority Corre- within IPR Vector Address (Initial sponding Setting Default Interrupt Source Offset Value) IPR (Bits) Range Priority MTU3 TGI3A H'000001C0– 0–15 (0) IPRE High High H'000001C3 (7–4)
Page 145 Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Interrupt Priority Vector Table Priority Corre- within IPR Vector Address (Initial sponding Setting Default Interrupt Source Offset Value) IPR (Bits) Range Priority SCI1 ERI1 H'00000210– 0–15 (0) IPRF High High H'00000213 (3–0)
Page 146: Description Of Registers
Description of Registers 6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) Interrupt priority registers A–H (IPRA–IPRH) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA–IPRH bits is shown in table 6.4.
Page 147: Interrupt Control Register (Icr)
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15–12, 11–8, 7–4, and 3–0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F.
Page 148: Irq Status Register (Isr)
• Bit 8—NMI Edge Select (NMIE) Bit 8: NMIE Description Interrupt request is detected on falling edge of NMI input (initial value) Interrupt request is detected on rising edge of NMI input • Bits 7–0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7 interrupt request detection mode.
Page 149 • Bits 7–0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt request status. Bits 7-0: IRQ0F–IRQ7F Detection Setting Description Level detection No IRQn interrupt request exists. Clear conditions: When IRQn input is high level Edge detection No IRQn interrupt request was detected. (initial value) Clear conditions: 1.
Page 150: Interrupt Operation
Interrupt Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers A–H (IPRA–IPRH).
Page 151 Program execution state Interrupt? NMI? User break? Level 15 interrupt? IRQOUT = low level * Level 14 interrupt? Save SR to stack I3 to I0 ≤ Level 1 level 14? Save PC to stack interrupt? I3 to I0 ≤ Copy accept-interrupt level 13? level to I3 to I0 I3 to I0 =...
Page 152: Stack After Interrupt Exception Processing
6.4.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address PC * 32 bits SP * 4n–8 32 bits 4n–4 Notes: *1 PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Processing Interrupt Response Time...
Page 153 Table 6.5 Interrupt Response Time Number of States NMI, Peripheral Item Module Notes DMAC/DTC active 0 or 1 1 state required for interrupt judgment signals for which DMAC/DTC activation is possible Compare identified inter- rupt priority with SR mask level Wait for completion of X (≥...
Page 154: Data Transfer With Interrupt Request Signals
Interrupt acceptance 5 + m1 + m2 + m3 m1 m2 1 m3 1 Instruction (instruction M M E M E E replaced by interrupt exception processing) Overrun fetch Interrupt service routine F D E start instruction Instruction fetch (instruction fetched from memory where program is stored). Instruction decoding (fetched instruction is decoded).
Page 155: Handling Dtc Activating And Cpu Interrupt Sources, But Not Dmac Activating Sources
Interrupt source DMAC Interrupt source flag clear (by DMAC) Interrupt source (those not designated as DMAC activating sources) CPU interrupt request DTC activation request DTER DTECLR DTE clear Transfer end Interrupt source flag clear (by DTC) Figure 6.6 Interrupt Control Block Diagram 6.6.1 Handling DTC Activating and CPU Interrupt Sources, but Not DMAC Activating Sources...
Page 156: Handling Dmac Activating Sources But Not Cpu Interrupt Or Dtc Activating Sources
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt or DTC Activating Sources 1. Select the DMAC as a source and set the DME bit to 1. CPU interrupt sources and DTC activating sources are masked regardless of the interrupt priority level register settings or DTC register settings.
Page 157: User Break Controller (Ubc)
Section 7 User Break Controller (UBC) Overview The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC and a user break interrupt is generated according to the conditions of the bus cycle generated by the CPU, DMAC, or DTC. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to easily debug programs without using a large in-circuit emulator.
Page 158: Register Configuration
Module bus interface UBBR UBAMRH UBARH UBAMRL UBARL Break condition comparator User break interrupt Interrupt request generating circuit Interrupt controller UBARH, UBARL: User break address registers H, L UBAMRH, UBAMRL: User break address mask registers H, L UBBR: User break bus cycle register Figure 7.1 User Break Controller Block Diagram 7.1.3 Register Configuration...
Page 159: Register Descriptions
Table 7.1 Register Configuration Initial Access Name Abbr. Value Address Size User break address register H UBARH H'0000 H'FFFF8600 8, 16, 32 User break address register L UBARL H'0000 H'FFFF8602 8, 16, 32 User break address mask register H UBAMRH H'0000 H'FFFF8604 8, 16, 32 User break address mask register L...
Page 160: User Break Address Mask Register (Ubamr)
UBARL: Bit: UBARL UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8 Initial value: R/W: Bit: UBARL UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0 Initial value: R/W: • UBARH Bits 15–0—User Break Address 31–16 (UBA31–UBA16): These bits store the upper bit values (bits 31–16) of the address of the break condition.
Page 161: User Break Bus Cycle Register (Ubbr)
UBAMRL: Bit: UBAMRL UBM15 UBM14 UBM13 UBM12 UBM11 UBM10 UBM9 UBM8 Initial value: R/W: Bit: UBAMRL UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0 Initial value: R/W: • UBAMRH Bits 15–0—User Break Address Mask 31–16 (UBM31–UBM16): These bits designate whether to mask any of the break address 31–16 bits (UBA31–UBA16) established in the UBARH.
Page 162 Bit: — — — — — — — — Initial value: R/W: Bit: Initial value: R/W: Bits 15–8—Reserved: These bits always read as 0. The write value should always be 0. • Bits 7 and 6—CPU Cycle/Peripheral Cycle Select (CP1, CP0): These bits designate break conditions for CPU cycles or peripheral cycles (DMA/DTC cycles).
Page 163 • Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read and/or write cycles. Bit 3: RW1 Bit 2: RW0 Description No user break interrupt occurs (initial value) Break on read cycles Break on write cycles Break on both read and write cycles •...
Page 164: Operation
Operation 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break address register (UBAR), the desired masked bits in the addresses are set in the user break address mask register (UBAMR) and the breaking bus cycle type is set in the user break bus cycle register (UBBR).
Page 165 UBARH/UBARL UBAMRH/UBAMRL Internal address bits 31–0 CPU cycle DMA/DTC cycle Instruction fetch User break interrupt Data access Read cycle Write cycle Byte size Word size Longword size Figure 7.2 Break Condition Judgment Method...
Page 166: Break On On-Chip Memory Instruction Fetch Cycle
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in 1 bus cycle. Therefore, 2 instructions can be retrieved in 1 bus cycle when fetching instructions from on-chip memory. At such times, only 1 bus cycle is generated, but by setting the start addresses of both instructions in the user break address register (UBAR) it is possible to cause independent breaks.
Page 167: Break On Cpu Data Access Cycle
2. Register settings: UBARH = H'0015 UBARL = H'389C UBBR = H'0058 Conditions set: Address: H'0015389C Bus cycle: CPU, instruction fetch, write (operand size not included in conditions) A user break interrupt does not occur because the instruction fetch cycle is not a write cycle. 3.
Page 168: Break On Dma/Dtc Cycle
7.4.3 Break on DMA/DTC Cycle 1. Register settings: UBARH = H'0076 UBARL = H'BCDC UBBR = H'00A7 Conditions set: Address: H'0076BCDC Bus cycle: DMA/DTC, data access, read, longword A user break interrupt occurs when longword data is read from address H'0076BCDC. 2.
Page 169: Contention Between User Break And Exception Handling
Instruction execution: TRAPA instruction execution → Branch destination instruction execution 3. Conditional delay branch instruction, branch taken: BT/S, BF/S Instruction fetch cycles: Conditional delay branch instruction fetch → Next-instruction fetch (delay slot) → Next-instruction overrun fetch → Branch destination instruction fetch Instruction execution: Conditional delay branch instruction execution →...
Page 171: Data Transfer Controller (Dtc)
Section 8 Data Transfer Controller (DTC) Overview The SH7040 Series has an on-chip data transfer controller (DTC), which is activated either by interrupts or software and can perform data transfers. 8.1.1 Features • Arbitrary channel number transfer setting possible  Transfer information can be established for each interrupt source ...
Page 172: Block Diagram
8.1.2 Block Diagram Figure 8.1 shows the DTC block diagram. DTC transfer information is located in memory. On-chip DTMR Register control On-chip DTCR DTSAR On-chip peripheral Activation DTDAR module control DTIAR CPU interrupt request DTER Request source clear control priority DTCSR Interrupt request control...
Page 173: Register Configuration
8.1.3 Register Configuration The DTC has five registers in memory used for storing transfer data: DTMR, DTCR, DTSAR, DTDAR, and DTIAR. It is controlled by the three registers DTER (DTEA–DTEE), DTCSR, and DTBR. The register configurations are listed in table 8.1. Register Configuration * Table 8.1 Name...
Page 174 Bit: Initial value: R/W: — — — — — — — — Bit: Bit name: CHNE DISEL NMIM — — — — Initial value: R/W: — — — — — — — — Note: * Initial value undefined. • Bits 15–14—Source Address Mode 1, 0 (SM1, SM0): These bits designate whether to hold, increment, or decrement the DTSAR after a data transfer.
Page 175 • Bits 11–10—DTC Mode 1, 0 (MD1, MD0): These bits designate the DTC transfer mode. Bit 11 (MD1) Bit 10 (MD0) Description Normal mode Repeat mode Block transfer mode Reserved (setting prohibited) • Bits 9–8—DTC Data Transfer Size 1, 0 (SZ1, SZ0): These bits designate the data size for data transfers.
Page 176: Dtc Source Address Register (Dtsar)
• Bit 5—DTC Interrupt Select (DISEL): This bit designates whether to prohibit or allow interrupt requests to the CPU after one-time DTC transfers. Bit 5 (DISEL) Description Prohibit interrupts to the CPU after DTC data transfer completion if the transfer counter is not 0 (DTC clears the interrupt source flag of the activating source to 0) Allow interrupts to the CPU after DTC data transfer completion (DTC clears the DTER bit for the interrupt of the activating source to 0)
Page 177: Dtc Initial Address Register (Dtiar)
Bit: … … Initial value: … R/W: — — — — — … — — — — — Note: * Initial value is undefined. 8.2.4 DTC Initial Address Register (DTIAR) The DTC initial address register (DTIAR) specifies the initial transfer source/transfer destination address in repeat mode.
Page 178: Dtc Transfer Count Register B (Dtcrb)
Bit: DTCRAH Initial value: R/W: — — — — — — — — Bit: DTCRAL Initial value: R/W: — — — — — — — — Note: * Initial value is undefined. 8.2.6 DTC Transfer Count Register B (DTCRB) The DTCRB is a 16-bit register that designates the block length in block transfer mode. The contents of this register is located in memory.
Page 179: Dtc Control/Status Register (Dtcsr)
For the A mask, overwrite this register as follows: When clearing bit to 0: read the 1 bit to clear and write 0. When setting bit to 1: read the 0 bit to set and write 1. Bit: DTE7 DTE6 DTE5 DTE4 DTE3...
Page 180 • Bit 10—NMI Flag Bit (NMIF): Indicates that an NMI interrupt has occurred. When the NMIF bit is set, DTC transfers are not allowed even if the DTER bit is set to 1. If, however, a transfer has already started with the NMIM bit of the DTMR set to 1, execution will continue until that transfer ends.
Page 181: Dtc Information Base Register (Dtbr)
8.2.9 DTC Information Base Register (DTBR) The DTBR is a 16-bit readable/writable register that specifies the upper 16 bits of the memory address containing DTC transfer information. Always access the DTBR in word or longword units. If it is accessed in byte units the register contents will become undefined at the time of a write, and undefined values will be read out upon reads.
Page 182 Start Initial settings DTMR, DTCR, DTIAR, DTSAR, DTDAR NMIF = AE = 0? Transfer request generated? DTC vector read Transfer information read DTCRA = DTCRA – 1 (normal/block transfer mode) DTCRAL = DTCRAL – 1 (repeat mode) Transfer (1 transfer unit) DTSAR, DTDAR update DTCRB = DTCRB –...
Page 183: Activating Sources
8.3.2 Activating Sources The DTC performs write operations to the DTCSR with either interrupt sources or software as its activating sources. Each interrupt source is designated by specific DTER bits to determine whether it becomes an interrupt request to the CPU or a DTC activating source. When the DISEL bit is 1, an interrupt, established as the DTC activating source, is requested of the CPU after each data transfer in DRC.
Page 184 Through DTC activation, a register information start address is read from the vector table, then register information placed in memory space is read from that register information start address. Always designate register information start addresses in multiples of four. Memory space DTBR Register information start address...
Page 185 Table 8.2 Interrupt Sources and DTC Vector Addresses Source Activating Transfer Transfer Generator Source DTC Vector Address Source Destination Priority DTEA7 Arbitrary * Arbitrary * TGI4A H'00000400–H'00000401 High (CH4) DTEA6 Arbitrary * Arbitrary * TGI4B H'00000402–H'00000403 DTEA5 Arbitrary * Arbitrary * TGI4C H'00000404–H'00000405 DTEA4 Arbitrary *...
Page 186: Register Information Placement
Table 8.2 Interrupt Sources and DTC Vector Addresses (cont) Source Activating Transfer Transfer Generator Source DTC Vector Address Source Destination Priority Arbitrary * SCI0 RXI0 H'00000438–H'00000439 DTED3 RDR0 High DTED2 Arbitrary * TXI0 H'0000043A–H'0000043B TDR0 Arbitrary * SCI1 RXI1 H'0000043C–H'0000043D DTED1 RDR1 DTED0 Arbitrary * TXI1...
Page 187: Normal Mode
Memory space Memory space Memory space Register information DTMR DTMR DTMR start address DTCRA DTCRA DTCRA DTIAR DTCRB Register information DTSAR DTSAR DTSAR DTDAR DTDAR DTDAR Normal mode Repeat mode Block transfer mode Figure 8.5 DTC Register Information Placement in Memory Space 8.3.5 Normal Mode Performs the transfer of one byte, one word, or one longword for each activation.
Page 188: Block Transfer Mode
The total transfer count is specified between 1 and 256. When the specified number of transfers ends, the address register of the designated repeat area is returned to its initial state and the transfer is repeated. Other address registers are consecutively incremented, decremented, or remain fixed. While DISEL = 0, no interrupt request is made to the CPU, even if the transfer with DTCRAL = 1 ends.
Page 189: Operation Timing
Table 8.5 Block Transfer Mode Register Functions Values Written Back upon a Register Function Transfer Information Write DTMR Operation mode DTMR control DTCRA Transfer count DTCRA – 1 DTCRB Block length (Not written back) DTSAR Transfer source (DTS = 0) Increment/ decrement/ fixed address (DTS = 1) DTSAR initial value DTDAR...
Page 190 Table 8.6 Execution State of DTC Register Information Internal Mode Vector Read I Read/Write J Data Read K Data Write L Operation M Normal Repeat Block transfer Note: N: block size (default set values of DTCRB) Table 8.7 State Counts Needed for Execution State chip chip Internal I/O...
Page 191: Dtc Usage Procedure
8.3.10 DTC Usage Procedure The procedure for DTC interrupt activation is as follows: 1. Transfer data (DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR) is located in memory space. 2. Establish the register information start address with DTBR and the DTC vector table. 3.
Page 192: Cautions On Use
5. The RDRF flag of the SSR is set to 1 by each completion of a 1-byte data reception by the SCI, an RxI interrupt is generated, and the DTC is activated. The received data is transferred from RDR to RAM by the DTC, and the RDRF flag is 0 cleared. 6.
Page 193: Cache Memory (Cac)
Section 9 Cache Memory (CAC) Overview The LSI has an on-chip cache memory (CAC) with 1 kbyte of cache data and a 256-entry cache tag. The cache data and cache tag space can be used as on-chip RAM space when the cache is not being used.
Page 194: Block Diagram
9.1.2 Block Diagram Figure 9.2 shows a block diagram of the cache. Cache tag Cache controller Cache data Bus state Cache controller External bus interface CCR: Cache control register Figure 9.2 Cache Block Diagram 9.1.3 Register Configuration The cache has one register, which can be used to control the enabling or disabling of each cache space.
Page 195: Register Explanation
Table 9.1 Register Configuration Initial Access Size Name Abbreviation Value Address (Bits) H'0000 * Cache control register H'FFFF8740 8, 16, 32 Note: * Bits 15–5 are undefined. Register Explanation 9.2.1 Cache Control Register (CCR) The cache control register (CCR) selects the cache enable/disable of each space. The CCR is a 16-bit readable/writable register.
Page 196: Address Array And Data Array
• Bit 3—CS3 Space Cache Enable (CECS3): Selects whether to use CS3 space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 3 (CECS3) Description CS3 space cache disabled (initial value) CS3 space cache enabled •...
Page 197: Cache Address Array Read/Write Space
Table 9.2 Special Cache Space Space Classification Address Size Bus Width Address array H'FFFFF000–H'FFFFF3FF 1 kbyte 32 bit Data array H'FFFFF400–H'FFFFF7FF 1 kbyte 32 bit 9.3.1 Cache Address Array Read/Write Space The cache address array has a compulsory read/write (figure 9.3). 10 9 Upper 22 bits of the address array space address Entry address...
Page 198: Cautions On Use
Cautions on Use 9.4.1 Cache Initialization Always initialize the cache before enabling it. Specifically, use an address array write to write 0 to all valid bits for all entries (256 times), that is,those in the address range H'FFFFF000– H'FFFFF3FF. Writes to the address array or data array by the CPU, DMAC, or DTC are not possible while the cache is enabled.
Page 199 Internal Miss-hit address Address Idle cycle CS assert extension Idle cycle Idle cycle Data Figure 9.5 Cache Fill Timing in Case of Non-Consecutive Cache Miss from Normal Space (No Wait, No CS Assert Extension) Internal Miss-hit address Address CS assert additional extension Data Figure 9.6 Cache Fill Timing in Case of Consecutive Cache Misses from Normal Space (No Wait, CS Assert Extension)
Page 200: Cache Hit After Cache Miss
Internal Miss-hit address Idle cycle Address COLUMN Idle cycle RAS assert extension CASxx Idle cycle Data Figure 9.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space (Normal Mode, TPC = 0, RCD = 0, No Wait) CS space access DRAM access...
Page 201: Section 10 Bus State Controller (Bsc)
Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like DRAM, SRAM, and ROM to be linked directly to the LSI without external circuitry.
Page 202: Block Diagram
10.1.2 Block Diagram Figure 10.1 shows the BSC block diagram. interface WCR1 Wait WAIT control unit WCR2 CS0 to CS3 BCR1 Area control unit BCR2 RDWR WRHH, WRHL RTCSR WRH, WRL CASHH, CASHL Memory RTCNT CASH, CASL control unit CMI interrupt request Comparator RTCOR Interrupt...
Page 203: Pin Configuration
10.1.3 Pin Configuration Table 10.1 shows the bus state controller pin configuration. Table 10.1 Pin Configuration Signal Description A21–A0 Address output (A21–A18 will become input ports with power-on reset) D31–D0 32-bit data bus. D15-D0 are address output and data I/O during address/data multiplex I/O.
Page 204: Register Configuration
10.1.4 Register Configuration The BSC has eight registers. These registers are used to control wait states, bus width, and interfaces with memories like DRAM, ROM, and SRAM, as well as refresh control. The register configurations are listed in table 10.2. All registers are 16 bits.
Page 205: Address Map
10.1.5 Address Map Figure 10.2 shows the address format used by the SH7040 Series. A31–A24 A23, A22 Output address: Output from the address pins CS space selection: Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000 Space selection: Not output externally;...
Page 206 Table 10.3 Address Map for On-Chip ROM Effective Mode Address Space Memory Size Bus Width H'00000000–H'0003FFFF * On-chip ROM On-chip ROM memory 256 kbytes 32 bits H'00040000–H'001FFFFF Reserved Reserved 8/16/32 bits * H'00200000–H'003FFFFF CS0 space Ordinary space 2 Mbytes 8/16/32 bits * H'00400000–H'007FFFFF CS1 space Ordinary space...
Page 207: Description Of Registers
Table 10.4 Address Map for On-Chip ROM Ineffective Mode Address Space Memory Size Bus Width 4 Mbytes 8/16/32 bist * H'00000000–H'003FFFFF CS0 space Ordinary space 4 Mbytes 8/16/32 bits * H'00400000–H'007FFFFF CS1 space Ordinary space 4 Mbytes 8/16/32 bits * H'00800000–H'00BFFFFF CS2 space Ordinary space...
Page 208 Bit: — — — — — — Initial value: R/W: Bit: A3LG A2LG A1LG A0LG A3SZ A2SZ A1SZ A0SZ Initial value: R/W: • Bits 15, 14, 12–9—Reserved: These bits always read as 0. The write value should always be 0. •...
Page 209 • Bit 6—CS2 Space Long Size Specification (A2LG): Specifies the CS2 space bus size. Bit 6 (A2LG) Description According to the A2SZ bit value (initial value) Longword (32 bit) size • Bit 5—CS1 Space Long Size Specification (A1LG): Specifies the CS1 space bus size. Bit 5 (A1LG) Description According to the A1SZ bit value (initial value)
Page 210: Bus Control Register 2 (Bcr2)
• Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size when A1LG = Bit 1 (A1SZ) Description Byte (8 bit) size Word (16 bit) size (initial value) Note: This bit is ignored when A1LG = 1; CS1 space bus size becomes longword (32 bit). •...
Page 211 • Bits 15–8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces.
Page 212 Bit 9 (IW01) Bit 8 (IW00) Description No idle cycle after accessing CS0 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value) • Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when doing consecutive accesses of the same CS space.
Page 213: Wait Control Register 1 (Wcr1)
• Bits 3–0—CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending write data hold time.
Page 214 Bit: Initial value: R/W: Bit: Initial value: R/W: • Bits 15–12—CS3 Space Wait Specification (W33, W32, W31, W30): Specifies the number of waits for CS3 space access. Bit 15 Bit 14 Bit 13 Bit 12 (W33) (W32) (W31) (W30) Description No wait (external wait input disabled) 1 wait external wait input enabled ⋅⋅⋅...
Page 215: Wait Control Register 2 (Wcr2)
• Bits 7–4—CS1 Space Wait Specification (W13, W12, W11, W10): Specifies the number of waits for CS1 space access. Bit 7 Bit 6 Bit 5 Bit 4 (W13) (W12) (W11) (W10) Description No wait (external wait input disabled) 1 wait external wait input enabled ⋅⋅⋅...
Page 216: Dram Area Control Register (Dcr)
• Bits 15–6—Reserved: These bits always read as 0. The write value should always be 0. • Bits 5–4—DRAM Space DMA Single Address Mode Access Wait Specification (DDW1, DDW0): Specifies the number of waits for DRAM space access during DMA single address mode accesses.
Page 217 Bit: TRAS1 TRAS0 DWW1 DWW0 DWR1 DWR0 Initial value: R/W: Bit: — RASD AMX1 AMX0 Initial value: R/W: • Bit 15—RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after RAS is negated before next assert. Bit 15 (TPC) Description 1.5 cycles (initial value) 2.5 cycles...
Page 218 • Bits 11–10—DRAM Write Cycle Wait Count (DWW1–DWW0): Specifies the number of DRAM write cycle column address output cycles. Bit 11 (DWW1) Bit 10 (DWW0) Description 2-cycle (no wait) external wait disabled (initial value) 3-cycle (1 wait) external wait disabled 4-cycle (2 wait) external wait enabled 5-cycle (3 wait) external wait enabled •...
Page 219: Refresh Timer Control/Status Register (Rtcsr)
• Bits 3–2—DRAM Bus Width Specification (SZ1, SZ0): Specifies the DRAM space bus width. Bit 3 (SZ1) Bit 2 (SZ0) Description Byte (8 bits) (initial value) Word (16 bits) Don’t care Longword (32 bits) • Bits 1–0—DRAM Address Multiplex (AMX1–AMX0): Specifies the DRAM address multiplex count.
Page 220 • Bit 6—Compare Match Flag (CMF): This status flag, which indicates that the values of RTCNT and RTCOR match, is set/cleared under the following conditions: Bit 6 (CMF) Description Clear condition: After RTCSR is read when CMF is 1, 0 is written in CMF.
Page 221: Refresh Timer Counter (Rtcnt)
• Bit 0—Refresh Mode (RMD): When the RFSH bit is 1, this bit selects normal refresh or self- refresh. When the RFSH bit is 1, self-refresh mode is entered immediately after the RMD bit is set to 1. When RMD is cleared to 0, a CAS-before-RAS refresh is performed at the interval set in the refresh time constant register (RTCNT).
Page 222: Refresh Time Constant Register (Rtcor)
10.2.8 Refresh Time Constant Register (RTCOR) RTCOR is a 16-bit read/write register that establishes the compare match period with RTCNT. The values of RTCOR and RTCNT are constantly compared. When the values correspond, the compare match flag of RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) of the RTCSR is set to 1 and the RMD bit is 0, a refresh request signal is produced by this match.
Page 223: Accessing Ordinary Space
10.3 Accessing Ordinary Space A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 10.3.1 Basic Timing Figure 10.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are performed in 2 states.
Page 224: Wait State Control
10.3.2 Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR settings (figure 10.4). Address Read Data Write Data Figure 10.4 Wait Timing of Ordinary Space Access (Software Wait Only)
Page 225 When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 10.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when T state shifts to T state.
Page 226: Cs Assert Period Extension
CS Assert Period Extension 10.3.3 Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 10.6. T and T cycles are added respectively before and after the ordinary cycle.
Page 227: Dram Access
10.4 DRAM Access 10.4.1 DRAM Direct Connection When address space A31–A24 = H'01 has been accessed, the corresponding space becomes a 16- Mbyte DRAM space, and the DRAM interface function can be used to directly connect the SH7040 Series to DRAM. Row address and column address are always multiplexed for DRAM space.
Page 228: Basic Timing
10.4.2 Basic Timing The SH7040 Series supports 2 CAS format DRAM access. The DRAM access basic timing is a minimum of 3 cycles for normal mode. Figure 10.7 shows the basic DRAM access timing. DRAM space access is controlled by RAS, CASx, and RDWR signals. The following signals are associated with transfer of these actual byte locations: CASHH (bits 31–24), CASHL (bits 23–16), CASH (bits 15–8), and CASL (bits 7–0).
Page 229: Wait State Control
10.4.3 Wait State Control Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1, DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and writes. The timing with waits inserted is shown in figures 10.8 through 10.11. External waits can be inserted at the time of software waits 2, 3.
Page 230 Address Column Data Write CASx RDWR Data Read CASx RDWR Figure 10.9 DRAM Bus Cycle (Normal Mode, TPC = 1, RCD = 1, Two Waits)
Page 231 Address Column Data Write CASx RDWR Data Read CASx RDWR Figure 10.10 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, Three Waits)
Page 232 Address Column Data Write CASx RDWR Data Read CASx RDWR WAIT Figure 10.11 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD= 0, Two Waits + Wait Due to WAIT Signal)
Page 233: Burst Operation
10.4.4 Burst Operation High-Speed Page Mode: When the burst enable bit (BE) of the DCR is set, burst accesses can be performed using high speed page mode. The timing is shown in figure 10.12. Wait cycles can be inserted during burst accesses by using the DCR. Address Column Column...
Page 234 CS space DRAM access DRAM access access Address Column CS space Column CASx Data Figure 10.13 DRAM Access Normal Operation (RAS Up Mode) CS space DRAM DRAM access access access Address Column CS space Column CASx Data Figure 10.14 RAS Down Mode...
Page 235: Refresh Timing
10.4.5 Refresh Timing The bus state controller is equipped with a function to control refreshes of DRAM. CAS-before- RAS (CBR) refresh or self-refresh can be selected by setting the RTCSR’s RMD bit. CAS-before-RAS Refresh: For CBR refreshes, set the RCR’s RMD bit to 0 and the RFSH bit to 1.
Page 236 Self-Refresh: When both the RMD and RFSH bits of the RTCSR are set to 1, the CAS signal and RAS signal are output and the DRAM enters self-refresh mode, as shown in figure 10.16. Do not access DRAM during self-refreshes, in order to preserve DRAM data. When performing DRAM accesses, first cancel the self-refresh, then access only after doing individual refreshes for all row addresses within the time prescribed for the particular DRAM.
Page 237: Address/Data Multiplex I/O Space Access
10.5 Address/Data Multiplex I/O Space Access When the BCR1 register IOE bit is set to 1, the D15–D0 pins can be used for multiplexed address/data I/O for the CS3 space. Consequently, peripheral LSIs requiring address/data multiplexing can be directly connected to this LSI. Address/data multiplex I/O space bus width is selected by the A14 bit, and is 8 bit when A14 = 0 and 16 bit when A14 = 1.
Page 238: Wait State Control
10.5.2 Wait State Control Setting the WCR controls waits during address/data multiplex I/O space accesses. Software wait and external wait insertion timing is the same as during ordinary space accesses. The timing for one software wait + one external wait inserted is shown in figure 10.18. Address Read Data...
Page 239: Cs Assertion Extension
10.5.3 CS Assertion Extension The timing diagram when setting CS assertion extension during address/data multiplex I/O space access is shown in figure 10.19. Address Read Data input Address output Data WRxx Write Data output Address output Data Figure 10.19 Wait Timing in Address/Data Multiplex I/O Space when CS Assertion Extension is Set 10.6 Waits between Access Cycles...
Page 240 BCR2 and the DIW of the DCR occur. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. Figure 10.20 shows an example of idles between cycles. In this example, 1 idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, 1 idle cycle is inserted.
Page 241: Simplification Of Bus Cycle Start Detection
10.6.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3–CW0 bits of the BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits.
Page 242 to cause the external device to negate the BREQ and return the bus rights to the SH7040 Series. Please note that if the external device does not return the bus rights within the time prescribed for the DRAM refresh interval, this LSI will not be able to perform the refresh operation and the DRAM contents cannot be guaranteed.
Page 243: Memory Connection Examples
10.8 Memory Connection Examples Figures 10.23–10.31 show examples of the memory connections. As A21–A18 become input ports in power-on reset, they should be handled (e.g. pulled down) as necessary. 32k × 8 bits SH704x A0–A14 A0–A14 D0–D7 I/O0–I/O7 Figure 10.23 8-Bit Data Bus Width ROM Connection 256k ×...
Page 244 256k × 16 bits SH704x A2–A19 A0–A17 D16–D31 I/O0–I/O15 D0–D15 A0–A17 I/O0–I/O15 Figure 10.25 32-Bit Data Bus Width ROM Connection 123k × 8 bits SH704x SRAM A0–A16 A0–A16 D0–D7 I/O0–I/O7 Figure 10.26 8-Bit Data Bus Width SRAM Connection...
Page 245 128k × 8 bits SH704x SRAM A1–A17 A0–A16 D8–D15 I/O0–I/O7 D0–D7 A0–A16 I/O0–I/O7 Figure 10.27 16-Bit Data Bus Width SRAM Connection...
Page 246 128k × 8 bits SH704x SRAM A2–A18 A0–A16 WRHH D24–D31 I/O0–I/O7 WRHL D16–D23 D8–D15 A0–A16 D0–D7 I/O0–I/O7 A0–A16 I/O0–I/O7 A0–A16 I/O0–I/O7 Figure 10.28 32-Bit Data Bus Width SRAM Connection...
Page 247 512k × 8 bits SH704x DRAM RDWR A0–A9 A0–A9 CASL AD0–AD7 I/O0–I/O7 Figure 10.29 8-Bit Data Bus Width DRAM Connection 256k × 16 bits SH704x DRAM RDWR A0–A8 A1–A9 CASH UCAS CASL LCAS AD0–AD15 I/O0–I/O15 Figure 10.30 16-Bit Data Bus Width DRAM Connection...
Page 248: On-Chip Peripheral I/O Register Access
256k × 16 bits SH704x DRAM RDWR A2–A10 A0–A8 CASHH UCAS CASHL LCAS AD16–AD31 I/O0–I/O15 CASH CASL AD0–AD15 A0–A8 UCAS LCAS I/O0–I/O15 Figure 10.31 32-Bit Data Bus Width DRAM Connection 10.9 On-Chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in table 10.6. Table 10.6 On-Chip Peripheral I/O Register Access On-chip MTU,...
Page 249: Cpu Operation When Program Is In External Memory
Cycles in which Bus is not Released (a) One bus cycle: The bus is never released during a single bus cycle. For example, in the case of a longword read (or write) in 8-bit normal space, the four memory accesses to the 8-bit normal space constitute a single bus cycle, and the bus is never released during this period.
Page 251: Section 11 Direct Memory Access Controller (Dmac)
Section 11 Direct Memory Access Controller (DMAC) 11.1 Overview The SH7040 Series includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (transfer request acknowledge signal), external memories, memory- mapped external devices, and on-chip peripheral modules (except for the DMAC, DTC, BSC, and UBC).
Page 252  Channel 3: Dual address mode only. Direct address transfer mode and indirect address transfer mode selectable. • Reload function: Enables automatic reloading of the value set in the first source address register every fourth DMA transfer. This function can be executed on channel 2 only. •...
Page 253: Block Diagram
11.1.2 Block Diagram Figure 11.1 is a block diagram of the DMAC. DMAC module Circuit SARn On-chip ROM control Register DARn On-chip RAM control On-chip DMATCRn peripheral Activation module control CHCRn DMAOR DREQ0, DREQ1 Request SCI0, SCI1 priority A/D converter * control DEIn DACK0, DACK1...
Page 254: Pin Configuration
11.1.3 Pin Configuration Table 11.1 shows the DMAC pins. Table 11.1 DMAC Pin Configuration Channel Name Symbol Function DREQ0 DMA transfer request DMA transfer request input from external device to channel 0 DMA transfer request DACK0 DMA transfer strobe output from acknowledge channel 0 to external device DREQ0 acceptance...
Page 255: Register Configuration
11.1.4 Register Configuration Table 11.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels Table 11.2 DMAC Registers Chan- Abbrevi- Initial Register Access Name ation Value...
Page 256: Register Descriptions
Table 11.2 DMAC Registers (cont) Chan- Abbrevi- Initial Register Access Name ation Value Address Size Size 16, 32 * DMA transfer count DMATCR2 R/W Undefined H'FFFF86E8 32 bit (cont) register 2 R/W * 16, 32 * DMA channel control CHCR2 H'00000000 H'FFFF86EC 32 bit register 2 16, 32 *...
Page 257: Dma Destination Address Registers 0-3 (Dar0-Dar3)
Bit: Initial value: — — — — — — — — R/W: Bit: … … … … Initial value: — — — … … — — — R/W: … … 11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify the destination address of a DMA transfer.
Page 258: Dma Transfer Count Registers 0-3 (Dmatcr0-Dmatcr3)
11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count). Specifying a H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 transfers.
Page 259: Dma Channel Control Registers 0-3 (Chcr0-Chcr3)
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA channel control registers 0–3 (CHCR0–CHCR3) is a 32-bit read/write register where the operation and transmission of each channel is designated. They are initialized by a power-on reset and in software standby mode. There is no initializing with manual reset. Bit: —...
Page 260 • Bit 19—Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 for CHCR0, CHCR1, and CHCR3, and cannot be modified. Bit 19: RO Description Does not reload source address (initial value)
Page 261 • Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): These bits specify increment/decrement of the DMA transfer destination address. These bit specifications are ignored when transferring data from an external device to address space in single address mode.
Page 262 • Bits 11–8—Resource Select 3–0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: Bit 8: Description External request, dual address mode (initial value) Prohibited External request, single address mode. External address space → external device. External request, single address mode.
Page 263 • Bit 5—Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 5: TM Description Cycle steal mode (initial value) Burst mode • Bits 4 and 3—Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer. Bit 4: TS1 Bit 3: TS0 Description Specifies byte size (8 bits) (initial value)
Page 264: Dmac Operation Register (Dmaor)
• Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE Description Operation of the corresponding channel disabled (initial value) Operation of the corresponding channel enabled Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3–RS0 settings). With an external request or on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is enabled.
Page 265 • Bits 9–8—Priority Mode 1 and 0 (PR1 and PR0): These bits determine the priority level of channels for execution when transfer requests are made for several channels simultaneously. Bit 9: PR1 Bit 8: PR0 Description CH0 > CH1 > CH2 > CH3 (initial value) CH0 >...
Page 266: Operation
• Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are suspended.
Page 267 Figure 11.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? Transfer request occurs? * Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR –...
Page 268: Dma Transfer Requests
11.3.2 DMA Transfer Requests DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.
Page 269 transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. The transfer request source need not be the data transfer source or transfer destination. However, when the transfer request is set by RxI (transfer request because SCI’s receive data is full), the transfer source must be the SCI’s receive data register (RDR).
Page 270: Channel Priority
11.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order, either in a fixed mode or in round robin mode. These modes are selected by priority bits PR1 and PR0 in the DMA operation register (DMAOR).
Page 271 Transfer on channel 0 Initial priority setting Channel 0 is given the lowest CH0 > CH1 > CH2 > CH3 priority. CH1 > CH2 > CH3 > CH0 Priority after transfer Transfer on channel 1 CH0 > CH1 > CH2 > CH3 Initial priority setting When channel 1 is given the lowest priority, the priority...
Page 272 Figure 11.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The DMAC operates in the following manner under these circumstances: 1.
Page 273: Dma Transfer Types
11.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 11.5. It can operate in the single address mode, in which either the transfer source or destination is accessed using an acknowledge signal, or dual access mode, in which both the transfer source and destination addresses are output. The dual access mode consists of a direct address mode, in which the output address value is the object of a direct data transfer, and an indirect address mode, in which the output address value is not the object of the data transfer, but the value stored at the output address becomes the transfer object...
Page 274 External address bus External data bus This LSI External memory DMAC External device with DACK DACK DREQ : Data flow Figure 11.5 Data Flow in Single Address Mode Two types of transfers are possible in the single address mode: (a) transfers between external devices with DACK and memory-mapped external devices, and (b) transfers between external devices with DACK and external memory.
Page 275: Dual Address Mode
A21–A0 Address output to external memory space Data that is output from the external D15–D0 device with DACK WR signal to external memory space DACK signal to external devices with DACK DACK (active low) a. External device with DACK to external memory space A21–A0 Address output to external memory space Data that is output from external memory space...
Page 276 1st bus cycle DMAC Memory Transfer source module Transfer destination Data buffer module The SAR value is taken as the address, and data is read from the transfer source module and stored temporarily in the DMAC. 2nd bus cycle DMAC Memory Transfer source module...
Page 277 Transfer source Transfer destination A21–A0 address address D15–D0 WRH, WRL DACK Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: Transfer between external memories with DACK are output during read cycle. Figure 11.8 Example of Direct Address Transfer Timing in Dual Address Mode...
Page 278 Indirect Address Transfer Mode: In this mode the memory address storing the data you actually want to transfer is specified in DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer mode, the DMAC internal transfer source address register value is read first.
Page 279 1st, 2nd bus cycles DMAC SAR3 Memory DAR3 Transfer source module Temporary buffer Transfer destination Data module buffer The SAR3 value is taken as the address, memory data is read, and the value is stored in the temporary buffer. Since the value read at this time is used as the address, it must be 32 bits. When external connection data bus is 16 bits, two bus cycles are required.
Page 280 Transfer Transfer Transfer Indirect A21–A0 source source destination address address (H) address (L) address Indirect Indirect Transfer Transfer D15–D0 address (H) address (L) data data Internal Indirect Transfer source address address * address Internal Transfer Transfer Indirect address * data bus data data DMAC...
Page 281 Figure 11.11 shows an example of timing in indirect address mode when transfer source and indirect address storage locations are in internal memory, the transfer destination is an on-chip peripheral module with 2-cycle access space, and transfer data is 8-bit. Since the indirect address storage destination and the transfer source are in internal memory, these can be accessed in one cycle.
Page 282: Bus Modes
11.3.7 Bus Modes Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes: cycle steal and burst. Cycle-Steal Mode: In the cycle steal mode, the bus right is given to another bus master after each one-transfer-unit (byte, word, or longword) DMAC transfer.
Page 283: Relationship Between Request Modes And Bus Modes By Dma Transfer Category
11.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 11.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.6 Relationship of Request Modes and Bus Modes by DMA Transfer Category Bus * Address Request...
Page 284: Bus Mode And Channel Priority Order
11.3.9 Bus Mode and Channel Priority Order When a given channel is transferring in burst mode, and a transfer request is issued to channel 0, which has a higher priority ranking, transfer on channel 0 begins immediately. If the priority level setting is fixed mode (CH0 >...
Page 285 DRAK is output once for the first DREQ sampling, irrespective of transfer mode or DREQ detection method. In burst mode, using edge detection, DREQ is sampled for the first cycle only, so DRAK is also output for the first cycle only. Therefore, the DREQ signal negate timing can be ascertained, and this facilitates handshake operations of transfer requests with the DMAC.
Page 286 Figure 11.15 Cycle Steal, Dual Address, and Level Detection (Fastest Operation)
Page 287 Figure 11.16 Cycle Steal, Dual Address, and Level Detection (Normal Operation)
Page 288 Figures 11.17 and 11.18 show cycle steal mode and single address mode. In this case, transfer begins at earliest three cycles after the first DREQ sampling. The second sampling begins from the start of the transfer one bus cycle before the start of the first DMAC transfer. In single address mode, the DACK signal is output during the DMAC transfer period.
Page 289 Figure 11.17 Cycle Steal, Single Address, and Level Detection (Fastest Operation)
Page 290 Figure 11.18 Cycle Steal, Single Address, and Level Detection (Normal Operation)
Page 291 Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with dual address and level detection is virtually the same as that of cycle steal mode. For example, DMAC transfer begins (figure 11.19), at the earliest, three cycles after the timing of the first sampling.
Page 292 Figure 11.19 Burst Mode, Dual Address, and Level Detection (Fastest Operation)
Page 293 Figure 11.20 Burst Mode, Dual Address, and Level Detection (Normal Operation)
Page 294 Burst Mode, Single Address, and Level Detection: DREQ sampling timing in burst mode with single address and level detection is shown in figures 11.21 and 11.22. In burst mode with single address and level detection, a dummy cycle is inserted as one bus cycle, at the earliest, three cycles after timing of the first sampling.
Page 295 Figure 11.21 Burst Mode, Single Address, and Level Detection (Fastest Operation)
Page 296 Figure 11.22 Burst Mode, Single Address, and Level Detection (Normal Operation)
Page 297 Burst Mode, Dual Address, and Edge Detection: In burst mode with dual address and edge detection, DREQ sampling is conducted only on the first cycle. In figure 11.23, DMAC transfer begins, at the earliest, three cycles after the timing of the first sampling.
Page 298 Figure 11.23 Burst Mode, Dual Address, and Edge Detection...
Page 299 Burst Mode, Single Address, and Edge Detection: In burst mode with single address and edge detection, DREQ sampling is conducted only on the first cycle. In figure 11.24, a dummy cycle is inserted, at the earliest, three cycles after the timing for the first sampling. During this period, data is undefined, and DACK is not output.
Page 300 Figure 11.24 Burst Mode, Single Address and Edge Detection...
Page 301: 11.3.11 Source Address Reload Function
11.3.11 Source Address Reload Function Channel 2 has a source address reload function. This returns to the first value set in the source address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 11.25 illustrates this operation.
Page 302: 11.3.12 Dma Transfer Ending Conditions
The reload function can be executed whether the transfer data size is 8, 16, or 32 bits. DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore, when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2.
Page 303: 11.3.13 Dmac Access From Cpu
When the processing of a one unit transfer is complete. In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and TCR values are updated.
Page 304: Example Of Dma Transfer Between External Ram And External Device With Dack
11.4.2 Example of DMA Transfer between External RAM and External Device with DACK In this example, an external request, serial address mode transfer with external memory as the transfer source and an external device with DACK as the transfer destination is executed using DMAC channel 1.
Page 305 Table 11.9 Transfer Conditions and Register Set Values for Transfer between A/D Converter and On-Chip Memory Transfer Conditions Register Value Transfer source: on-chip A/D converter ch0 SAR2 H'FFFF83F0 Transfer destination: on-chip memory DAR2 H'FFFFF000 Transfer count: 128 times (reload count 32 times) DMATCR2 H'00000080 Transfer source address: incremented...
Page 306: Example Of Dma Transfer Between A/D Converter And Internal Memory (Address Reload On) (A Mask)
Table 11.10 DMAC Internal Status Item Address Reload On Address Reload Off H'FFFF83F0 H'FFFF83F4 H'FFFFF004 H'FFFFF004 DMATCR H'0000007C H'0000007C Bus rights Released Maintained DMAC operation Halted Processing continues Interrupts Not issued Not issued Transfer request source flag clear Executed Not executed Notes: 1.
Page 307 Table 11.11 Transfer Conditions and Register Set Values for Transfer between A/D Converter (A/D1) and Internal Memory Transfer Conditions Register Value Transfer source: on-chip A/D converter (A/D1) SAR2 H'FFFF8408 Transfer destination: internal memory DAR2 H'FFFFF000 Transfer count: 128 times (reload count 32 times) DMATCR2 H'00000080 Transfer source address: incremented...
Page 308: Example Of Dma Transfer Between External Memory And Sci1 Send Side (Indirect Address On)
Table 11.12 DMAC Internal Status Item Address Reload On Address Reload Off H'FFFF8408 H'FFFF840C H'FFFFF004 H'FFFFF004 DMATCR H'0000007C H'0000007C Bus rights Released Maintained DMAC operation Halted Processing continues Interrupts Not issued Not issued Transfer request source flag clear Executed Not executed Notes: 1.
Page 309 Table 11.13 Transfer Conditions and Register Set Values for Transfer between External Memory and SCI1 Sending Side Transfer Conditions Register Value Transfer source: external memory SAR3 H'00400000 Value stored in address H'00400000 — H'00450000 Value stored in address H'00450000 — H'55 Transfer destination: on-chip SCI TDR1 DAR3...
Page 310: Cautions On Use
11.5 Cautions on Use 1. Other than the DMA operation register (DMAOR) accessing in word (16-bit) units, access all registers in word (16-bit) or longword (32-bit) units. 2. When rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (set the DE bit to 0 before doing rewrites with a CHCR byte address).
Page 311: Section 12 Multifunction Timer Pulse Unit (Mtu)
Section 12 Multifunction Timer Pulse Unit (MTU) 12.1 Overview The SuperH microprocessor has an on-chip 16-bit multifunction timer pulse unit (MTU) with five channels of 16-bit timers. 12.1.1 Features • Can process a maximum of sixteen different pulse outputs and inputs. •...
Page 312  Complementary PWM mode: By combining channels 3 and 4, a triangle wave comparator type six-phase PWM output is possible with non-overlapping times. • High speed access via internal 16-bit bus • Twenty-three interrupt sources  Channels 0, 3, and 4 have four compare-match/input capture interrupts and one overflow interrupt which can be requested independently.
Page 313 Table 12.1 summarizes the MTU functions. Table 12.1 MTU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Internal: φ/1, φ/4, φ/16, φ/64, φ/256, φ/1024 Counter clocks External: Eight to each channel from TCLKA, TCLKB, TCLKC, and TCLKD General registers TGR0A TGR1A...
Page 314: Block Diagram
Table 12.1 MTU Functions (cont) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Hard DTC TGR compare- TGR compare- TGR compare- TGR compare- TGR compare- activation match or input match or input match or input match or input match or input capture capture...
Page 315 (I/O pins) Channel 3: TIOC3A TIOC3B TIOC3C (Interrupt TIOC3D request signals) Channel 3: Channel 4: TGI3A TIOC4A TGI3B TIOC4B TGI3C TIOC4C TGI3D TIOC4D TGI3V Channel 4: TGI4A TGI4B TGI4C (Clock input) TGI4D Internal clock: TGI4V φ/1 φ/4 φ/16 Internal data bus φ/64 A/D conversion φ/256...
Page 316: Pin Configuration
12.1.3 Pin Configuration Table 12.2 summarizes the MTU pins. Table 12.2 Pin Configuration Channel Name Pin Name I/O Function Shared Clock input A TCLKA Clock A input pin (A-phase input pin in channel 1 phase counting mode) Clock input B TCLKB Clock B input pin (B-phase input pin in channel 1 phase counting mode)
Page 317 Table 12.2 Pin Configuration (cont) Channel Name Pin Name I/O Function Input TIOC3A I/O TGR3A input capture input/output compare capture/output output/PWM output pin compare-match 3A In complementary PWM/reset synchronous PWM mode, 1/2 PWM period toggle output pin Input TIOC3B I/O TGR3B input capture input/output compare output capture/output compare-match 3B In complementary PWM/reset synchronous PWM...
Page 318: Register Configuration
12.1.4 Register Configuration Table 12.3 summarizes the MTU register configuration. Table 12.3 Register Configuration Chan- Abbrevi- Initial Access Size (Bits) * Name ation Value Address Shared Timer start register TSTR H'00 H'FFFF8240 8, 16, 32 Timer synchro register TSYR H'00 H'FFFF8241 Timer control register 0 TCR0...
Page 319 Table 12.3 Register Configuration (cont) Chan- Abbrevi- Initial Access Size (Bits) * Name ation Value Address Timer control register 2 TCR2 H'00 H'FFFF82A0 8, 16, 32 Timer mode register 2 TMDR2 R/W H'C0 H'FFFF82A1 Timer I/O control register 2 TIOR2 H'00 H'FFFF82A2 Timer interrupt enable...
Page 320 Table 12.3 Register Configuration (cont) Chan- Abbrevi- Initial Access Size (Bits) * Name ation Value Address R/W * 4 (cont) Timer counter 4 TCNT4 H'0000 H'FFFF8212 16, 32 R/W * General register 4A TGR4A H'FFFF H'FFFF821C R/W * General register 4B TGR4B H'FFFF H'FFFF821E...
Page 321: Mtu Register Descriptions
12.2 MTU Register Descriptions 12.2.1 Timer Control Register (TCR) The TCR is an 8-bit read/write register for controlling the TCNT counter for each channel. The MTU has five TCR registers, one for each of the channels 0 to 4. TCR is initialized to H'00 by a power-on reset or the standby mode.
Page 322 Channels 0, 3, 4: Bit 7: Bit 6: Bit 5: CCLR2 CCLR1 CCLR0 Description TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync.
Page 323 Bit 4: Bit 3: CKEG1 CKEG0 Description Count on rising edges (initial value) Count on falling edges Count on both rising and falling edges Notes: 1. X: 0 or 1, don’t care. 2. Internal clock edge selection is effective when the input clock is φ/4 or slower. When ø/1 or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation complies with the initial value (count on rising edges).
Page 324 Channel 1: Bit 2: Bit 1: Bit 0: TPSC2 TPSC1 TPSC0 Description Internal clock: count with φ/1 (initial value) Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input Internal clock: count with φ/256 Count with the TCNT2 overflow/underflow...
Page 325 Channel 3: Bit 2: Bit 1: Bit 0: TPSC2 TPSC1 TPSC0 Description Internal clock: count with φ/1 (initial value) Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 Internal clock: count with φ/256 Internal clock: count with φ/1024 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input Channel 4:...
Page 326: Timer Mode Register (Tmdr)
12.2.2 Timer Mode Register (TMDR) The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU has five TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset or the standby mode. Manual reset does not initialize TMDR. Channels 0, 3, 4: TMDR0, TMDR3, TMDR4: Bit: —...
Page 327 • Bit 4—Buffer Operation A (BFA): Designates whether to use the TGRA register for normal operation, or buffer operation in combination with the TGRC register. When using TGRC as a buffer register, no TGRC register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRC registers.
Page 328: Timer I/O Control Register (Tior)
12.2.3 Timer I/O Control Register (TIOR) The TIOR is a register that controls the TGR. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. TIOR is initialized to H'00 by a power-on reset or the standby mode.
Page 329 Channel 0 (TIOR0H Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR0B register function. Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description TGR0B Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 330 • Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR0A register function. Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description TGR0A Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 331 Channel 0 (TIOR0L Register): • Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGR0D register function. Bit 7: Bit 6: Bit 5: Bit 4: IOD3 IOD2 IOD1 IOD0 Description TGR0D Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 332 • Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR0C register function. Bit 3: Bit 2: Bit 1: Bit 0: IOC3 IOC2 IOC1 IOC0 Description TGR0C Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 333 Channel 1 (TIOR1 Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR1B register function. Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description TGR1B Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 334 • Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR1A register function. Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description TGR1A Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 335 Channel 2 (TIOR2 Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR2B register function. Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description TGR2B Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 336 • Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR2A register function. Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description TGR2A Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 337 Channel 3 (TIOR3H Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR3B register function. Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description TGR3B Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 338 • Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR3A register function. Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description TGR3A Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 339 Channel 3 (TIOR3L Register): • Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGR4D register function. Bit 7: Bit 6: Bit 5: Bit 4: IOD3 IOD2 IOD1 IOD0 Description TGR3D Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 340 • Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR4C register function. Bit 3: Bit 2: Bit 1: Bit 0: IOC3 IOC2 IOC1 IOC0 Description TGR3C Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 341 Channel 4 (TIOR4H Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR4B register function. Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description TGR4B Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 342 • Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR4A register function. Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description TGR4A Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 343 Channel 4 (TIOR4L Register): • Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGR4D register function. Bit 7: Bit 6: Bit 5: Bit 4: IOD3 IOD2 IOD1 IOD0 Description TGR4D Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match...
Page 344: Timer Interrupt Enable Register (Tier)
• Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR4C register function. Bit 3: Bit 2: Bit 1: Bit 0: IOC3 IOC2 IOC1 IOC0 Description TGR4C Output disabled (initial value) is an Initial Output 0 on compare-match output output Output 1 on compare-match compare is 0...
Page 345 Channels 1, 2: TIER1, TIER2: Bit: TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value: R/W: Channels 3, 4: TIER3, TIER4: Bit: TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value: R/W: • Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an A/D conversion start request by a TGRA register input capture/compare-match.
Page 346 • Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when the TGFD bit of the channel 0, 3, 4 TSR register is set to 1. This bit is reserved for channels 1 and 2. It always reads as 1. The write value should always be 1.
Page 347: Timer Status Register (Tsr)
12.2.5 Timer Status Register (TSR) The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The MTU has five TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset or by standby mode.
Page 348 • Bit 5—Underflow Flag (TCFU): This status flag indicates the occurrence of a channel 1, 2 TCNT counter underflow. This bit is reserved in channels 0, 3, and 4. This bit always reads as 0. The write value should always be 0. Bit 5: TCFU Description Clear condition: With TCFU=1, a 0 write to TCFU after reading it (initial...
Page 349 • Bit 2—Input Capture/Output Compare Flag C (TGFC): This status flag indicates the occurrence of a channel 0, 3, or 4 TGRC register input capture or compare-match. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0.
Page 350: Timer Counters (Tcnt)
12.2.6 Timer Counters (TCNT) The timer counters (TCNT) are 16-bit counters, with one for each channel, for a total of five. The TCNT are initialized to H'0000 by a power-on reset and when in standby mode. Manual reset does not initialize TCNT. Accessing the TCNT counters in 8-bit units is prohibited. Always access in 16-bit units.
Page 351: Timer General Register (Tgr)
12.2.7 Timer General Register (TGR) Each timer general register (TGR) is a 16-bit register that can function as either an output compare register or an input capture register. There are a total of sixteen TGR, four each for channels 0, 3, and 4, and two each for channels 1 and 2.
Page 352: Timer Synchro Register (Tsyr)
Counter Start Channel CST4 Channel 4 (TCNT4) CST3 Channel 3 (TCNT3) CST2 Channel 2 (TCNT2) CST1 Channel 1 (TCNT1) CST0 Channel 0 (TCNT0) Bit n: CSTn Description TCNTn count is halted (initial value) TCNTn counts Note: n = 4 to 0. However, CST4 is bit 7, CST3 is bit 6. If 0 is written to the CST bit during operation with the TIOC pin in output status, the counter stops, but the TIOC pin output compare output level is maintained.
Page 353: Timer Output Master Enable Register (Toer)
Counter Start Channel SYNC4 Channel 4 (TCNT4) SYNC3 Channel 3 (TCNT3) SYNC2 Channel 2 (TCNT2) SYNC1 Channel 1 (TCNT1) SYNC0 Channel 0 (TCNT0) Bit n: SYNCn Description Timer counter (TCNTn) independent operation (initial value) (TCNTn preset/clear unrelated to other channels) Timer counter synchronous operation * TCNTn synchronous preset/ synchronous clear * possible...
Page 354 • Bit 5—Master Enable TIOC4D (OE4D): Enables or disables the TIOC4D pin MTU output. Bit 5: OE4D Description Disable TIOC4D pin MTU output (initial value) Enable TIOC4D pin MTU output • Bit 4—Master Enable TIOC4C (OE4C): Enables or disables the TIOC4C pin MTU output. Bit 4: OE4C Description Disable TIOC4C pin MTU output (initial value)
Page 355: Timer Output Control Register (Tocr)
12.2.11 Timer Output Control Register (TOCR) The timer output control register (TOCR) enables/disables PWM synchronized toggle output in complementary PWM mode and reset sync PWM mode, and controls output level inversion of PWM output. The TOCR is initialized to H'00 by a power-on reset or in the standby mode. Manual reset does not initialize TOCR.
Page 356: Timer Gate Control Register (Tgcr)
Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT3 and TCNT4 values TGR3A TCNT4 TCNT3 TGR4A TDDR H'0000 Time Compare match output (up count) Compare match Initial Positive output (down count) Active level output phase output...
Page 357 • Bit 6—Brushless DC Motor (BDC): Selects gate signal output/chopping output function for brushless DC motor control. Bit 6: BDC Description Ordinary output (initial value) Gate signal/chopping output for brushless DC motor • Bit 5—Reverse Phase Output (N): Selects whether to output gate signals directly to the reverse phase pin (TIOC3D, TIOC4C, and TIOC4D) output, or to output by chopping the gate signal and the complementary PWM/reset-synchronized PWM output.
Page 358: Timer Subcounter (Tcnts)
• Bits 2–0—Output Phase Switch 2–0 (WF, VF, UF): These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2–0 is a substitute for external input. Function TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D Bit 2:...
Page 359: Timer Dead Time Data Register (Tddr)
12.2.14 Timer Dead Time Data Register (TDDR) The timer dead time data register (TDDR) is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT3 and TCNT4 counter offset values. In complementary PWM mode, when the TCNT3 and TCNT4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT3 counter and the count operation starts.
Page 360: Timer Period Buffer Register (Tcbr)
12.2.16 Timer Period Buffer Register (TCBR) The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing established in the TMDR register. The TCBR register is initialized to H'FFFF by a power-on reset or in standby mode.
Page 361: 8-Bit Registers
12.3.2 8-Bit Registers All registers other than the TCNT and general registers (TGR) are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figures 12.4 ,12.5, and 12.6). Internal data bus Upper 8 bits Module data bus...
Page 362: Operation
12.4 Operation 12.4.1 Overview The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external event counter.
Page 363: Basic Functions
Complementary PWM Mode: Three-phase complementary positive and negative PWM waveforms whose positive and negative phases do not overlap can be obtained using channels 3 and 4. When set for complementary PWM mode, TGR3A, TGR3B, TGR4A, and TGR4B become output compare registers. The TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins also automatically become PWM output pins while TCNT3 and TCNT4 become up/down counters.
Page 364 Counting mode selection Select counter clock Free-running counter Periodic counter Select counter clear source Select output compare register Set period Start counting Start counting Periodic counter Free-running counter Figure 12.7 Procedure for Selecting the Counting Operation Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves them all in the free-running mode.
Page 365 Periodic Counter Operation Example: Periodic counter operation is obtained for a given channel’s TCNT by selecting compare-match as a TCNT clear source. Set the TGR register for period setting to output compare register and select counter clear upon compare-match using the CCLR2–CCLR0 bits of the timer control register (TCR).
Page 366 Output selection Select waveform output mode Select output timing Start counting Figure 12.10 Procedure for Selecting Compare Match Waveform Output Operation Waveform Output Operation (0 Output/1 Output): Figure 12.11 shows 0 output/1 output. In the example, TCNT is a free-running counter, 1 is output upon compare-match A and 0 is output upon compare-match B.
Page 367 TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle TIOCA output Toggle TIOCB output Figure 12.12 Example of Toggle Output Input Capture Function: In the input capture mode, the TCNT value is transferred into the TGR register when the input edge is detected at the input capture/output compare pin (TIOC).
Page 368: Synchronous Operation
Input Capture Operation: Figure 12.14 shows input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture input edges. In the example, TCNT is set to clear at the input capture of the TGRB register. Counter cleared TCNT value by TIOCB input...
Page 369 Procedure for Selecting the Synchronizing Mode (Figure 12.15): 1. Set 1 in the SYNC bit of the timer synchro register (TSYR) to use the corresponding channel in the synchronizing mode. 2. When a value is written in the TCNT in any of the synchronized channels, the same value is simultaneously written in the TCNT in the other channels.
Page 370 Synchronized Operation: Figure 12.16 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter clear upon compare-match with TGR0B. Channels 1 and 2 are set for synchronous counter clears by synchronous presets and TGR0B register compare-matches.
Page 371: Buffer Operation
12.4.4 Buffer Operation Buffer operation is a function of channels 0, 3, and 4. TGRC and TGRD can be used as buffer registers. Table 12.5 shows the register combinations for buffer operation. Table 12.5 Register Combinations Channel General Register Buffer Register TGR0A TGR0C TGR0B...
Page 372 Procedure for Setting Buffer Mode (Figure 12.19): 1. Use the timer I/O control register (TIOR) to set the TGR as either an input capture or output compare register. 2. Use the timer mode register (TMDR) BFA, and BFB bits to set the TGR for buffer mode. 3.
Page 373 TCNT value TGR0B H'0520 H'0450 H'0200 TGR0A H'0000 Time H'0200 H'0450 H'0520 TGR0C Transfer TGR0A H'0200 H'0450 TIOC0A Figure 12.20 Buffer Operation Example (Output Compare Register) Buffer Operation Examples—when TGR Is an Input Capture Register: Figure 12.21 shows an example of TGRA set as an input capture register with the TGRA and TGRB registers set for buffer operation.
Page 374: Cascade Connection Mode
12.4.5 Cascade Connection Mode Cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. This function operates by using the TPSC2–TPSC0 bits of the TCR register to set the channel 1 counter clock to count by TCNT2 counter overflow/underflow.
Page 375: Pwm Mode
Cascade Connection Operation Examples—Phase Counting Mode: Figure 12.23 shows an example of operation when the TCNT1 counter is set to count on TCNT2 overflow/underflow and channel 2 is set to phase counting mode. The TCNT1 counter increments with a TCNT2 counter overflow and decrements with a TCNT2 underflow.
Page 376 Table 12.7 lists the combinations of PWM output pins and registers. Table 12.7 Combinations of PWM Output Pins and Registers Output Pin Channel Register PWM Mode 1 PWM Mode 2 0 (AB pair) TGR0A TIOC0A TIOC 0A TGR0B TIOC 0B 0 (CD pair) TGR0C TIOC0C...
Page 377 PWM mode Select counter clock Select counter clear source Select waveform output level Set TGR Select PWM mode Start counting PWM mode Figure 12.24 Procedure for Selecting the PWM Mode PWM Mode Operation Examples—PWM Mode 1 (Figure 12.25): A TGRA register compare- match is used as a TCNT counter clear source, the TGRA register initial output value and output compare output value are both 0, and the TGRB register output compare output value is a 1.
Page 378 PWM Mode Operation Examples—PWM Mode 2 (Figure 12.26): Channels 0 and 1 are set for synchronous operation, TGR1B register compare-match is used as a TCNT counter clear source, the other TGR register initial output value is 0 and output compare output value is 1, and a 5-phase PWM waveform is output.
Page 379: Phase Counting Mode
100% Duty Cycle: Figure 12.28 shows an example of a 100% duty cycle PWM waveform output in PWM mode. In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter. TCNT value Output does not change if period register and duty cycle register compare matches occur simultaneously...
Page 380 The TSR register TCFD bit is a count direction flag. Read the TCFD flag to confirm whether the TCNT is incrementing or decrementing. Table 12.8 shows the correspondence between channels and external clock pins. Table 12.8 Phase Counting Mode Clock Input Pins Channel A Phase Input Pin B Phase Input Pin...
Page 381 TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Increment Decrement Time Figure 12.30 Phase Counting Mode 1 Operation Table 12.9 Phase Count Mode 1 Up/Down Counting Conditions TCLKA (Channel 1) TCLKB (Channel 1) TCLKC (Channel 2) TCLKD (Channel 2) Operation 1 (high level)
Page 382 Phase Count Mode 2: Figure 12.31 shows an example of phase counting mode 2 operation. Table 12.10 lists the up counting and down counting conditions for the TCNT. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Increment Decrement...
Page 383 Phase Count Mode 3: Figure 12.32 shows an example of phase counting mode 3 operation. Table 12.11 lists the up counting and down counting conditions for the TCNT. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Increment Decrement...
Page 384 Phase Count Mode 4: Figure 12.33 shows an example of phase counting mode 4 operation. Table 12.12 lists the up counting and down counting conditions for the TCNT. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Increment Decrement...
Page 385 input clock is used as the TGR0B register input capture source, and a pulse width of four times the 2-phase encoder pulse is detected. The channel 1 TGR1A and TGR1B registers are set for the input capture function, the channel 0 TGR0A and TGR0C register compare-match is used as an input capture source, and all of the control period increment and decrement values are stored.
Page 386: Reset-Synchronized Pwm Mode
12.4.8 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained using channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins become PWM output pins and TCNT3 becomes an upcounter.
Page 387 4. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 5. Reset TCNT3 and TCNT4 to H'0000. 6. TGR3A is the period register. Set the waveform period value in TGR3A. Set the transition times of the PWM output waveforms in TGR3B, TGR4A, and TGR4B.
Page 388 Reset-synchronized PWM mode Stop counting Select counter clock Select counter clear source Brushless DC motor control setting Set TCNT Set TGR PWM cycle output enabling, PWM output level setting Set reset-synchronized PWM mode Enable PWM output Start count operation Reset-synchronized PWM mode Figure 12.35 Procedure for Selecting the Reset-Synchronized PWM Mode...
Page 389 Reset-Synchronized PWM Mode Operation: Figure 12.36 shows an example of operation in the reset-synchronized PWM mode. TCNT3 and TCNT4 operate as upcounters. The counter is cleared when a TCNT3 and TGR3A compare-match occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGR3B, TGR4A, TGR4B compare-match, and upon counter clears.
Page 390: Complementary Pwm Mode
12.4.9 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained using channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins become PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period.
Page 391 Table 12.16 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU TCNT3 Start of up-count from value set Maskable by BSC/BCR1 setting * in dead time register TGR3A Set TCNT3 upper limit value Maskable by BSC/BCR1 setting * (1/2 carrier cycle + dead time) TGR3B PWM output 1 compare register...
Page 392 @ @ @ @ @ @ @ @ @ @ @ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ TGR3C TCBR @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ TDDR TGR3A TCDR...
Page 393 Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 12.38. 1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT3 and TCNT4 are stopped.
Page 394 Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC motor control setting TCNT setting Inter-channel cycle setting TGR setting Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting Enable waveform output Start count operation...
Page 395 Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase PWM output is possible. Figure 12.39 illustrates counter operation in complementary PWM mode, and figure 12.40 shows an example of complementary PWM mode operation. • Counter operation In complementary PWM mode, three counters—TCNT3, TCNT4, and TCNTS—perform up/down-count operations.
Page 396 • Register operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 12.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGR3B, TGR4A, and TGR4B.
Page 397 Transfer from temporary Transfer from temporary register to compare register register to compare register TGR3A TCNTS TCDR TCNT3 TGR4A TCNT4 TGR4C TDDR H'0000 Buffer register H'6400 H'0080 TGR4C Temporary register H'6400 H'0080 TEMP2 Compare register H'6400 H'0080 TGR4A Output waveform Output waveform (Output waveform is active-low) Figure 12.40 Example of Complementary PWM Mode Operation...
Page 398 • Initialization In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3–MD0 in the timer mode register (TMDR), the following initial register values must be set. TGR3C operates as the buffer register for TGR3A, and should be set with 1/2 the PWM carrier cycle + dead time Td.
Page 399 • PWM cycle setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGR3A, in which the TCNT3 upper limit value is set, and TCDR, in which the TCNT4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: TGR3A set value = TCDR set value + TDDR set value The TGR3A and TCDR settings are made by setting the values in buffer registers TGR3C and...
Page 400 • Register data updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register.
Page 401 Figure 12.42 Example of Data Update in Complementary PWM Mode...
Page 402 • Initial output in complementary PWM mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT4 exceeds the value set in the dead time register (TDDR).
Page 403 Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT3, 4 value TCNT3 TCNT4 TDDR TGR4A Time Initial output Positive phase Active level output Negative phase output Complementary TCNT3, 4 count start...
Page 404 • Complementary PWM mode PWM output generation method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non- overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register.
Page 405 T2 period T1 period T1 period TGR3A TCDR TDDR H'0000 Positive phase Negative phase Figure 12.45 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGR3A TCDR TDDR H'0000 Positive phase Negative phase Figure 12.46 Example of Complementary PWM Mode Waveform Output (2)
Page 406 T1 period T2 period T1 period TGR3A TCDR TDDR H'0000 Positive phase Negative phase Figure 12.47 Example of Complementary PWM Mode Waveform Output (3) T1 period T2 period T1 period TGR3A TCDR TDDR H'0000 Positive phase Negative phase Figure 12.48 Example of Complementary PWM Mode 0% and 100% Waveform Output (1)
Page 407 T1 period T2 period T1 period TGR3A TCDR TDDR H'0000 Positive phase Negative phase Figure 12.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period T1 period TGR3A TCDR TDDR H'0000 Positive phase Negative phase Figure 12.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (3)
Page 408 T1 period T2 period T1 period TGR3A TCDR TDDR H'0000 c b' d a' Positive phase Negative phase Figure 12.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period T2 period T1 period TGR3A TCDR TDDR H'0000 Positive phase Negative phase...
Page 409 • Complementary PWM mode 0% and 100% duty output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 12.48 to 12.52 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state.
Page 410 • Counter clearing by another channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2–CCLR0 in the timer control register (TCR), it is possible to have TCNT3, TCNT4, and TCNTS cleared by another channel.
Page 411 • Example of AC synchronous motor (brushless DC motor) drive waveform output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 12.55 to 12.58 show examples of brushless DC motor drive waveforms created using TGCR.
Page 412 External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 12.56 Example of Output Phase Switching by External Input (2) TGCR UF bit...
Page 413 TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 12.58 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) •...
Page 414 Complementary PWM Mode Output Protection Function: Complementary PWM mode output has the following protection functions. • Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus control register 1 (BCR1).
Page 415: Interrupts
12.5 Interrupts 12.5.1 Interrupt Sources and Priority Ranking The MTU has three interrupt sources: TGR register compare-match/input captures, TCNT counter overflows and TCNT counter underflows. Because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled.
Page 416 Table 12.17 MTU Interrupt Sources Interrupt DMAC Activation Priority * Channel Source Description Activation TGI0A TGR0A input capture/compare-match Yes High TGI0B TGR0B input capture/compare-match No TGI0C TGR0C input capture/compare-match No TGI0D TGR0D input capture/compare-match No TCI0V TCNT0 overflow TGI1A TGR1A input capture/compare-match Yes TGI1B TGR1B input capture/compare-match No TCI1V...
Page 417: Dtc/Dmac Activation
12.5.2 DTC/DMAC Activation DTC Activation: The TGR register input capture/compare-match interrupt of any channel can be used as a source to activate the on-chip data transfer controller (DTC). For details, refer to section 8, Data Transfer Controller (DTC). The MTU has 17 input capture/compare-match interrupts that can be used as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2, and five for channel 4.
Page 418: Operation Timing
12.6 Operation Timing 12.6.1 Input/Output Timing TCNT Count Timing: Count timing for the TCNT counter with internal clock operation is shown in figure 12.59. Count timing with external clock operation (normal mode) is shown in figure 12.60, and figure 12.61 shows count timing with external clock operation (phase counting mode). φ...
Page 419 φ External Falling edge Rising edge Falling edge clock TCNT input clock N – 1 N + 1 TCNT Figure 12.61 TCNT Count Timing during External Clock Operation (Phase Counting Mode) Output Compare Output Timing: The compare-match signal is generated at the final state of TCNT and TGR matching.
Page 420 φ TCNT input clock TCNT N + 1 Compare- match signal TIOC pin Figure 12.63 Output Compare Output Timing (Complementary PWM Mode/Reset Sync PWM Mode) Input Capture Signal Timing: Figure 12.64 illustrates input capture timing. φ Input capture Rising edge Falling edge input Input capture...
Page 421 Counter Clearing Timing Due to Compare-Match/Input Capture: Timing for counter clearing due to compare-match is shown in figure 12.65. Figure 12.66 shows the timing for counter clearing due to input capture. φ Compare- match signal Counter clear signal H'0000 TCNT Figure 12.65 Counter Clearing Timing (Compare-Match) φ...
Page 422 Buffer Operation Timing: Compare-match buffer operation timing is shown in figure 12.67. Figure 12.68 shows input capture buffer operation timing. φ n + 1 TCNT Compare- match signal Compare- match buffer signal TGRA, TGRB TGRC, TGRD Figure 12.67 Buffer Operation Timing (Compare-Match) φ...
Page 423: Interrupt Signal Timing
12.6.2 Interrupt Signal Timing Setting TGF Flag Timing during Compare-Match: Figure 12.69 shows timing for the TGF flag of the timer status register (TSR) due to compare-match, as well as TGI interrupt request signal timing. φ TCNT input clock TCNT N + 1 Compare- match signal...
Page 424 φ Input capture signal TCNT TGF flag TGI interrupt Figure 12.70 TGI Interrupt Timing (Input Capture) Setting Timing for Overflow Flag (TCFV)/Underflow Flag (TCFU): Figure 12.71 shows timing for the TCFV flag of the timer status register (TSR) due to overflow, as well as TCIV interrupt request signal timing.
Page 425 φ TCNT input clock TCNT H'0000 H'FFFF (underflow) Underflow signal TCFU flag TCIU interrupt Figure 12.72 TCIU Interrupt Setting Timing φ TCNT input clock TCNT H'0001 H'0000 H'0001 (underflow) Underflow signal TCFV flag TCIV interrupt Figure 12.73 TCIV Interrupt Setting Timing (TSR4, Complementary PWM Mode)
Page 426 Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. For DTC/DMA controller activation, clearing can also be done automatically. Figure 12.74 shows the timing for status flag clearing by the CPU. Figure 12.75 shows timing for clearing due to the DTC/DMA controller.
Page 427: Notes And Precautions
12.7 Notes and Precautions This section describes contention and other matters requiring special attention during MTU operations. 12.7.1 Input Clock Limitations The input clock pulse width, in the case of single edge, must be 1.5 states or greater, and 2.5 states or greater for both edges.
Page 428: Contention Between Tcnt Write And Clear
12.7.3 Contention between TCNT Write and Clear If a counter clear signal is issued in the T state during the TCNT write cycle, TCNT clearing has priority, and TCNT write is not conducted (figure 12.77). TCNT write cycle φ Address TCNT address Write signal Counter...
Page 429: Contention Between Tcnt Write And Increment
12.7.4 Contention between TCNT Write and Increment If a count-up signal is issued in the T state during the TCNT write cycle, TCNT write has priority, and the counter is not incremented (figure 12.78). TCNT write cycle φ Address TCNT address Write signal TCNT input clock...
Page 430: Contention Between Buffer Register Write And Compare Match
12.7.5 Contention between Buffer Register Write and Compare Match If a compare-match occurs in the T state of the TGR write cycle, data is transferred by the buffer operation from the buffer register to the TGR. Data to be transferred differs depending on channels 0 and 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write (figures 12.79 and 12.80).
Page 431 TGR write cycle φ Buffer register Address address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register Figure 12.80 TGR Write and Compare-Match Contention (Channels 3 and 4)
Page 432: Contention Between Tgr Read And Input Capture
12.7.6 Contention between TGR Read and Input Capture If an input capture signal is issued in the T state of the TGR read cycle, the read data is that after input capture transfer (figure 12.81). TGR read cycle φ Address address Read signal Input capture...
Page 433: Contention Between Tgr Write And Input Capture
12.7.7 Contention between TGR Write and Input Capture If an input capture signal is issued in the T state of the TGR read cycle, input capture has priority, and TGR write does not occur (figure 12.82). TGR write cycle φ Address TGR address Write signal...
Page 434: Contention Between Buffer Register Write And Input Capture
12.7.8 Contention between Buffer Register Write and Input Capture If an input capture signal is issued in the T state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 12.83). Buffer register write cycle φ...
Page 435: Contention Between Tgr Write And Compare Match
12.7.9 Contention between TGR Write and Compare Match If a compare-match occurs in the T state of the TGR write cycle, data is written to the TGR and a compare-match signal is issued (figure 12.84). TGR write cycle φ TGR address Address Write signal Compare...
Page 436 TCNT write cycle φ Address TCNT2 address Write signal TCNT2 H'FFFE H'FFFF N + 1 TCNT2 write data TGR2A–B H'FFFF Ch2 compare- match signal A/B Disabled TCNT1 input clock TCNT1 TGR1A Ch1 compare- match signal A TGR1B Ch1 inputcapture signal B TCNT0 TGR0A–D Ch0 input capture...
Page 437: 12.7.11 Counter Value During Complementary Pwm Mode Stop
12.7.11 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT3 and TCNT4 in complementary PWM mode, TCNT3 has the timer dead time register (TDDR) value, and TCNT4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state (figure 12.86).
Page 438: 12.7.13 Reset Sync Pwm Mode Buffer Operation And Compare Match Flag
12.7.13 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR4 is set to 1.
Page 439 Buffer transfer with TGR3A TCNT3 compare match A3 Point a TGR3A, TGR3C TGR3C TGR3B, TGR4A, TGR4B Point b TGR3D, TGR4C, TGR3B, TGR3D, TGR4D TGR4A, TGR4C, TGR4B, TGR4D H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGF3C Not set TGF3D Not set TGF4C TGF4D Figure 12.87 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode...
Page 440: 12.7.14 Overflow Flags In Reset Sync Pwm Mode
When setting the buffer operation in the reset synchronous PWM mode , it is not necessary to set the timer interrupt enable register’s (TIER4) TGIEC and TGIED bits to 0, to prohibit interrupt output. Figure 12.88 shows an example of operations for TGR3, TGR4, TIOC3, and TIOC4, with TMDR3’s BFA and BFB bits set to 1, and TMDR4’s BFA and BFB bits set to 0.
Page 441 When TCNT3 and TCNT4 count up to H'FFFF, a compare-match occurs with TGR3A, and TCNT3 and TCNT4 are both cleared. At this point, TSR3’s TCFV bit is not set, but the TCFV bit of TSR4 is set. This can be avoided by sync setting for channel 3 and channel 4. Set the SYNC3 and SYNC4 bits of the timer sync register (TSYR) to 1, compare-match with TGR3A by TCR3 for the counter clear source, and sync clear with TCR4.
Page 442 Counter clear by compare match 3A TGR3A (H'FFFF) TCNT3=TCNT4 H'0000 TCF3V Not set Not set TCF4V Figure. 12.90 Reset Sync PWM Mode Overflow Flag (for A Mask)
Page 443: 12.7.15 Notes On Compare Match Flags In Complementary Pwm Mode
12.7.15 Notes on Compare Match Flags in Complementary PWM Mode In complementary PWM mode, buffer register compare-match flags can be set only for compare with three counters (TCNT3, TCNT4, and TCNTS). Note that when the buffer register set value is dead time (Td), 2Td, TGR3A – Td, or TGR3A –...
Page 444 • A mask operation For A mask, the above operation is modified as follows: In complementary PWM mode, buffer register compare-match flags can be set only for compare with three counters (TCNT3, TCNT4, and TCNTS). Special properties of compare match flag disappear and compare match flags of buffer registers are set to all set values of buffer registers.
Page 445: 12.7.16 Contention Between Overflow/Underflow And Counter Clearing
12.7.16 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 12.93 shows the operation timing when a TGR compare-match is specified as the clearing source, and H'FFFF is set in TGR.
Page 446: 12.7.17 Contention Between Tcnt Write And Overflow/Underflow
12.7.17 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 12.94 shows the operation timing in this case.
Page 447: Cautions On Transition From Normal Operation Or Pwm Mode
12.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset- Synchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset- synchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct.
Page 448: Cautions On Restarting With Sync Clear Of Another Channel
Note that for channel 0, the TIOCC pin allows both default output setting by TIOR and PWM output when setting buffer operation only for the TGRD register in PWM mode. When using channel 0 in PWM mode 1 and setting buffer operation, use both the TGRC and TGRD registers as buffer registers.
Page 449: Mtu Output Pin Initialization
Figure 12.95 shows an example of the duration while the temporary register is executing comparisons. initial TB, TA, and TB indicate the duration of the temporary register comparison. initial TB TGR3A TCDR TCNT3 TCNT4 TDDR H'0000 Figure. 12.95 Temporary Register Comparison Execution Time 12.8 MTU Output Pin Initialization 12.8.1...
Page 450: Operation In Case Of Re-Setting Due To Error During Operation, Etc
12.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level.
Page 451 • In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. • In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins.
Page 452 (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.96 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. RESET TMDR TOER...
Page 453 (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.97 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TOER...
Page 454 (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 12.98 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TOER...
Page 455 (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.99 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re- setting.
Page 456 (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.100 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
Page 457 (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.101 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting. RESET TMDR TOER...
Page 458 (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 12.102 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. RESET TMDR TOER...
Page 459 (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 12.103 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TOER...
Page 460 (9) Operation when Rrror Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 12.104 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TOER...
Page 461 (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.105 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re- setting.
Page 462 (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.106 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
Page 463 (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.107 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting.
Page 464 (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 12.108 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. RESET TMDR TIOR...
Page 465 (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 12.109 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TIOR...
Page 466 (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 12.110 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TIOR...
Page 467 (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.111 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re- setting.
Page 468 (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.112 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. RESET TMDR TIOR...
Page 469 (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.113 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TIOR...
Page 470 (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 12.114 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TIOR...
Page 471 (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.115 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting.
Page 472 (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.116 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
Page 473 (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.117 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 474 (23a) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.118 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
Page 475 (23b) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.119 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
Page 476 (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.120 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode. RESET TOCR TMDR...
Page 477 (25) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.121 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in normal mode after re-setting.
Page 478 (26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.122 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 479 (27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.123 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in complementary PWM mode after re-setting. RESET TOCR TMDR...
Page 480 (28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.124 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in reset-synchronous PWM mode after re-setting. RESET TOCR TMDR...
Page 481: Port Output Enable (Poe)
12.9 Port Output Enable (POE) The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0–POE3 pin input, depending on the output status of the high-current pins (PE09/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C/DACK0/AH, PE15/TIOC4D/DACK1/IRQOUT).
Page 482: Block Diagram
12.9.2 Block Diagram The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 12.125. TIOC3B * Output level detection circuit TIOC3D * TIOC4A * Output level TIOC4C * detection circuit TIOC4B * Output level TIOC4D * detection circuit...
Page 483: Pin Configuration
12.9.3 Pin Configuration Table 12.18 shows the POE pins. Table 12.18 Pin Configuration Name Abbreviation Description POE0–POE3 Port output enable input pins Input Input request signals to make high- current pins high-impedance state Table 12.19 shows output-level comparisons with pin combinations. Table 12.19 Output Level Comparisons Pin Combination Description...
Page 484: Poe Register Descriptions
12.10 POE Register Descriptions 12.10.1 Input Level Control/Status Register (ICSR) The input level control/status register (ICSR) is a 16-bit read/write register that selects the POE0– POE3 pin input modes, controls the enable/prohibit of interrupts, and indicates status. If any of the POE3F–POE0F bits are set to 1, the high current pins become high impedance state.
Page 485 • Bit 13—POE1 Flag (POE1F): This flag indicates that a high impedance request has been input to the POE1 pin. Bit 13: POE1F Description Clear condition: By writing 0 to POE1F after reading a POE1F = 1 (initial value) Set condition: When the input set by ICSR bits 3 and 2 occurs at the POE1 pin •...
Page 486 • Bits 5 and 4—POE2 Mode 1, 0 (POE2M1 and POE2M0): These bits select the input mode of the POE2 pin. Bit 5: Bit 4: POE2M1 POE2M0 Description Accept request on falling edge of POE2 input. (initial value) Accept request when POE2 input has been sampled for 16 φ/8 clock pulses, and all are low level.
Page 487: Output Level Control/Status Register (Ocsr)
12.10.2 Output Level Control/Status Register (OCSR) The output level control/status register (OCSR) is a 16-bit read/write register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance. OCSR is initialized to H'0000 by an external power-on reset;...
Page 488 • Bit 9—Output Level Compare Enable (OCE): This bit enables the start of output level comparisons. When setting this bit, pay special attention to the output pin combinations shown in table 12.19. When 0 is output, the OSF bit is set to 1 at the same time this bit is set, and output goes to high impedance.
Page 489: Operation
12.11 Operation 12.11.1 Input Level Detection Operation If the input conditions set by the ICSR occur on any of the POE pins, all high-current pins become high-impedance state. Falling Edge Detection: When a change from high to low level is input to the POE pins. Low-Level Detection: Figure 12.126 shows the low-level detection operation.
Page 490: 12.11.2 Output-Level Compare Operation
12.11.2 Output-Level Compare Operation Figure 12.127 shows an example of the output-level compare operation for the combination of PE09/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations. 0 level overlapping detected PE09/ TIOC3B PE11/ TIOC3D High impedance state Figure 12.127 Output-Level Detection Operation 12.11.3 Release from High-Impedance State High-current pins that have entered high-impedance state due to input-level detection can be...
Page 491: 12.11.4 Poe Timing
12.11.4 POE timing Figure 12.128 shows an example of timing from POE input to high impedance of pin. CK last transition POE input Last transition edge detected PE9/TIOC3B High impedance state * Note: * Other high current pins (PE11/TICO3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C/DACK0/AH, PE15/TIOC4D/DACK1/IRQOUT) will enter the high impedance state with the same timing.
Page 493: Section 13 Watchdog Timer (Wdt)
Section 13 Watchdog Timer (WDT) 13.1 Overview The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip.
Page 494: Block Diagram
13.1.2 Block Diagram Figure 13.1 is the block diagram of the WDT. Overflow φ/2 φ/64 Interrupt (interrupt control φ/128 signal) φ/256 Clock Clock φ/512 select φ/1024 φ/4096 WDTOVF Reset φ/8192 Internal control reset signal * Internal clock sources RSTCSR TCNT TCSR interface Module bus...
Page 495: Register Configuration
13.1.4 Register Configuration Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 WDT Registers Address Write * Read * Name Abbreviation R/W Initial Value R/(W) * Timer control/status TCSR...
Page 496: Timer Control/Status Register (Tcsr)
13.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) Its functions include selecting the timer mode and clock source. Bits 7–5 are initialized to 000 by a power-on reset or in standby mode.
Page 497 • Bit 5—Timer Enable (TME): Enables or disables the timer. Bit 5: TME Description Timer disabled: TCNT is initialized to H'00 and count-up stops (initial value) Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. •...
Page 498: Reset Control/Status Register (Rstcsr)
13.2.3 Reset Control/Status Register (RSTCSR) The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers in that it is more difficult to write. See section 13.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow and selects the internal reset signal type.
Page 499: Register Access
13.2.4 Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions.
Page 500: Operation
Writing 0 to the WOVF bit Address: H'FFFF8612 H'A5 H'00 Writing to the RSTE and RSTS bits Address: H'FFFF8612 H'5A Write data Figure 13.3 Writing to the RSTCSR Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers.
Page 501 TCNT value Overflow H'FF H'00 Time WT/IT = 1 H'00 written WOVF = 1 WT/IT = 1 H'00 written TME = 1 in TCNT TME = 1 in TCNT WDTOVF and internal reset generated WDTOVF signal 128 φ clocks Internal reset signal * 512 φ...
Page 502: Interval Timer Mode
13.3.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5).
Page 503: Timing Of Setting The Overflow Flag (Ovf)
13.3.4 Timing of Setting the Overflow Flag (OVF) In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and an interval timer interrupt is simultaneously requested (figure 13.6). H'FF H'00 TCNT Overflow signal (internal signal) Figure 13.6 Timing of Setting the OVF...
Page 504: Notes On Use
13.4 Notes on Use 13.4.1 TCNT Write and Increment Contention If a timer counter (TCNT) increment clock pulse is generated during the T state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 13.8). TCNT write cycle Address TCNT address...
Page 505: System Reset With Wdtovf
System Reset With WDTOVF 13.4.4 If a WDTOVF signal is input to the RES pin, the LSI cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9. SH7040 Series Reset input Reset signal to...
Page 507: Section 14 Serial Communication Interface (Sci)
Section 14 Serial Communication Interface (SCI) 14.1 Overview The SH7040 Series has a serial communication interface (SCI) with two independent channels, both of which possess the same functions. The SCI supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 508: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of the SCI. Internal Module data bus data bus φ φ/4 Baud rate φ/16 generator Transmit/ φ/64 receive control Parity Clock generation Parity check External clock Receive shift register Serial mode register Receive data register Serial control register Transmit shift register...
Page 509: Pin Configuration
14.1.3 Pin Configuration Table 14.1 summarizes the SCI pins by channel. Table 14.1 SCI Pins Channel Pin Name Abbreviation Input/Output Function Serial clock pin SCK0 Input/output SCI0 clock input/output Receive data pin RxD0 Input SCI0 receive data input Transmit data pin TxD0 Output SCI0 transmit data output...
Page 510: Register Descriptions
14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the RDR.
Page 511: Transmit Data Register (Tdr)
The CPU cannot read or write the TSR directly. Bit: R/W: — — — — — — — — 14.2.4 Transmit Data Register (TDR) The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the TDR into the TSR and starts serial transmission.
Page 512 • Bit 7—Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or clock synchronous mode. Bit 7: C/A Description Asynchronous mode (initial value) Clocked synchronous mode • Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Page 513 • Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting.
Page 514: Serial Control Register (Scr)
14.2.6 Serial Control Register (SCR) The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a power-on reset or in standby mode.
Page 515 • Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE Description Transmitter disabled (initial value). The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. Transmitter enabled. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into the TDR.
Page 516 • Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2: TEIE Description Transmit-end interrupt (TEI) requests are disabled. * (initial value) Transmit-end interrupt (TEI) requests are enabled.
Page 517: Serial Status Register (Ssr)
14.2.7 Serial Status Register (SSR) The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER).
Page 518 • Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains received data. Bit 6: RDRF Description RDR does not contain valid received data (initial value) RDRF is cleared to 0 when the chip is power-on reset or enters standby mode, software reads RDRF after it has been set to 1, then writes 0 in RDRF, or the DMAC or DTC reads data from RDR RDR contains valid received data...
Page 519 • Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in the asynchronous mode. Bit 4: FER Description Receiving is in progress or has ended normally (initial value). Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value.
Page 520 • Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, the TDR did not contain valid data, so transmission has ended. TEND is a read- only bit and cannot be written. Bit 2: TEND Description Transmission is in progress TEND is cleared to 0 when software reads TDRE after it has been set to 1, then...
Page 521: Bit Rate Register (Brr)
14.2.8 Bit Rate Register (BRR) The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write the BRR.
Page 522 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 7.3728 9.8304 Bit Rate (Bits/s) Error (%) Error (%) Error (%) –0.07 0.03 –0.26 0.00 0.16 0.00 0.00 0.16 0.00 0.00 0.16 0.00 1200 0.00 0.16 0.00 2400 0.00 0.16...
Page 523 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 11.0592 Bit Rate (Bits/s) Error (%) Error (%) Error (%) –0.25 0.19 0.03 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16...
Page 524 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 12.288 14.7456 Bit Rate (Bits/s) Error (%) Error (%) Error (%) 0.08 –0.17 0.70 0.00 0.16 0.00 0.00 0.16 0.00 0.00 0.16 0.00 1200 0.00 0.16 0.00 2400 0.00 0.16...
Page 525 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 17.2032 Bit Rate (Bits/s) Error (%) Error (%) Error (%) 0.03 0.48 –0.12 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16...
Page 526 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 18.432 19.6608 Bit Rate (Bits/s) Error (%) Error (%) Error (%) –0.22 0.31 –0.25 0.00 0.00 0.16 0.00 0.00 0.16 0.00 0.00 0.16 1200 0.00 0.00 0.16 2400 0.00 0.00...
Page 527 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 22.1184 Bit Rate (Bits/s) Error (%) Error (%) Error (%) –0.35 0.19 –0.44 –0.54 0.00 0.16 0.16 0.00 0.16 –0.54 0.00 0.16 1200 0.16 0.00 0.16 2400 –0.54 0.00 0.16...
Page 528 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 24.576 25.8048 Bit Rate (Bits/s) Error (%) Error (%) Error (%) 0.08 –0.40 0.36 0.00 0.00 –0.43 0.00 0.00 0.16 0.00 0.00 –0.43 1200 0.00 0.00 0.16 2400 0.00 0.00...
Page 529 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 27.0336 29.4912 Bit Rate (Bits/s) Error (%) Error (%) Error (%) 0.00 0.23 -0.07 0.00 0.16 0.00 0.00 0.16 0.00 0.00 0.16 0.00 1200 0.00 0.16 0.00 2400 0.00 0.16...
Page 530 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 31.9488 Bit Rate (Bits/s) Error (%) Error (%) Error (%) 0.13 -0.13 0.03 -0.35 0.00 0.16 0.16 0.00 0.16 -0.35 0.00 0.16 1200 0.16 0.00 0.16 2400 -0.35 0.00 0.16...
Page 531 Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 33.1776 33.3333 Bit Rate (Bits/s) Error (%) Error (%) Error (%) 0.33 0.19 -0.02 0.39 0.00 -0.45 -0.07 0.00 0.01 0.39 0.00 -0.45 1200 -0.07 0.00 0.01 2400 0.39 0.00...
Page 532 Table 14.4 Bit Rates and BRR Settings in Clocked Synchronous Mode φ (MHz) Bit Rate (Bits/s) 2.5k 100k 250k 500k — — 2.5M...
Page 533 Table 14.4 Bit Rates and BRR Settings in Clocked Synchronous Mode (cont) φ (MHz) Bit Rate (Bits/s) 2.5k 100k 250k 500k 2.5M — — — — 3.5M — — — — — — — — — —...
Page 534 Table 14.4 Bit Rates and BRR Settings in Clocked Synchronous Mode (cont) φ (MHz) 33.3333 Bit Rate (Bits/s) 2.5k 100k 250k 500k 2.5M — — — — — — — — — — — — — — — — — —...
Page 535 B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) φ: Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) SMR Settings Clock Source CKS1...
Page 536 Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings φ (MHz) Maximum Bit Rate (Bits/s) 125000 4.9152 153600 187500 7.3728 230400 250000 9.8304 307200 312500 11.0592 345600 375000 12.288 384000 437500 14.7456 460800 500000 17.2032 537600 562500...
Page 537 Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 1.0000 62500 4.9152 1.2288 76800 1.5000 93750 7.3728 1.8432 115200 2.0000 125000 9.8304 2.4576 153600 2.5000 156250 11.0592 2.7648 172800 3.0000 187500...
Page 538 Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 3.6667 3666666.7 4.0000...
Page 539: Operation
14.3 Operation 14.3.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission format are selected in the serial mode register (SMR), as shown in table 14.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 14.9.
Page 540 Table 14.8 Serial Mode Register Settings and SCI Communication Formats SMR Settings SCI Communication Format Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 Data Parity Multipro- Stop Bit Mode STOP Length cessor Bit Length Asynchronous 8-bit Not set Not set 1 bit 2 bits...
Page 541: Operation In Asynchronous Mode
14.3.2 Operation in Asynchronous Mode In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Page 542 Transmit/Receive Formats: Table 14.10 shows the 11 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 14.10 Serial Communication Formats (Asynchronous Mode) SMR Bits Serial Transmit/Receive Format and Frame Length CHR PE STOP START...
Page 543 When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate.
Page 544 Initialize Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Select transmit/receive format in SMR Set value to BRR Wait 1-bit interval elapsed? Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary Figure 14.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 14.5 shows a sample flowchart for...
Page 545 Initialize Start transmitting Read TDRE bit in SSR TDRE = 1? Write transmission data to TDR and clear TDRE bit in SSR to 0 All data transmitted? Read TEND bit in SSR TEND = 1? Output break signal? Set DR = 0 Clear TE bit in SCR to 0;...
Page 546 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR).
Page 547 Start Parity Stop Parity Stop Start Data Data Serial Idle D0 D1 D7 0/1 data (marking state) TDRE TEND TxI interrupt TEI interrupt request interrupt handler writes request request data in TDR and clears TDRE to 0 1 frame Example: 8-bit data with parity and one stop bit Figure 14.6 SCI Transmit Operation in Asynchronous Mode Receiving Serial Data (Asynchronous Mode): Figures 14.7 and 14.8 show a sample flowchart for receiving serial data.
Page 548 Initialization Start reception Read ORER, PER, and FER bits in SSR PER, FER, ORER = 1? Error handling Read the RDRF bit in SSR RDRF = 1? Read reception data of RDR and clear RDRF bit in SSR to 0 All data received? Clear the RE bit of SCR to 0 End reception...
Page 549 Start of error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 PER = 1? Parity error handling Clear ORER, PER, and FER to 0 in SSR Figure 14.8 Sample Flowchart for Receiving Serial Data (2)
Page 550 In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. 3.
Page 551: Multiprocessor Communication
Start Parity Stop Parity Stop Start Data Data Serial Idle D0 D1 D7 0/1 data (marking state) TDRF RxI interrupt request 1 frame RxI interrupt Framing error handler reads generates data in RDR and ERI interrupt clears RDRF to 0. request.
Page 552 Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 14.8. Clock: See the description in the asynchronous mode section. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D...
Page 553 Initialization Start transmission Read TDRE bit in SSR TDRE = 1? Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? Read TEND bit in SSR TEND = 1? Output break signal? Set DR = 0 Clear TE bit in SCR to 0;...
Page 554 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR).
Page 555 Multiprocessor Multiprocessor Start Stop Stop Start Data Data Serial Idle D0 D1 D7 0/1 data (marking state) TDRE TEND TxI interrupt handler writes interrupt interrupt interrupt data in TDR and request request request clears TDRE to 0 1 frame Example: 8-bit data with multiprocessor bit and one stop bit Figure 14.12 SCI Multiprocessor Transmit Operation Receiving Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for receiving multiprocessor serial data.
Page 556 Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER bits of SSR FER = 1? or ORER =1? Read RDRF bit in SSR RDRF = 1? Read receive data from RDR Is ID the station’s ID Read ORER and FER bits in SSR FER = 1? or ORER =1?
Page 557 Start error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 Clear ORER and FER bits in SSR to 0 Figure 14.13 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
Page 558 Figures 14.14 and 14.15 show examples of SCI receive operation using a multiprocessor format. Start Data Stop Start Data Stop (ID1) (data 1) Serial D0 D1 Idling data (marking) MPIE RDRF value RxI interrupt request RxI interrupt handler Not station’s No RxI interrupt, (multiprocessor reads data in RDR...
Page 559: Clock Synchronous Operation
Start Data Stop Start Data Stop (ID2) (data 2) Serial Idling data (marking) MPIE RDRF Data2 value RxI interrupt request RxI interrupt handler Station’s ID, so receiving MPIE (multiprocessor reads data in RDR continues, with data bit is again interrupt), MPIE = 0 and clears RDRF to 0 received by the RxI set to 1...
Page 560 Transfer direction One unit (character or frame) of communication data Synchroni- zation clock Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: * High except in continuous transmitting or receiving. Figure 14.16 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next.
Page 561 Figure 14.17 is a sample flowchart for initializing the SCI. 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR). 3.
Page 562 Transmitting Serial Data (Synchronous Mode): Figure 14.18 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. SCI initialization: Set the TxD pin function with the PFC. 2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0.
Page 563 Initialize Start transmitting Read TDRE flag in SSR TDRE = 1? Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted? Read TEND flag in SSR TEND = 1? Clear TE bit to 0 in SCR Figure 14.18 Sample Flowchart for Serial Transmitting...
Page 564 Figure 14.19 shows an example of SCI transmit operation. Transmit direction Synchroni- zation clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TxI interrupt request request handler writes request data in TDR and clears TDRE to 0 1 frame Figure 14.19 Example of SCI Transmit Operation...
Page 565 Receiving Serial Data (Clock Synchronous Mode): Figures 14.20 and 14.21 shows a sample flowchart for receiving serial data. When switching from the asynchronous mode to the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled.
Page 566 Initialization Start reception Read the ORER bit of SSR ORER = 1? Error processing Read RDRF bit of SSR RDRF = 1? Read receive data from RDR and clear RDRF bit of SSR to 0 All data received? Clear RE bit of SCR to 0 End reception Figure 14.20 Sample Flowchart for Serial Receiving (1)
Page 567 Error handling Overrun error processing Clear ORER bit of SSR to 0 Figure 14.21 Sample Flowchart for Serial Receiving (2) Figure 14.22 shows an example of the SCI receive operation. Transfer direction Synchroni- zation clock Serial Bit 7 Bit 0 Bit 7 Bit 0 Bit 1...
Page 568 to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RxI).
Page 569 Initialization Start transmitting/receive Read TDRE bit in SSR TDRE = 1? Write transmission data in TDR and clear TDRE bit of SSR to 0 Read ORER bit of SSR ORER = 1? Error handling Read RDRF bit of SSR RDRF = 1? Read receive data of RDR, and clear RDRF bit of SSR to 0 data transmitted/and...
Page 570: Sci Interrupt Sources And The Dmac/Dtc
14.4 SCI Interrupt Sources and the DMAC/DTC The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RxI), and transmit-data-empty (TxI). Table 14.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR).
Page 571: Notes On Use
14.5 Notes on Use Sections 14.5.1 through 14.5.9 provide information for using the SCI. 14.5.1 TDR Write and TDRE Flags The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status.
Page 572: Break Detection And Processing
14.5.3 Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set.
Page 573 16 clocks 8 clocks 15 0 15 0 Internal base clock –7.5 clocks +7.5 clocks Receive Start bit data (RxD) Synchronization sampling timing Data sampling timing Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as: ...
Page 574: Constraints On Dmac/Dtc Use
14.5.7 Constraints on DMAC/DTC Use • When using an external clock source for the synchronization clock, update the TDR with the DMAC or the DTC, and then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input in the first four system clocks after the TDR is written, an error may occur (figure 14.25).
Page 575: Section 15 High Speed A/D Converter (Excluding A Mask)
Section 15 High Speed A/D Converter (Excluding A Mask) 15.1 Overview The high speed A/D converter has 10-bit resolution, and can select from a maximum of eight channels of analog inputs. 15.1.1 Features The high speed A/D converter has the following features: •...
Page 576: Block Diagram
15.1.2 Block Diagram Figure 15.1 is the block diagram of the high speed A/D converter. Internal conversion data bus circuit AV cc Bus I/F AV ref * ADDRA S&H A ADDRB ADDRC − ADDRD S&H B ADDRE ADDRF ADDRG ADDRH AV ss ADCR ADCSR ADTRG...
Page 577: Register Configuration
Table 15.1 Pin Configuration Abbreviation Function Analog supply Analog section power supply Analog ground Analog section ground and A/D conversion reference voltage Reference voltage A/D conversion standard voltage (SH7043 only) Analog input 0 Analog input channel 0 Analog input 1 Analog input channel 1 Analog input 2 Analog input channel 2...
Page 578: Register Descriptions
15.2 Register Descriptions 15.2.1 A/D Data Registers A–H (ADDRA–ADDRH) The ADDR are 16-bit read only registers for storing A/D conversion results. There are eight of these registers, ADDRA through ADDRH. The A/D converted data is 10-bit data which is sent to the ADDR for the corresponding converted channel for storage.
Page 579: A/D Control/Status Register (Adcsr)
Table 15.3 Analog Input Channel and ADDR Correspondence Analog Input Channel A/D Data Register ADDRA * ADDRB * ADDRC * ADDRD * ADDRE ADDRF ADDRG ADDRH Note: * Except during buffer operation 15.2.2 A/D Control/Status Register (ADCSR) The ADCSR is an 8-bit read/write register used for A/D conversion operation control and to indicate status.
Page 580 • Bit 7—A/D End Flag (ADF): This status flag indicates that A/D conversion has ended. Bit 7: ADF Description Clear conditions (initial value) • With ADF = 1, by reading the ADF flag then writing 0 in ADF • When the DTC or DMAC are activated by an ADI interrupt Set conditions •...
Page 581 • Bit 4—Clock Select (CKS): Sets the A/D conversion time. Set, according to the operating frequency, to give a conversion time of at least 2 µs (5 V version) or 4 µs (3.3 V version). Make conversion time changes only while conversion is halted. Bit 4: CKS Description Conversion time = 40 states (A/D converter standard clock = φ/2) (initial...
Page 582: A/D Control Register (Adcr)
15.2.3 A/D Control Register (ADCR) The ADCR is an 8-bit read/write register used for A/D conversion operation control. The ADCR is initialized to H'00 by power-on reset or in standby mode. Manual reset does not initialize. Bit: — TRGS1 TRGS0 SCAN DSMP BUFE1...
Page 583: Bus Master Interface
• Bit 2—Simultaneous Sampling (DSMP): Enables or disables the simultaneous sampling of two channels. See section 15.4.6, Simultaneous Sampling Operation, for details on simultaneous sampling. Set the DSMP bit only while conversion is halted. Bit 2: DSMP Description Normal sampling operation (initial value) Simultaneous sampling operation •...
Page 584 Word data read Data Bus I/F register Internal data bus Upper 8 bits AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 Lower 8 bits AD 3 AD 2 AD 1 AD 0 Figure 15.2 ADDR Read Operation (1)
Page 585 Byte data read Data register Bus I/F Internal data bus Upper 8 bits AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 Figure 15.3 ADDR Read Operation (2)
Page 586: Operation
15.4 Operation • The high speed A/D converter has 10-bit resolution. • In addition to the four operating modes of select or group, and single or scan can be set in combination with buffer operation and simultaneous sampling operation. • Select mode uses one channel and group mode selects multiple channels. •...
Page 587: Select-Scan Mode
Automatic clear Set to 1 by software ADST Conversion standby Channel 0 Conversion Conversion Sampling 1 Channel 1 standby conversion 1 standby Conversion standby Channel 2 Conversion standby Channel 3 ADDRA ADDRB Conversion result 1 ADDRC ADDRD Figure 15.4 A/D Converter Operation Example (Select-Single Mode) 15.4.2 Select-Scan Mode Choose select-scan mode when doing repeated A/D conversions for one channel.
Page 588: Group-Single Mode
Set to 1 by software Cleared to 0 by software ADST Channel 0 Conversion standby Conversion A/D conversion 5 stopped Conver- Sampling Sampling Sampling sion conver- conver- Channel 1 standby sion 1 sion 3 Conversion Sampling Sampling conver- conver- standby sion 4 sion 2 Sampling 6...
Page 589: Group-Scan Mode
Set to 1 by software Automatic clear ADST Conversion Sampling Conversion conversion Channel 0 standby standby Sampling conversion Conversion standby Conversion standby Channel 1 Sampling Conversion Conversion standby conversion Channel 2 standby Channel 3 Conversion standby Conversion result 1 ADDRA ADDRB Conversion result 2 ADDRC...
Page 590: Buffer Operation
Figure 15.7 shows an example of operation in the group-scan mode when AN0–AN2 are selected. Conversion standby Set to 1 by software Cleared to 0 by software ADST Conver- sion stopped Conver- Sam- Sam- conver- conver- sion pling pling Channel 0 sion 1 sion 4 standby...
Page 591 To use in combination with simultaneous sampling, set GRP = 1, BUFE1, BUFE0 = B'10, and CH2 = 0. Buffer operation timing is shown in figure 15.8. Set to 1 Cleared to 0 ADST by software by software Conver- Sampling Sampling Sampling sion...
Page 592 When the ADF flag is set to 1, if the ADIE bit is also set to 1, an ADI interrupt is issued. After the ADCSR is read, the ADF flag is cleared by a 0 write. With select single mode, the A/D converter goes into standby mode at the end of every conversion cycle.
Page 593: Simultaneous Sampling Operation
Table 15.5 Conversion Channel and ADF Flag Setting/Clearing Conditions During Buffer Operation 2 Channel Setting Sampling Channel CH2 CH1 CH0 BUFE1, BUFE0 = B'01 BUFE1, BUFE0 = B'10 BUFE1, BUFE0 = B'11 — AN0, AN2 (ADDRC) AN0, AN2, AN3 (ADDRD) AN0, AN2–AN4 AN0, AN1, AN4 AN0, AN4 (ADDRE)
Page 594 Table 15.6 Simultaneous Sampling Channels Channel Setting Sampling Channels, GRP 1 AN0, AN1 AN0, AN1→AN2, AN3 AN0, AN1→AN2, AN3→AN4, AN5 AN0, AN1→AN2, AN3→AN4, AN5→AN6, AN7 Set to 1 by software Automatically cleared ADST Conver- Sampling Conversion sion conver- Channel 0 standby standby sion 1...
Page 595: Conversion Start Modes
15.4.7 Conversion Start Modes The conversion start mode of the high speed A/D converter is set by the PWR bit of the ADCSR. When the PWR bit is cleared to 0, low-power conversion mode is set and the internal analog circuit becomes inactive.
Page 596 Figures 15.10 and 15.11 show examples of conversion start operation timing. Analog circuit Clear power supply ADST Set to 1 by software Cleared to 0 by software Sam- Sam- Conver- pling pling sion conver- conver- Channel 0 standby sion 1 sion 3 Sam- Conver-...
Page 597 (PWR cleared to 0) Analog circuit Switched off power Switched on by software (PWR set to 1) by software supply Set to 1 by software ADST Set to 1 by software Sam- Sam- Conversion Channel 0 pling conver- pling conver- standby sion 1 sion 2...
Page 598: Conversion Start By External Input
15.4.8 Conversion Start by External Input A/D conversions can be started by trigger signals generated by timer conversion start triggers or ADTRG inputs. When a trigger signal designated by the TRGS1 and TRGS0 bits of the ADCR occurs, the ADST bit of the ADCSR is set to 1 and A/D conversion is started. The other operations are the same as when the ADST bit is set to 1 by software.
Page 599: A/D Conversion Time
15.4.9 A/D Conversion Time The high speed A/D converter has an on-chip sample and hold circuit. The high speed A/D converter samples the input at time t after the ADST bit is set to 1, and then starts the conversion. The A/D conversion time t is the sum of the conversion start delay time t , the input sampling...
Page 600: Interrupts
Table 15.7 A/D Conversion Times CKS = 0 CKS = 1 Time Symbol A/D conversion start delay time Input sampling time A/D conversion time 42.5 42.5 42.5 82.5 82.5 82.5 CONV Notes: 1. Unit: states 2. Table entries are for when ADST = 1. If 200 states have not elapsed since the PWR bit has been set, no conversions are done until after those 200 states have occurred.
Page 601: Notes On Use
When the DTC or DMAC are activated by an ADI interrupt, the ADF flag is cleared to 0 when the final specified data register is read. Table 15.9 High Speed A/D Converter Interrupt Sources Interrupt Source Description DTC, DMAC Activation Interrupt caused by conversion end Possible 15.6...
Page 602 AVcc AVref This LSI 100Ω Rin * AN0 to AN7 0.1µF AVss Notes: Numbers are only to be noted as reference value 0.01µF 10µF *2 Rin: Input impedance Figure 15.14 Example of a Protection Circuit for the Analog Input Pins 1.0kΩ...
Page 603 Table 15.10 Analog Input Pin Specification Item Unit Analog input capacity — Permitted source impedance — kΩ...
Page 605: Section 16 Mid-Speed A/D Converter (A Mask)
Section 16 Mid-Speed A/D Converter (A Mask) 16.1 Overview The mid-speed A/D converter has 10 bit resolution, and can select from a maximum of eight channels of analog input. The mid-speed A/D converter is structured by two independent modules (A/D0 and A/D1) 16.1.1 Features The mid-speed A/D converter has the following features:...
Page 606: Block Diagram
16.1.2 Block Diagram Figure 16.1 is the block diagram of the mid-speed A/D converter. , AVref and AV pins of both A/D are common in LSI. A/D0 Module data bus AVcc Port 10-bit D/A trigger trigger (Only with 144 pin) Logical −...
Page 607: Pin Configuration
16.1.3 Pin Configuration Table 16.1 shows the input pins used with the mid-speed A/D converter. The AV and AV pins are for the mid-speed A/D converter internal analog section power supply. AVref pin is the A/D conversion standard voltage. Table 16.1 Pin Configuration Abbreviation I/O Function Analog supply...
Page 608: Register Configuration
16.1.4 Register Configuration Table 16.2 shows the register configuration of the mid-speed A/D converter. Table 16.2 Register Configuration Name Abbreviation R/W Initial Value Address Access Size A/D0 data register AH ADDRA0H H'00 H'FFFF8400 8, 16 A/D0 data register AL ADDRA0L H'00 H'FFFF8401 A/D0 data register BH...
Page 609: Register Descriptions
16.2 Register Descriptions 16.2.1 A/D Data Register A–D (ADDRA0–ADDRD0, ADDRA1–ADDRD1) A/D registers are special registers that read stored results of A/D conversion in 16 bits. There are eight registers: ADDRA0–ADDRD0 (A/D0) and ADDRA1–ADDRD1 (A/D1). The A/D converted data is 10 bit data which is to the ADDR of the corresponding converted channel for storage.
Page 610: A/D Control/Status Register (Adcsr0, Adcsr1)
16.2.2 A/D Control/Status Register (ADCSR0, ADCSR1) The A/D control/status registers (ADCSR0, 1) are registers that can read/write in 8 bits and control A/D converter operations such as mode selection. There are the ADCSR0 (A/D0) and ADCSR1 (A/D1). The ADCSR is initialized to H'00 during power-on reset or standby mode. Manual reset does not initialize ADCSR.
Page 611 • Bit 5—A/D Start (ADST): Selects start/end of A/D conversion. A1 is maintained during A/D conversion start. It is also possible to set a 1 by the A/D conversion trigger input pin (ADTRG). Bit 5: ADST Description A/D conversion halted (Initial value) 1.
Page 612: A/D Control Register (Adcr0, Adcr1)
Channel Selection Description Single mode Scan mode A/D0 A/D1 A/D0 A/D1 (Initial value) (Initial value) AN0, AN1 AN4, AN5 AN0, AN1 AN4–AN6 AN0–AN3 AN4–AN7 16.2.3 A/D Control Register (ADCR0, ADCR1) A/D control registers (ADCR0, 1) are registers that can read/write in 8 bits and enables or disables A/D conversion start of the external trigger input.
Page 613: Interface With Cpu
16.3 Interface with CPU Although A/D data register ADDR (ADDRA0–ADDRD0, ADDRA1–ADDRD1) are 16-bit registers, the bus width within the chip that integrates with the CPU is 8-bits. So, upper and lower data of the ADDR must be read separately. To avoid change in data while reading the upper/lower 2 bytes of ADDR, the lower byte data is read through the temporary register (TEMP).
Page 614: Operation
16.4 Operation The mid-speed converter operates using the continuous comparison method and is equipped with 10-bit resolution. Operations for the single and scan modes are explained below. 16.4.1 Single Mode (SCAN=0) The single mode is selected when executing A/D conversion for one channel only. A/D conversion is initiated when the ADST bit of the A/D control/status register is set to 1 by the software or external trigger input.
Page 615 Figure 16.3 Operation Example of Mid-speed A/D Converter (Single Mode, Channel 1 Selected)
Page 616: Scan Mode (Scan=1)
16.4.2 Scan Mode (SCAN=1) The scan mode is optimal for monitoring analog input of multiple channels (including channel 1). A/D conversion is started from channel 1 (AN0 for A/D0 and AN4 for A/D1) of the group when the ADST bit of the A/D control/status register (ADCSR) is set to 1 by the software or external trigger input.
Page 617 Figure 16.4 Operation Example of Mid-speed A/D Converter (Scan Mode, Three Channels Selected) (AN0–AN2)
Page 618: Input Sampling And A/D Conversion Time
16.4.3 Input Sampling and A/D Conversion Time The mid-speed A/D converter is equipped with a sample and hold circuit. The mid-speed A/D converter samples input after t hours has elapsed since setting the ADST bit of the A/D control/status register (ADCSR) to 1, then begins conversion. The A/D conversion timing is shown in table 16.4.
Page 619: External Trigger Input Timing
Table 16.4 A/D Conversion Time (Single Mode) CKS=0 CKS=1 Notation Min A/D conversion start delay time t — — Input sampling time — — — — A/D conversion time — — CCNV Note: Numbers in the table are in states (t 16.4.4 External Trigger Input Timing It is possible to start A/D conversion from an external trigger input.
Page 620: Interrupt And Dma, Dtc Transfer Requests
16.5 Interrupt and DMA, DTC Transfer Requests The mid-speed A/D converter generates A/D conversion complete interrupt when completing A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit of ADCSR. It is also possible to activate DMA or DTC transfer by the ADI interrupt request. It is possible to activate DTC with ADI0 interrupt of A/D0 and activate DMAC with ADI1 interrupt of A/D1.
Page 621: A/D Conversion Precision Definitions
16.6 A/D Conversion Precision Definitions The medium-speed A/D converter converts analog values input from analog input channels to 10- bit digital values by comparing them with an analog reference voltage. In this operation, the absolute precision of the A/D conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error.
Page 622: Usage Notes
16.7 Usage Notes The following points should be noted when using the mid-speed A/D converter. 16.7.1 Analog Voltage Settings (1) Analog input voltage range The voltage applied to analog input pins during A/D conversion should be in the range AVSS ≤...
Page 623 This LSI 100 Ω AN0–AN15 0.1 µF Notes: Numbers are only to be noted as reference value 10 µF 0.01 µF *2 R : Input impedance Figure 16.8 Example of Analog Input Pin Protection Circuit...
Page 624 1.0kΩ AN0 to AN7 20pFΩ 1MΩ Analog multiplexer Mid-speed A/D converter Note : Numbers are only to be noted as reference value Figure 16.9 Equivalent Circuit for the Analog Input Pins Table 16.6 Analog Pin Specifications Item Unit Analog input capacitance —...
Page 625: Section 17 Compare Match Timer (Cmt)
Section 17 Compare Match Timer (CMT) 17.1 Overview The SH7040 series has an on-chip compare match timer (CMT) configured of 16-bit timers for two channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 17.1.1 Features The CMT has the following features: •...
Page 626 φ/8 φ/32 φ/128 φ/512 φ/8 φ/32 φ/128 φ/512 CM10 CMI1 Control circuit Clock selection Control circuit Clock selection interface Module bus Internal bus CMSTR: Compare match timer start register CMCSR: Compare match timer control/status register CMCOR: Compare match timer constant register CMCNT: Compare match timer counter CMI:...
Page 627: Register Configuration
17.1.3 Register Configuration Table 17.1 summarizes the CMT register configuration. Table 17.1 Register Configuration Initial Access Size Channel Name Abbreviation Value Address (Bits) Shared Compare match timer CMSTR H'0000 H'FFFF83D0 8, 16, 32 start register R/(W) * Compare match timer CMCSR0 H'0000 H'FFFF83D2 8, 16, 32...
Page 628: Register Descriptions
17.2 Register Descriptions 17.2.1 Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by power-on resets and by standby mode.
Page 629: Compare Match Timer Control/Status Register (Cmcsr)
17.2.2 Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by power-on resets and by standby mode. Manual reset does not initialize CMCSR.
Page 630: Compare Match Timer Counter (Cmcnt)
• Bits 1, 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT from among the four internal clocks obtained by dividing the system clock (φ). When the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and CKS0.
Page 631: Compare Match Timer Constant Register (Cmcor)
17.2.4 Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare match period with the CMCNT. The CMCOR is initialized to H'FFFF by power-on resets and by standby mode. There is no initializing with manual reset.
Page 632: Cmcnt Count Timing
17.3.2 CMCNT Count Timing One of four clocks (φ/8, φ/32, φ/128, φ/512) obtained by dividing the system clock (CK) can be selected by the CKS1, CKS0 bits of the CMCSR. Figure 17.3 shows the timing. Internal clock CMCNT input clock N –...
Page 633: Compare Match Flag Clear Timing
CMCNT input clock CMCNT CMCOR Compare match signal Figure 17.4 CMF Set Timing 17.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1, or by a clear signal after a DTC transfer.
Page 634: Notes On Use
17.5 Notes on Use Take care that the contentions described in sections 17.5.1–17.5.3 do not arise during CMT operation. 17.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed.
Page 635: Contention Between Cmcnt Word Write And Incrementation
17.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 17.7 shows the timing. CMCNT write cycle Address CMCNT Internal...
Page 636: Contention Between Cmcnt Byte Write And Incrementation
17.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. The byte data on the side not performing the writing is also not incremented, so the contents are those before the write.
Page 637: Section 18 Pin Function Controller
Section 18 Pin Function Controller 18.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. Table 18.1 lists the SH7040 Series’s multiplexed pins. The multiplex pin functions have restrictions dependent on the operating mode. Table 18.2 lists the pin functions and initial values for each operating mode.
Page 638 Table 18.1 Multiplexed Pins (cont) Function 1 Function 2 Function 3 Function 4 TFP- Port (Re-lated Module) (Related Module) (Related Module) (Related Module) PA4 I/O (port) TxD1 output (SCI) — — 134 50 PA3 I/O (port) RxD1 input (SCI) — —...
Page 639 Table 18.1 Multiplexed Pins (cont) Function 1 Function 2 Function 3 Function 4 TFP- Port (Related Module) (Related Module) (Related Module) (Related Module) PC6 I/O (port) A6 output (BSC) — — 15 11 PC5 I/O (port) A5 output (BSC) — —...
Page 640 Table 18.1 Multiplexed Pins (cont) Function 1 Function 2 Function 3 Function 4 TFP- Port (Related Module) (Related Module) (Related Module) (Related Module) PD13 I/O (port) D13 I/O (BSC) — — 75 57 PD12 I/O (port) D12 I/O (BSC) — —...
Page 641 Table 18.1 Multiplexed Pins (cont) Function 1 Function 2 Function 3 Function 4 TFP- Port (Related Module) (Related Module) (Related Module) (Related Module) PE3 I/O (port) TIOC0D I/O (MTU) DRAK1 output — 113 95 (DMAC) TIOC0C I/O (MTU) DREQ1 input PE2 I/O (port) —...
Page 645: Register Configuration
18.2 Register Configuration Table 18.3 summarizes the registers of the pin function controller. Table 18.3 Pin Function Controller Registers Name Abbreviation R/W Initial Value Address Access Size Port A I/O register H PAIORH H'0000 H'FFFF8384 8, 16, 32 H'FFFF8385 Port A I/O register L PAIORL H'0000 H'FFFF8386...
Page 646: Register Descriptions
18.3 Register Descriptions 18.3.1 Port A I/O Register H (PAIORH) The port A I/O register H (PAIORH) is a 16-bit read/write register that selects input or output for the most significant 8 pins of port A. Bits PA23IOR–PA16IOR correspond to pins PA23/WRHH– PA16/AH.
Page 647: Port A I/O Register L (Paiorl)
18.3.2 Port A I/O Register L (PAIORL) The port A I/O register L (PAIORL) is a 16-bit read/write register that selects input or output for the least significant 16 pins of port A. Bits PA15IOR–PA0IOR correspond to pins PA15/CK– PA0/RXD0. PAIORL is enabled when the port A pins function as general input/outputs (PA15– PA0), or with the serial clock (SCK1, SCK0).
Page 648 The settings for this register are effective only for the 144-pin version. There are no corresponding pins for this register in the 112-pin and 120-pin versions. However, read/writes are possible. Bit: — PA23 — PA22 — PA21 — PA20 Initial value: R/W: Bit: PA19...
Page 649 • Bit 8—PA20 Mode (PA20MD): Selects the function of the PA20/CASHL pin. Bit 8: PA20MD Description General input/output (PA20) (initial value) Column address output (CASHL) (PA20 in single chip mode) • Bits 7 and 6—PA19 Mode 1, 0 (PA19MD1 and PA19MD0): These bits select the function of the PA19/BACK/DRAK1 pin.
Page 650: Port A Control Registers L1, L2 (Pacrl1 And Pacrl2)
• Bit 0—PA16 Mode (PA16MD): Selects the function of the PA16/AH pin. Bit 0: PA16MD Description General input/output (PA16) (initial value) Address hold output (AH) (PA16 in single chip mode) 18.3.4 Port A Control Registers L1, L2 (PACRL1 and PACRL2) PACRL1 and PACRL2 are 16-bit read/write registers that select the functions of the least significant sixteen multiplexed pins of port A.
Page 651 • Bit 14—PA15 Mode (PA15MD): Selects the function of the PA15/CK pin. Bit 14: PA15MD Description General input/output (PA15) (single chip mode initial value) Clock output (CK) (extended mode initial value) • Bit 13—Reserved: This bit always reads as 0. The write value should always be 0. •...
Page 652 • Bit 4—PA10 Mode (PA10MD): Selects the function of the PA10/CS0 pin. Bit 4: PA10MD Description General input/output (PA10) (initial value) (CS0 in on-chip ROM invalid mode) Chip select output (CS0) (PA10 in single chip mode) • Bits 3 and 2—PA9 Mode 1, 0 (PA9MD1 and PA9MD0): These bits select the function of the PA9/TCLKD/IRQ3 pin.
Page 653 Port A Control Register L2 (PACRL2): Bit: — PA4MD Initial value: R/W: Bit: — PA3MD — PA1MD — PA0MD Initial value: R/W: • Bits 15 and 14—PA7 Mode 1, 0 (PA7MD1 and PA7MD0): These bits select the function of the PA7/TCLKB/CS3 pin. Bit 15: Bit 14: PA7MD1...
Page 654 • Bits 11 and 10—PA5 Mode 1, 0 (PA5MD1 and PA5MD0): These bits select the function of the PA5/SCK1/DREQ1/IRQ1 pin. Bit 11: Bit 10: PA5MD1 PA5MD0 Description General input/output (PA5) (initial value) Serial clock input/output (SCK1) DMA transfer request received input (DREQ1) (PA5 in single chip mode) Interrupt request input (IRQ1) •...
Page 655: Port B I/O Register (Pbior)
• Bit 2—PA1 Mode (PA1MD): Selects the function of the PA1/TxD0 pin. Bit 2: PA1MD Description General input/output (PA1) (initial value) Transmit data output (TxD0) • Bit 1—Reserved: This bit always reads as 0. The write value should always be 0. •...
Page 656: Port B Control Registers (Pbcr1 And Pbcr2)
18.3.6 Port B Control Registers (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the ten multiplexed pins of port B. PBCR1 selects the functions of the top two bits of port B; PBCR2 selects the functions of the bottom eight bits of port B.
Page 657 • Bits 1 and 0—PB8 Mode (PB8MD1 and PB8MD0): PB8MD1 and PB8MD0 select the function of the PB8/IRQ6/A20/WAIT pin. Bit 1: PB8MD1 Bit 0: PB8MD0 Description General input/output (PB8) (initial value) Interrupt request input (IRQ6) Address output (A20) (PB8 in single chip mode) Wait state request input (WAIT) (PB8 in single chip mode) Port B Control Register 2 (PBCR2):...
Page 658 • Bits 13 and 12—PB6 Mode (PB6MD1 and PB6MD0): PB6MD1 and PB6MD0 select the function of the PB6/IRQ4/A18/BACK pin. Bit 13: Bit 12: PB6MD1 PB6MD0 Description General input/output (PB6) (initial value) Interrupt request input (IRQ4) Address output (A18) (PB6 in single chip mode) Bus right request output (BACK) (PB6 in single chip mode) •...
Page 659 • Bits 5 and 4—PB2 Mode (PB2MD1 and PB2MD0): PB2MD1 and PB2MD0 select the function of the PB2/IRQ0/POE0/RAS pin. Bit 5: PB2MD1 Bit 4: PB2MD0 Description General input/output (PB2) (initial value) Interrupt request input (IRQ0) Port output enable (POE0) Row address strobe (RAS) (PB2 in single chip mode) •...
Page 660: Port C I/O Register (Pcior)
18.3.7 Port C I/O Register (PCIOR) The port C I/O register (PCIOR) is a 16-bit read/write register that selects input or output for the 16 port C pins. Bits PC15IOR–PC0IOR correspond to pins PC15/A15 to PC0/A0. PCIOR is enabled when the port C pins function as general input/outputs (PC15–PC0). For other functions, it is disabled.
Page 661: Port C Control Register (Pccr)
18.3.8 Port C Control Register (PCCR) PCCR is a 16-bit read/write register that selects the functions for the sixteen port C multiplexed pins. There are instances when these register settings will be ignored, depending on the operation mode. Refer to table 18.2, Pin Arrangement by Mode, for details. PCCR is initialized to H'0000 by power-on resets but is not initialized for manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is maintained.
Page 662 • Bit 12—PC12 Mode (PC12MD): Selects the function of the PC12/A12 pin. Bit 12: PC12MD Description General input/output (PC12) (initial value) (A12 in on-chip ROM invalid mode) Address output (A12) (PC12 in single chip mode) • Bit 11—PC11 Mode (PC11MD): Selects the function of the PC11/A11 pin. Bit 11: PC11MD Description General input/output (PC11) (initial value) (A11 in on-chip ROM invalid mode)
Page 663 • Bit 6—PC6 Mode (PC6MD): Selects the function of the PC6/A6 pin. Bit 6: PC6MD Description General input/output (PC6) (initial value) (A6 in on-chip ROM invalid mode) Address output (A6) (PC6 in single chip mode) • Bit 5—PC5 Mode (PC5MD): Selects the function of the PC5/A5 pin. Bit 5: PC5MD Description General input/output (PC5) (initial value) (A5 in on-chip ROM invalid mode)
Page 664: Port D I/O Register H (Pdiorh)
• Bit 0—PC0 Mode (PC0MD): Selects the function of the PC0/A0 pin. Bit 0: PC0MD Description General input/output (PC0) (initial value) (A0 in on-chip ROM invalid mode) Address output (A0) (PC0 in single chip mode) 18.3.9 Port D I/O Register H (PDIORH) The port D I/O register H (PDIORH) is a 16-bit read/write register that selects input or output for the most significant sixteen port D pins.
Page 665: Port D I/O Register L (Pdiorl)
18.3.10 Port D I/O Register L (PDIORL) The port D I/O register L (PDIORL) is a 16-bit read/write register that selects input or output for the least significant sixteen port D pins. Bits PD15IOR–PD0IOR correspond to the PD15/D15 pin to PD0/D0 pin. PDIORL is enabled when the port D pins function as general input/outputs (PD15–PD0).
Page 666 Port D Control Register H1 (PDCRH1): Bit: PD31 PD31 PD30 PD30 PD29 PD29 PD28 PD28 Initial value: R/W: Bit: PD27 PD27 PD26 PD26 PD25 PD25 PD24 PD24 Initial value: R/W: • Bits 15 and 14—PD31 Mode 1, 0 (PD31MD1 and PD31MD0): These bits select the function of the PD31/D31/ADTRG pin.
Page 667 • Bits 11 and 10—PD29 Mode 1, 0 (PD29MD1 and PD29MD0): These bits select the function of the PD29/D29/CS3 pin. Bit 11: Bit 10: PD29MD1 PD29MD0 Description General input/output (PD29) (initial value) (D29 with no ROM and CS0 = 32 bit width) Data input/output (D29) (PD29 in single chip mode) Chip select output (CS3) (PD29 in single chip mode, D29 with no ROM and CS0 = 32 bit width)
Page 668 • Bits 5 and 4—PD26 Mode 1, 0 (PD26MD1 and PD26MD0): These bits select the function of the PD26/D26/DACK0 pin. Bit 5: Bit 4: PD26MD1 PD26MD0 Description General input/output (PD26) (initial value) (D26 with no ROM and CS0 = 32 bit width) Data input/output (D26) (PD26 in single chip mode) DMA transfer request received output (DACK0) (PD26 in single chip mode, and D26 with no ROM and CS0 = 32 bit width)
Page 669 Port D Control Register H2 (PDCRH2): Bit: PD23 PD23 PD22 PD22 PD21 PD21 PD20 PD20 Initial value: R/W: Bit: PD19 PD19 PD18 PD18 PD17 PD17 PD16 PD16 Initial value: R/W: • Bits 15 and 14—PD23 Mode 1, 0 (PD23MD1 and PD23MD0): These bits select the function of the PD23/D23/IRQ7 pin.
Page 670 • Bits 11 and 10—PD21 Mode 1, 0 (PD21MD1 and PD21MD0): These bits select the function of the PD21/D21/IRQ5 pin. Bit 11: Bit 10: PD21MD1 PD21MD0 Description General input/output (PD21) (initial value) (D21 with no ROM and CS0 = 32 bit width) Data input/output (D21) (PD21 in single chip mode) Interrupt request input (IRQ5) Reserved...
Page 671 • Bits 5 and 4—PD18 Mode 1, 0 (PD18MD1 and PD18MD0): These bits select the function of the PD18/D18/IRQ2 pin. Bit 5: Bit 4: PD18MD1 PD18MD0 Description General input/output (PD18) (initial value) (D18 with no ROM and CS0 = 32 bit width Data input/output (D18) (PD18 in single chip mode) Interrupt request input (IRQ2) Reserved...
Page 672: Port D Control Register L (Pdcrl)
18.3.12 Port D Control Register L (PDCRL) PDCRL is a 16-bit read/write register that selects the multiplexed pin functions for the least significant sixteen port D pins. There are instances when these register settings will be ignored, depending on the operation mode. On-Chip ROM-Disabled Extended Mode: •...
Page 673 • Bit 15—PD15 Mode (PD15MD): Selects the function of the PD15/D15 pin. Bit 15: PD15MD Description General input/output (PD15) (initial value) (D15 in on-chip ROM invalid mode) Data input/output (D15) (PD15 in single chip mode) • Bit 14—PD14 Mode (PD14MD): Selects the function of the PD14/D14 pin. Bit 14: PD14MD Description General input/output (PD14) (initial value) (D14 in on-chip ROM invalid mode) Data input/output (D14) (PD14 in single chip mode)
Page 674 • Bit 9—PD9 Mode (PD9MD): Selects the function of the PD9/D9 pin. Bit 9: PD9MD Description General input/output (PD9) (initial value) (D9 in on-chip ROM invalid mode) Data input/output (D9) (PD9 in single chip mode) • Bit 8—PD8 Mode (PD8MD): Selects the function of the PD8/D8 pin. Bit 8: PD8MD Description General input/output (PD8) (initial value) (D8 in on-chip ROM invalid mode)
Page 675 • Bit 3—PD3 Mode (PD3MD): Selects the function of the PD3/D3 pin. Bit 3: PD3MD Description General input/output (PD3) (initial value) (D3 in on-chip ROM invalid mode) Data input/output (D3) (PD3 in single chip mode) • Bit 2—PD2 Mode (PD2MD): Selects the function of the PD2/D2 pin. Bit 2: PD2MD Description General input/output (PD2) (initial value) (D2 in on-chip ROM invalid mode)
Page 676: Port E I/O Register (Peior)
18.3.13 Port E I/O Register (PEIOR) The port E I/O register (PEIOR) is a 16-bit read/write register that selects input or output for the 16 port E pins. Bits PE15IOR–PE0IOR correspond to pins PE15/TIOC4D/DACK1/IRQOUT– PE0/TIOC0A/DREQ0. PEIOR is enabled when the port E pins function as general input/outputs (PE15–PE0) or TIOC pin of the MTU.
Page 677 Port E Control Register 1 (PECR1): Bit: PE15 PE15 PE14 PE14 PE13 PE13 — PE12MD Initial value: R/W: Bit: — PE11MD — PE10MD — PE9MD — PE8MD Initial value: R/W: • Bits 15 and 14—PE15 Mode 1, 0 (PE15MD1 and PE15MD0): These bits select the function of the PE15/TIOC4D/DACK1/IRQOUT pin.
Page 678 • Bits 11 and 10—PE13 Mode 1, 0 (PE13MD1 and PE13MD0): These bits select the function of the PE13/TIOC4B/MRES pin. Bit 11: Bit 10: PE13MD1 PE13MD0 Description General input/output (PE13) (initial value) MTU input capture input/output compare output (TIOC4B) Manual reset input (MRES) Reserved •...
Page 679 • Bit 2—PE9 Mode (PE9MD): Selects the function of the PE9/TIOC3B pin. Bit 2: PE9MD Description General input/output (PE9) (initial value) MTU input capture input/output compare output (TIOC3B) • Bit 1—Reserved: This bit always reads as 0. The write values should always be 0. •...
Page 680 • Bit 12—PE6 Mode (PE6MD): Selects the function of the PE6/TIOC2A pin. Bit 12: PE6MD Description General input/output (PE6) (initial value) MTU input capture input/output compare output (TIOC2A) • Bit 11—Reserved: This bit always reads as 0. The write value should always be 0. •...
Page 681: Irqout Function Control Register
• Bits 5 and 4—PE2 Mode 1, 0 (PE2MD1 and PE2MD0): These bits select the function of the PE2/TIOC0C/DREQ1 pin. Bit 5: Bit 4: PE2MD1 PE2MD0 Description General input/output (PE2) (initial value) MTU input capture input/output compare output (TIOC0C) DREQ1 request receive input (PE2 in single chip mode) Reserved •...
Page 682 The IFCR is initialized to H'0000 by external power-on reset but is not initialized for manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is maintained. Bit: — — — — — — — — Initial value: R/W: Bit:...
Page 683: Cautions On Use
18.4 Cautions on Use For the I/O ports and pins with multiplexing of DREQ or IRQ, switching from the port input Low level condition to IRQ or DREQ edge detection will detect the concerned edge.
Page 685: Section 19 I/O Ports (I/O)
Section 19 I/O Ports (I/O) 19.1 Overview There are six ports, A, B, C, D, E, and F. The pins of the ports are multiplexed for use as general- purpose I/Os (the port F pins are general input) or for other functions. Use the pin function controller (PFC) to select the function of multiplexed pins.
Page 686 Table 19.1 Port A, FP-112/TFP-120 Version ROM Disabled Extended ROM Enabled Extended Mode (Modes 0, 1) Mode (Mode 2) Single Chip Mode PA15 (I/O)/CK (output) PA15 (I/O)/CK (output) PA15 (I/O)/CK (output) RD (output) PA14 (I/O)/RD (output) PA14 (I/O) WRH (output) PA13 (I/O)/WRH (output) PA13 (I/O) WRL (output)
Page 687 Table 19.2 Port A, FP-144 Version ROM Disabled Extended ROM Enabled Extended Mode (Modes 0, 1) Mode (Mode 2) Single Chip Mode WRHH (output) PA23 (I/O)/WRHH (output) PA23 (I/O) WRHL (output) PA22 (I/O)/WRHL (output) PA22 (I/O) PA21 (I/O)/CASHH (output) PA21 (I/O)/CASHH (output) PA21 (I/O) PA20 (I/O)/CASHL (output) PA20 (I/O)/CASHL (output)
Page 688: Register Configuration
19.2.1 Register Configuration Table 19.3 summarizes the port A register. Table 19.3 Port A Register Name Abbreviation Initial Value Address Access Size Port A data register H PADRH H'0000 H'FFFF8380 8, 16, 32 H'FFFF8381 Port A data register L PADRL H'0000 H'FFFF8382 8, 16, 32...
Page 689: Port A Data Register L (Padrl)
19.2.3 Port A Data Register L (PADRL) PADRL is a 16-bit read/write register that stores data for port A. The bits PA15DR–PA0DR correspond to the PA15/CK–PA0/RXD0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PADRL; when PADRL is read, the register value will be output regardless of the pin status.
Page 690: Port B
19.3 Port B Port B is a 10-pin input/output port as listed in table 19.5. Table 19.5 Port B ROM Disabled Extended ROM Enabled Extended Mode (Modes 0, 1) Mode (Mode 2) Single Chip Mode PB9 (I/O)/IRQ7 (input)/A21 PB9 (I/O)/IRQ7 (input)/A21 PB9 (I/O)/IRQ7 (input)/ADTRG (output)/ADTRG (input) (output)/ADTRG (input)
Page 691: Port B Data Register (Pbdr)
19.3.2 Port B Data Register (PBDR) PBDR is a 16-bit read/write register that stores data for port B. The bits PB9DR–PB0DR correspond to the PB9/IRQ7/A21/ADTRG–PB0/A16 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PBDR; when PBDR is read, the register value will be read regardless of the pin status.
Page 692: Port C
19.4 Port C Port C is a 16 pin input/output port as listed in table 19.8. Table 19.8 Port C ROM Disabled Extended ROM Enabled Extended Mode (Modes 0, 1) Mode (Mode 2) Single Chip Mode A15 (output) PC15 (I/O)/A15 (output) PC15 (I/O) A14 (output) PC14 (I/O)/A14 (output)
Page 693: Port C Data Register (Pcdr)
19.4.2 Port C Data Register (PCDR) PCDR is a 16-bit read/write register that stores data for port C. The bits PC15DR–PC0DR correspond to the PC15/A15–PC0/A0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PCDR; when PCDR is read, the register value will be read regardless of the pin status.
Page 694: Port D
19.5 Port D There are two versions of port D: • FP-112 • FP-144 In the FP-112 version, port D is a 16-pin input/output port, as shown in table 19.11. Table 19.11 Port D, FP-112 Version Extended Mode Extended Mode Without ROM Without ROM Extended Mode With...
Page 695 Table 19.12 Port D, FP-144 Version Extended Mode Extended Mode Without ROM Without ROM Extended Mode With (Mode 0) (Mode 1) ROM (Mode 2) Single Chip Mode PD31 (I/O)/D31 (I/O)/ D31 (I/O) PD31 (I/O)/D31 (I/O)/ PD31 (I/O)/ADTRG ADTRG (input) ADTRG (input) (input) PD30 (I/O)/D30 (I/O)/ D30 (I/O)
Page 696: Register Configuration
Table 19.12 Port D, FP-144 Version (cont) Extended Mode Extended Mode Without ROM Without ROM Extended Mode With (Mode 0) (Mode 1) ROM (Mode 2) Single Chip Mode D15 (I/O) D15 (I/O) PD15 (I/O)/D15 (I/O) PD15 (I/O) D14 (I/O) D14 (I/O) PD14 (I/O)/D14 (I/O) PD14 (I/O) D13 (I/O)
Page 697: Port D Data Register H (Pddrh)
19.5.2 Port D Data Register H (PDDRH) PDDRH is a 16-bit read/write register that stores data for port D. The bits PD31DR–PD16DR correspond to the PD31/D31/ADTRG–PD16/D16/IRQ0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PDDRH; when PDDRH is read, the register value will be read regardless of the pin status.
Page 698: Port D Data Register L (Pddrl)
19.5.3 Port D Data Register L (PDDRL) PDDRL is a 16-bit read/write register that stores data for port D. The bits PD15DR–PD0DR correspond to the PD15/D15–PD0/D0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PDDRL; when PDDRL is read, the register value will be read regardless of the pin status.
Page 699: Port E
19.6 Port E Port E is a 16-pin input/output port, as listed in table 19.15. Table 19.15 Port E Extended Modes (Modes 0, 1, 2) Single Chip Mode PE15 (I/O)/TIOC4D (I/O)/DACK1 PE15 (I/O)/TIOC4D (I/O)/IRQOUT (output) (output)/IRQOUT (output) PE14 (I/O)/TIOC4C (I/O)/DACK0 (output)/AH PE14 (I/O)/TIOC4C (I/O) (output) PE13 (I/O)/TIOC4B (I/O)/MRES (input)
Page 700: Port E Data Register (Pedr)
19.6.2 Port E Data Register (PEDR) PEDR is a 16-bit read/write register that stores data for port E. The bits PE15DR–PE0DR correspond to the PE15/TIOC4D/DACK1/IRQOUT–PE0/TIOC0A/DREQ0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PEDR; when PEDR is read, the register value will be read regardless of the pin status.
Page 701: Port F
19.7 Port F Port F is an 8-pin input port. All modes are configured in the following way: • PF7 (input)/AN7 (input) • PF6 (input)/AN6 (input) • PF5 (input)/AN5 (input) • PF4 (input)/AN4 (input) • PF3 (input)/AN3 (input) • PF2 (input)/AN2 (input) •...
Page 702 Table 19.19 Read/Write Operation of the Port F Data Register (PFDR) Pin I/O Pin Function Read Write Input Ordinary Pin status is read Ignored (no effect on pin status) ANn: analog input 1 is read Ignored (no effect on pin status) n=7-0...
Page 703: Section 20 64/128/256Kb Mask Rom
Section 20 64/128/256kB Mask ROM 20.1 Overview This LSI is available with 64 kbytes, 128 kbytes, or 256 kbytes of on-chip ROM. The on-chip ROM is connected to the CPU, direct memory access controller (DMAC) and data transfer controller (DTC) through a 32-bit data bus (figures 20.1, 20.2, and 20.3). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16, and 32-bit widths.
Page 704 Internal data bus (32 bits) H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 On-chip ROM H'0001FFFC H'0001FFFD H'0001FFFE H'0001FFFF Figure 20.2 Mask ROM Block Diagram (128-kbyte Version) Internal data bus (32 bits) H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 On-chip ROM H'0003FFFC H'0003FFFD...
Page 705 The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins MD3–MD0 as shown in table 20.1. If you are using the on-chip ROM, select mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is allocated to addresses H'00000000–H'0000FFFF of memory area 0 for the 64-kbyte version, H'00000000–...
Page 707: Section 21 128Kb Prom
Section 21 128kB PROM 21.1 Overview This LSI has 128 kbytes of on-chip PROM.The on-chip ROM is connected to the CPU, the direct memory access controller (DMAC) and the data transfer controller (DTC) through a 32-bit data bus (figures 21.1). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16, and 32-bit widths.
Page 708: Prom Mode
Table 21.1 Operating Modes and ROM Mode Setting Pin Operating Mode MD3 MD2 MD1 MD0 Area 0 Mode 0 (MCU mode 0) On-chip ROM invalid, external 8-bit space (112 pin and 120 pin), external 16-bit space (144 pin) Mode 1 (MCU mode 1) On-chip ROM invalid, external 16-bit space (112 pin and 120 pin), external 32-bit space (144 pin) Mode 2 (MCU mode 2)
Page 709 EPROM socket HN27C101 SH7042 (112-pin version) adapter Pin number Pin name Pin name Pin number 0.1 µF RES/V PD0/D0 I/O0 PD1/D1 I/O1 PD2/D2 I/O2 PD3/D3 I/O3 PD4/D4 I/O4 PD5/D5 I/O5 PD6/D6 I/O6 PD7/D7 I/O7 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8...
Page 710 SH7042 (120-pin version) EPROM socket HN27C101 adapter Pin number Pin name Pin number Pin name 0.1 µF RES/Vpp I/O0 PD0/D0 PD1/D1 I/O1 PD2/D2 I/O2 I/O3 PD3/D3 I/O4 PD4/D4 I/O5 PD5/D5 I/O6 PD6/D6 PD7/D7 I/O7 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8...
Page 711 (144-pin version) SH7043 EPROM socket HN27C101 adapter Pin number Pin name Pin name Pin number 0.1 µF RES/V PD0/D0 I/O0 PD1/D1 I/O1 PD2/D2 I/O2 PD3/D3 I/O3 PD4/D4 I/O4 PD5/D5 I/O5 PD6/D6 I/O6 PD7/D7 I/O7 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8...
Page 712: Prom Programming
Address for MCU Address for modes 0, 1, 2, 3 PROM mode H'00000000 H'0000 On-chip ROM space (area 0) H'0001FFFF (128-kbyte version) H'1FFFF (128-kbyte version) Figure 21.5 On-Chip ROM Memory Map 21.3 PROM Programming The PROM mode write/verify specifications are the same as those of the standard EPROM HN27C101.
Page 713: Write/Verify And Electrical Characteristics
21.3.2 Write/Verify and Electrical Characteristics Write/Verify: Writing and verification can be done using an efficient high speed, high reliability programming format. This format allows data writing that is both fast and reliable without applying voltage stress to the device. Figure 21.6 shows the basic flow of the high speed, high reliability programming format.
Page 714 < > Preliminary Start Set EPROM writer to write/verify mode = 6.0 V ± 0.25 V, = 12.5 V ± 0.3 V) Address = 0 n = 0 n + 1 → n Data write = 0.2 ms ± 5%) n = 25? Address + 1 →...
Page 715 Electrical Characteristics: Tables 21.3 and 21.4 show the electrical characteristics for programming. Figure 21.7 shows the timing. = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V, V Table 21.3 DC Characteristics (V = 0 V, Ta = 25°C ±...
Page 716 = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V, V Table 21.4 AC Characteristics (V = 0 V, Ta = 25°C ± 5°C) Measurement Item Symbol Min Max Unit Conditions Figure 21.6 * Address setup time —...
Page 717: Cautions On Writing
Write Verify Address Write data Read data Data Note: * t is defined by the values noted in the flowchart (figure 19.6). Figure 21.7 Write/Verify Timing 21.3.3 Cautions on Writing 1. Writes must always be done with the established voltage and timing. The write voltage (programming voltage) V is 12.5 V (when the EPROM writer is set for the HN27C101 Hitachi specifications, V...
Page 718: Post-Write Reliability
(125–150°C, 24–48 hours) Data read out and verify = 5.0 V) Installation on board Figure 21.8 Screening Flow If there are any abnormalities in program write/verify or program read-out verification after high temperature biasing, please contact a Renesas Technology technical representative.
Page 719: Section 22 256Kb Flash Memory (F-Ztat)
Section 22 256kB Flash Memory (F-ZTAT) 22.1 Features This LSI has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode ...
Page 720: Overview
22.2 Overview 22.2.1 Block Diagram Internal address bus Internal data bus (32-bit) FLMCR1 FLMCR2 Operation FWP pin Bus interface/controller mode Mode pins EBR1 EBR2 RAMER Flash memory (256kB) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1 : Block specification register 1 EBR2...
Page 721: Mode Transition Diagram
22.2.2 Mode Transition Diagram When the mode pins and the FWP pin are set in the reset state and a reset start is executed, the microcomputer enters one of the operating modes shown in figure 22.2. In user mode, flash memory can be read but not programmed or erased.
Page 722: Onboard Program Mode
22.2.3 Onboard Program Mode Boot mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the LSI (originally incorporated in the chip) is programming control program and new started and the programming control program in...
Page 723: User Program Mode
User program mode 1. Initial state 2. Programming/erase control program transfer The FWP assessment program that confirms that When user program mode is entered, user user program mode has been entered, and the software confirms this fact, executes transfer program that will transfer the programming/erase program in the flash memory, and transfers the control program from flash memory to on-chip programming/erase control program to RAM.
Page 724: Flash Memory Emulation In Ram
22.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. •...
Page 725: Differences Between Boot Mode And User Program Mode
• User Program Mode Flash memory Programming control program execution state Application program Overlap RAM (Programming data) Programming data Figure 22.6 Programming to the Flash Memory 22.2.5 Differences between Boot Mode and User Program Mode Table 22.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase...
Page 726: Block Configuration
22.2.6 Block Configuration The flash memory is divided into seven 32 kbyte blocks, one 28 kbyte blocks, and four 1 kbyte blocks. Address H'00000 32kbyte 32kbyte 32kbyte 32kbyte 32kbyte 32kbyte 32kbyte 28kbyte 1kbyte 1kbyte 1kbyte 1kbyte Address H'3FFFF Figure 22.7 Block Configuration...
Page 727: Pin Configuration
22.3 Pin Configuration The flash memory is controlled by the pins shown in table 22.2. Table 22.2 Pin Configuration Pin Name Abbreviation I/O Function Power-on reset Input Power-on reset Flash write protect Input Flash program/erase protection by hardware Mode 3 Input Set operation mode of LSI Mode 2...
Page 728: Description Of Registers
22.5 Description of Registers 22.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000–H'1FFFF is entered by setting SWE to 1 when FWE = 1, then setting the EV1 or PV1 bit.
Page 729 Bit 5: ESU1 Description Erase setup release (Initial value) Erase setup [Setting condition] When FWE=1 and SWE=1 • Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode (applicable addresses: H'00000–H'1FFFFF). Do not set the SWE, ESU1, EV1, PV1, E1, or P1 bit at the same time.
Page 730: Flash Memory Control Register 2 (Flmcr2)
• Bit 1—Erase 1 (E1): Selects erase mode transition or release (applicable addresses: H'00000– H'1FFFF). Do not set the SWE, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1: E1 Description Erase mode release (Initial value) Transition to erase mode [Setting condition] When FWE=1, SWE=1, and ESU1=1 •...
Page 731 Bit: FLER — ESU2 PSU2 Initial value: R/W: • Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state.
Page 732 • Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or release (applicable addresses: H'20000–H'3FFFF). Do not set the ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3: EV2 Description Erase verify mode release (Initial value) Transition to the erase verify mode [Setting condition] When FWE=1 and SWE=1 •...
Page 733: Erase Block Register 1 (Ebr1)
22.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset and standby mode, when a high level is input to the FWP pin, and when a low level is input to the FWP pin and the SWE bit in FLMCR1 is not set.
Page 734: Ram Emulation Register (Ramer)
Table 22.4 Flash Memory Erase Blocks Block (size) Addresses EB0 (32kB) H'000000–H'007FFF EB1 (32kB) H'008000–H'00FFFF EB2 (32kB) H'010000–H'017FFF EB3 (32kB) H'018000–H'01FFFF EB4 (32kB) H'020000–H'027FFF EB5 (32kB) H'028000–H'02FFFF EB6 (32kB) H'030000–H'037FFF EB7 (28kB) H'038000–H'03EFFF EB8 (1kB) H'03F000–H'03F3FF EB9 (1kB) H'03F400–H'03F7FF EB10 (1kB) H'03F800–H'03FBFF EB11 (1kB) H'03FC00–H'03FFFF...
Page 735 • Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. This bit is ignored when the on-chip ROM is disabled. Bit 2: RAMS Description Emulation not selected Program/erase protect of all flash memory blocks is disabled (Initial value) Emulation selected Program/erase protect of all flash memory blocks is enabled...
Page 736: On-Board Programming Mode
22.6 On-Board Programming Mode When pins are set to on-board programming mode and a power-on reset is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode.
Page 737: Boot Mode
22.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI to be used is set to channel asynchronous mode. When a reset start is executed after the LSI pins have been set to boot mode in the power-on reset state, the boot program built into the LSI is started and the programming control program prepared in the host is serially transmitted to the LSI via SCI channel 1.
Page 738 Start Set pin to the boot program mode then reset start The host continuously sends data (H'00) using a fixed bit rate This LSI measures the low period of data H'00 sent by the host This LSI calculates the bit rate and sets value to the bit rate register After adjustment of the bit rate, this LSI sends 1 byte of data H'00 to the...
Page 739 Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period of more than 1 bit Figure 22.10 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
Page 740 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 22.11. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host.
Page 741: User Program Mode
22.6.2 User Program Mode After setting FWP, the user should branch to, and execute, the previously prepared programming/erase control program. As the flash memory itself cannot be read while flash memory programming/erasing is being executed, the control program that performs programming and erasing should be run in on-chip RAM or external memory.
Page 742: Programming/Erasing Flash Memory
22.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'00000–H'1FFFF, or the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2 for addresses H'20000–H'3FFFF.
Page 743: Program-Verify Mode (N = 1 For Addresses H'0000-H'1Ffff, N = 2 For Addresses H'20000-H'3Ffff)
FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Set 200 µs as the time for one programming operation. 22.7.2 Program-Verify Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses H'20000–H'3FFFF) In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
Page 744 Start Perform programming in the erased state. Do not perform additional programming Set SWE bit in FLMCR1 on previously programmed addresses. Wait 10 µs Store 32-byte program data in reprogram data area n = 1 m = 0 Write 32-byte data in reprogram data area in RAM to flash memory consecutively Enable WDT Set PSU1(2) bit in FLMCR1(2)
Page 745 • Sample 32-byte programming program The wait time set values (number of loops) are for the case where f = 28.7 MHz. For other frequencies, the set value is given by the following expression: Wait time (µs) × f (MHz) ÷ 4 Registers Used R4 (input): Program data storage address...
Page 746 MOV.L @R12+,R1 MOV.L R1,@R0 ADD.L #4,R0 ADD.L #-1,R13 CMP/PL COPY_LOOP ; Initialize GBR MOV.L #H’FFFF8500,R0 R0,GBR MOV.L #Wait10u,R3 ; Initialize R0 to FLCMR1 address MOV.L #FLMCR1,R0 ; Set SWE OR.B #SWESET,@(R0,GBR) ; Wait 10 µs Wait_1 SUBC R2,R3 Wait_1 MOV.L #H’20000,R9 CMP/GT R5,R9...
Page 747 MOV.W R3,@R1 MOV.L #Wait50u,R3 ; Set PSU OR.B #PSU1SET,@(R0,GBR) ; Wait 50 µs Wait_2 SUBC R2,R3 MOV.L #Wait200u,R3 ; Set P OR.B #P1SET,@(R0,GBR) ; Wait 200 µs Wait_3 SUBC R2,R3 Wait_3 MOV.L #Wait10u,R3 ; Clear P AND.B #P1CLEAR,@(R0,GBR) ; Wait 10 µs Wait_4 SUBC R2,R3...
Page 748 VerifyLoop .EQU ; Write H'FF to verify address MOV.L R11,@R12 ; Reprogram data RAM (PdataBuff) initialization MOV.L R11,@R3 MOV.L #Wait2u,R7 ; Wait 2 µs Wait_7 SUBC R2,R7 Wait_7 MOV.L @R12+,R7 MOV.L @R1+,R8 ; Verify CMP/EQ R7,R8 Verify_OK ; Verify NG, m <- 1 MOV.L #1,R10 ;...
Page 749: Erase Mode (N = 1 For Addresses H'0000-H'1Ffff, N = 2 For Addresses H'20000-H'3Ffff)
; R7 <- OK (return value) MOV.L #OK,R7 Program_end .EQU MOV.B #H’00,R0 ; Clear SWE MOV.B R0,@(FLMCR1,GBR) .ALIGN PdataBuff .RES.B 22.7.3 Erase Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses H'20000– H'3FFFF) When erasing flash memory, the erase/erase-verify flowchart shown in figure 22.14 should be followed.
Page 750: Erase-Verify Mode (N = 1 For Addresses H'00000-H'1Ffff, N = 2 For Addresses H'20000-H'3Ffff)
22.7.4 Erase-Verify Mode (n = 1 for Addresses H'00000–H'1FFFF, n = 2 for Addresses H'20000–H'3FFFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is released, then the ESUn bit is released at least 10 µs later), the watchdog timer is released after the elapse of 10 µs or more, and the operating mode is switched to erase-verify mode by setting the EVn bit in FLMCRn.
Page 751 Start Set SWE bit in FLMCR1 Wait 10 µs n = 1 Set EBR1(2) Enable WDT Set ESU1(2) bit in FLMCR1(2) Wait 200 µs Start erase Set E1(2) bit in FLMCR1(2) Wait 5 ms Clear E1(2) bit in FLMCR1(2) Halt erase Wait 10 µs Clear ESU1(2) bit in FLMCR1(2) Wait 10 µs...
Page 752 • Sample one-block erase program The wait time set values (number of loops) are for the case where f = 28.7 MHz. For other frequencies, the set value is given by the following expression: Wait time (µS) × f (MHz) ÷ 4 The WDT overflow cycle set value is for the case where f = 28.7 MHz.
Page 753 MOV.L #Wait10u,R3 MOV.L #FLMCR1,R0 ; Set SWE OR.B #SWESET,@(R0,GBR) ; Wait 10 µs EWait_1 SUBC R2,R3 EWait_1 ; Initialize n (R9) to 0 MOV.L #0,R9 MOV.B @(6,R5),R0 ; Erase memory block (EBR1) setting MOV.B R0,@(EBR1,GBR) MOV.B @(7,R5),R0 ; Erase memory block (EBR2) setting MOV.B R0,@(EBR2,GBR) MOV.L...
Page 754 ; Clear E AND.B #ECLEAR,@(R0,GBR) ; Wait 10 µs EWait_4 SUBC R2,R3 EWait_4 MOV.L #Wait10u,R3 ; Clear ESU AND.B #ESUCLEAR,@(R0,GBR) ; Wait 10 µs EWait_5 SUBC R2,R3 EWait_5 ; Disable WDT MOV.L #WDT_TCSR,R1 MOV.W #H’A55F,R3 MOV.W R3,@R1 MOV.L #Wait20u,R3 ; Set EV OR.B #EVSET,@(R0,GBR) ;...
Page 755 ; R7 <- OK (return value) MOV.L #OK,R7 ; Verify OK FlashErase_end BlockVerify_NG .EQU ; Verify NG, n <- n + 1 ADD.L #1,R9 MOV.L #Wait5u,R3 ; Clear EV AND.B #EVCLEAR,@(R0,GBR) ; Wait 5 µs EWait_9 SUBC R2,R3 EWait_9 ; If n > MAXErase then erase NG MOV.L #MAXErase,R7 CMP/EQ...
Page 756: Protection
22.8 Protection There are two kinds of flash memory program/erase protection, hardware protection and software protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2).
Page 757: Software Protection
22.8.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or the P2 or E2 bit in flash memory control register 2 (FLMCR2), does not cause a transition to program mode or erase mode.
Page 758: Error Protection
22.8.3 Error Protection In error protection, an error is detected when microcomputer runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the SH7051 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
Page 759 Reset or standby Program mode (hardware protection) Erase mode RES = 0 RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 FLMCR1, FLMCR2, EBR1, EBR2 Error initialization state RES = 0 Error protection mode Error protection mode Standby mode (software standby) RD VF PR ER FLER = 1...
Page 760: Flash Memory Emulation In Ram
22.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 761 H'000000 Flash memory EB0 to 7 This area can be accessed from both RAM and flash memory H'03F000 H'03F400 H'03F800 EB10 H'03FC00 EB11 H'03FFFF On-chip RAM H'FFFFF800 H'FFFFFBFF Figure 22.17 Example of RAM Overlap Operation Example in which Flash Memory Block Area (EB8) is Overlapped 1.
Page 762: Note On Flash Memory Programming/Erasing
22.10 Note on Flash Memory Programming/Erasing In the on-board programming modes (user mode and user program mode), NMI input should be disabled to give top priority to the program/erase operations (including RAM emulation). 22.11 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes.
Page 763: 22.11.1 Socket Adapter Pin Correspondence Diagrams
22.11.1 Socket Adapter Pin Correspondence Diagrams Connect the socket adapter to the chip as shown in figures 22.19 and 22.20. This will enable conversion to a 32-pin arrangement. The on-chip ROM memory map is shown in figure 22.18, and socket adapter pin correspondence diagrams in figures 22.19 and 22.20. Addresses in Addresses in MCU mode...
Page 764 Socket Adapter HD64F7044 (112-Pin) HN28F101P (32 Pins) (Conversion to 32-Pin Pin No. Pin Name Pin No. Pin Name Arrangement) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 21, 37, 46, 49, 50, 65, 73, 75, 76, 79, 100, 103 Legend 3, 23, 27, 33, 39, 55, 61, 71 FWE: Flash write enable...
Page 765 Socket Adapter HD64F7045 (144-Pin) HN28F101P (32 Pins) (Conversion to 32-Pin Pin No. Pin Name Pin No. Pin Name Arrangement) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 12, 26, 40, 63, 77, 85, 95, 97, 98, 103, 112, 127, 128, 131, 132, 135, 136 Legend 6, 14, 28, 35, 42, 55, 61,...
Page 766: 22.11.2 Programmer Mode Operation
22.11.2 Programmer Mode Operation Table 22.11 shows how the different operating modes are set when using programmer mode, and table 22.12 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. •...
Page 767: 22.11.3 Memory Read Mode
Table 22.12 Commands of the Programmer Mode First Cycle Second Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode write H'00 read Dout Auto-program mode write H'40 write Auto-erase mode write H'20 write H'20 Status read mode write H'71...
Page 768 Command write Memory read mode Address stable A16-0 nxtc I/O7-0 Note: Data is latched on the rising edge of WE. Figure 22.21 Timing Waveforms for Memory Read after Memory Write Table 22.14 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: V = 5.0 V ±10%, V = 0 V, T...
Page 769 Memory read mode Other mode command write Address stable A16-0 nxtc I/O7-0 Note: Do not enable WE and OE at the same time. Figure 22.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 22.15 AC Characteristics in Memory Read Mode (Conditions: V = 5.0 V ±10%, = 0 V, T = 25°C ±5°C)
Page 770 Address stable Address stable A16-0 I/O7-0 Figure 22.23 CE and OE Enable State Read Timing Waveforms Address stable Address stable A16-0 I/O7-0 Figure 22.24 CE and OE Clock System Read Timing Waveforms...
Page 771: 22.11.4 Auto-Program Mode
22.11.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3.
Page 772 Table 22.16 AC Characteristics in Auto-Program Mode (Conditions: V = 5.0 V ±10%, = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Command write cycle µs nxtc CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time wsts...
Page 773: 22.11.5 Auto-Erase Mode
22.11.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing.. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status output uses the auto-erase operation end identification pin).
Page 774: 22.11.6 Status Read Mode
A16-0 nxtc nxtc ests erase I/O7 Erase complete verify signal I/O6 Erase normal complete verify signal I/O5-0 H'20 H'20 H'00 Figure 22.26 Auto-Erase Mode Timing Waveforms 22.11.6 Status Read Mode Table 22.18 AC Characteristics in Status Read Mode (Conditions: V = 5.0 V ±10%, = 0 V, T = 25°C ±5°C)
Page 775: 22.11.7 Status Polling
A16-0 nxtc nxtc nxtc I/O7-0 H'71 H'71 Note : I/O2 and I/O3 are undefined. Figure 22.27 Status Read Mode Timing Waveforms Table 22.19 Return Commands for the Status Read Mode Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Attribute Normal Command...
Page 776: 22.11.8 Programmer Mode Transition Time
Table 22.20 Status Polling Output Truth Table During Internal Pin Name Operation Abnormal End Normal End I/O7 I/O6 I/O5–0 22.11.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 22.21 Stipulated Transition Times to Command Wait State Item Symbol...
Page 777: 22.11.9 Cautions Concerning Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
Page 779: Section 23 Ram
Section 23 RAM 23.1 Overview The SH7040 series has 4 kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access controller (DMAC)/data transfer controller (DTC) with a 32-bit data bus (figure 23.1). The CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. The DMAC can access 8 or 16 bit widths.
Page 781: Section 24 Power-Down State
Section 24 Power-Down State 24.1 Overview In the power-down state, the CPU functions are halted. This enables a great reduction in power consumption. 24.1.1 Power-Down States The power-down state is effected by the following two modes: • Sleep mode • Standby mode Table 24.1 describes the transition conditions for entering the modes from the program execution state as well as the CPU and peripheral function status in each mode and the procedures for canceling each mode.
Page 782: Related Register
24.1.2 Related Register Table 24.2 shows the register used for power-down state control. Table 24.2 Related Register Name Abbreviation Initial Value Address Access Size Standby control register SBYCR H'1F H'FFFF8614 8, 16, 32 24.2 Standby Control Register (SBYCR) The standby control register (SBYCR) is a read/write 8-bit register that sets the transition to standby mode, and the port status in standby mode.
Page 783: Sleep Mode
24.3 Sleep Mode 24.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the program execution state to the sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run during the sleep mode.
Page 784 Table 24.3 Register States in the Standby Mode Registers that Registers with Module Registers Initialized Retain Data Undefined Contents Interrupt controller — All registers — (INTC) User break controller — All registers — (UBC) Data transfer controller All registers (excluding transfer —...
Page 785: Canceling The Standby Mode
Table 24.3 Register States in the Standby Mode (cont) Registers that Registers with Module Registers Initialized Retain Data Undefined Contents Pin function controller — All registers — (PFC) I/O port (I/O) — All registers — Power-down state — Standby control —...
Page 786: Standby Mode Application Example
24.4.3 Standby Mode Application Example This example describes a transition to standby mode on the falling edge of an NMI signal, and a cancellation on the rising edge of the NMI signal. The timing is shown in figure 24.1. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) of the ICR is set to 0 (falling edge detection), the NMI interrupt is accepted.
Page 787: Section 25 Electrical Characteristics (5V, 28.7 Mhz Version)
Section 25 Electrical Characteristics (5V, 28.7 MHz Version) 25.1 Absolute Maximum Ratings Table 25.1 shows the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage –0.3 to +7.0 Programmable voltage (ZTAT version only) –0.3 to +13.5 Input voltage (other than A/D ports) –0.3 to V + 0.3...
Page 788: Dc Characteristics
25.2 DC Characteristics = 5.0 V ± 10%, AV = 5.0 V ± 10%, Table 25.2 DC Characteristics (Conditions: V ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = –20 to +75° C) Measurement Item Symbol Min Unit...
Page 789 = 5.0 V ± 10%, AV = 5.0 V ± 10%, Table 25.2 DC Characteristics (Conditions: V ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = –20 to +75°C) (cont) Measurement Item Symbol Min Typ Max Unit Conditions...
Page 790: Ac Characteristics
= 5.0 V ± 10%, AV Table 25.3 Permitted Output Current Values (Conditions: V 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = –20 to +75° C) Item Symbol Unit 2.0 * Output low-level permissible current (per pin)
Page 791 t cyc 1/2V 1/2V Figure 25.1 System Clock Timing EXcyc EXTAL 1/2V 1/2V Figure 25.2 EXTAL Clock Input Timing OSC2 OSC1 Figure 25.3 Oscillation Settling Time...
Page 792: Control Signal Timing
25.3.2 Control Signal Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, Table 25.5 Control Signal Timing (Conditions: V ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = –20 to +75° C) Item Symbol Unit...
Page 793 RESf RESr RESS RESS RESW MRESS MRESS MRES MRESW Figure 25.4 Reset Input Timing NMIr, NMIf NMIH NMIS V IH V IL IRQEH IRQES IRQ edge IRQLS IRQ level Figure 25.5 Interrupt Signal Input Timing...
Page 794 IRQOD IRQOD IRQOUT Figure 25.6 Interrupt Signal Output Timing BRQS BRQS BREQ (Input) BACKD1 BACKD2 BACK (Output) RD, RDWR, RAS, CASxx, CSn, WRxx A21–A0, D31–D0 During the bus-release period of a self-refresh, RAS, CASx, and RDWR are output. Note: Figure 25.7 Bus Right Release Timing...
Page 795: Bus Timing
25.3.3 Bus Timing Table 25.6 Bus Timing (Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V – AV = AV = 0 V, Ta = – 20 to +75°C) Item Symbol Min Max Unit Figure...
Page 796: 10%, Av
Table 25.7 Bus Timing (Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = – 20 to +75°C) Item Symbol Min Unit Figure Write address setup time —...
Page 797 A21–A0 CSD1 CSD2 RSD1 RSD2 (During read) D31–D0 (During read) WSD1 WSD2 WRxx (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn is specified from fastest negate timing of A21–A0, CSn, and RD. Note: Figure 25.8 Basic Cycle (No Waits)
Page 798 A21–A0 CSD1 CSD2 RSD1 RSD2 (During read) D31–D0 (During read) WSD1 WSD2 WRxx (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn is specified from fastest negate timing of A21–A0, CSn, and RD. Note: t Figure 25.9 Basic Cycle (Software Waits)
Page 799 A21–A0 (During read) D31–D0 (During read) WRxx (During write) D31–D0 (During write) WAIT DACKn Figure 25.10 Basic Cycle (2 Software Waits + Wait due to WAIT Signal)
Page 800 Column address Row address A21–A0 RASD1 RASD2 CASD1 CASD2 CASxx (During read) RDWR (During read) D31– D0 (During read) CASD1 CASD2 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2 WRxx (During write)
Page 801 Tcw1 Column address Row address A21–A0 RASD1 RASD2 CASD1 CASD2 CASxx (During read) RDWR (During read) D31–D0 (During read) CASD1 CASD2 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2 WRxx (During write)
Page 802 Tcw1 Tcw2 Row address Column address A21–A0 RASD1 RASD2 CASD2 CASxx CASD1 (During read) RDWR (During read) D31–D0 (During read) CASD1 CASD2 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2 WRxx...
Page 803 Tcw1 Tcw2 Tcwo Row address Column address A21–A0 RASD1 RASD2 CASD2 CASD1 CASxx (During read) RDWR (During read) D31–D0 (During read) CASD2 CASD1 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) WAIT DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2...
Page 804 A21–A0 Row address Column address Column address RASD1 RASD2 CASD1 CASD2 CASD1 CASD2 CASxx (During read) RDWR (During read) D31–D0 (During read) CASD1 CASD2 CASD1 CASD2 CASxx (During write) RWD1 RWD2 RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKD1 DACKn...
Page 805 TRr1 TRr2 TRcc RASD1 RASD2 CASD1 CASD2 CASxx RDWR Figure 25.18 Self Refresh A21–A0 CSD1 CSD2 AHD1 AHD2 RSD1 RSD2 (During read) D15–D0 Address (During read) WSD1 WSD2 WRxx (During write) D15–D0 Address (During write) WAIT DACKD1 DACKD1 DACKn is specified from fastest negate timing of A21–A0, CS3, and RD. Note: t Figure 25.19 Address Data Multiplex I/O Space Cycle (1 Software Wait + External Wait)
Page 806: Direct Memory Access Controller Timing
25.3.4 Direct Memory Access Controller Timing Table 25.8 Direct Memory Access Controller Timing (Conditions: V = 5.0 V ± 10%, = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV V, Ta = – 20 to +75°C) Item Symbol Unit...
Page 807 DREQ0 DREQ1 Edge DRQW Figure 25.21 DREQ0 and DREQ1 Input Timing (2) DRAKD DRAKD DRAKn Figure 25.22 DRAK Output Delay Time...
Page 808: Multifunction Timer Pulse Unit Timing
25.3.5 Multifunction Timer Pulse Unit Timing Table 25.9 Multifunction Timer Pulse Unit Timing (Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = –...
Page 809: I/O Port Timing
25.3.6 I/O Port Timing Table 25.10 I/O Port Timing (Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = – 20 to +75°C) Item Symbol Unit...
Page 810: Watchdog Timer Timing
25.3.7 Watchdog Timer Timing Table 25.11 Watchdog Timer Timing (Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = – 20 to +75°C) Item Symbol Unit...
Page 811: Serial Communication Interface Timing
25.3.8 Serial Communication Interface Timing Table 25.12 Serial Communication Interface Timing (Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = – 20 to +75°C) Item Symbol Unit...
Page 812: High-Speed A/D Converter Timing (Excluding A Mask)
25.3.9 High-speed A/D Converter Timing (excluding A mask) Table 25.13 High-speed A/D Converter Timing (Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV = 0 V, Ta = – 20 to +75°C) Item Symbol...
Page 813 φ Address Write signal ADST Sampling timing CONV : A/D conversion start delay time : Input sampling time : A/D conversion time CONV : Operation time Figure 25.30 Analog Conversion Timing...
Page 814: Mid-Speed Converter Timing (A Mask)
25.3.10 Mid-speed Converter Timing (A mask) Table 25.14 shows Mid-speed converter timing Table 25.14 Mid-speed Converter Timing (Conditions:Vcc=5.0V ± 10%, AVcc=5.0V ± 10%, AVcc=Vcc ± 10%, AVref=4.5V to Avcc, Vss=AVss=0V, Ta=-20 to ± 75°C) Item Symbol Unit Figure External trigger input pulse width —...
Page 815 Address Write signal Input sampling timing CONV Legend: : ADCSR write cycle : ADCSR address : A/D conversion start delay time : Input sampling time : A/D conversion time CONV Figure 25.32 Analog Conversion Timing...
Page 816: 25.3.11 Measuring Conditions For Ac Characteristics
25.3.11 Measuring Conditions for AC Characteristics • Input reference levels:  High level: 2.2 V  Low level: 0.8 V • Output reference levels:  High level: 2.0 V  Low level: 0.8 V DUT output output pin Note: is set with the following pins, including the total capacitance of the measurement equipment etc: CK, RAS, CASxx, RDWR, CS0–CS3, AH, BREQ, BACK, DACK0, 30 pF:...
Page 817: A/D Converter Characteristics
25.4 A/D Converter Characteristics Table 25.15 A/D Converter Timing (excluding A mask) (Conditions: V = 5.0 V ± 10%, = 5.0 V ± 10%, AV ± 10%, AV = 4.5 V to AV = AV V, Ta = – 20 to +75°C) 28.7 MHz Item Unit...
Page 819: Section 26 Electrical Characteristics (3.3V, 16.7 Mhz Version)
Section 26 Electrical Characteristics (3.3V, 16.7 MHz Version) 26.1 Absolute Maximum Ratings Table 26.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage –0.3 to +7.0 Programmable voltage (ZTAT version only) –0.3 to +13.5 Input voltage (other than A/D ports) –0.3 to V + 0.3 Input voltage (A/D ports)
Page 820: Dc Characteristics
26.2 DC Characteristics = 3.0 * = 3.0 * Table 26.2 DC Characteristics (Conditions: V to 3.6V, AV to 3.6V, = 3.0 * ± 10%, AV to AV = AV = 0V, T = –20 to +75°C) Measurement Item Symbol Unit Conditions ×...
Page 821 = 3.0 * = 3.0 * Table 26.2 DC Characteristics (Conditions: V to 3.6V, AV to 3.6V, AV = 3.0 * ± 10%, AV to AV = AV = 0V, T = –20 to +75°C) (cont) Measurement Item Symbol Min Typ Max Unit Conditions...
Page 822: Ac Characteristics
= 3.0 * to 3.6V, AV = 3.0 * Table 26.3 Permitted Output Current Values (Conditions: V = 3.0 * to AV to 3.6V, AV ± 10%, AV = AV = 0V, T = –20 to +75°C) Item Symbol Unit Output low-level permissible current (per pin) —...
Page 823 t cyc 1/2V 1/2V Figure 26.1 System Clock Timing EXcyc EXTAL 1/2V 1/2V Figure 26.2 EXTAL Clock Input Timing OSC2 OSC1 Figure 26.3 Oscillation Settling Time...
Page 824: Control Signal Timing
26.3.2 Control Signal Timing = 3.0 * = 3.0 * Table 26.5 Control Signal Timing (Conditions: V to 3.6V, AV to 3.6V, = 3.0 * ± 10%, AV to AV = AV = 0V, T = –20 to +75°C) Item Symbol Min Unit Figure...
Page 825 RESf RESr RESS RESS RESW MRESS MRESS MRES MRESW Figure 26.4 Reset Input Timing NMIr, NMIf NMIH NMIS V IH V IL IRQEH IRQES IRQ edge IRQLS IRQ level Figure 26.5 Interrupt Signal Input Timing...
Page 826 IRQOD IRQOD IRQOUT Figure 26.6 Interrupt Signal Output Timing BRQS BRQS BREQ (Input) BACKD1 BACKD2 BACK (Output) RD, RDWR, RAS, CASxx, CSn, WRxx A21–A0, D31–D0 During the bus-release period of a self-refresh, RAS, CASx, and RDWR are output. Note: Figure 26.7 Bus Right Release Timing...
Page 827: Bus Timing
26.3.3 Bus Timing = 3.0 * = 3.0 * Table 26.6 Bus Timing (Conditions: V to 3.6V, AV to 3.6V, AV = 3.0 * ± 10%, AV to AV = AV = 0V, T = –20 to +75°C) Item Symbol Min Max Unit Figure Address delay time 26.8, 9, 11–16, 19...
Page 828 = 3.0 * = 3.0 * Table 26.7 Bus Timing (Conditions: V to 3.6V, AV to 3.6V, AV = 3.0 * ± 10%, AV to AV = AV = 0V, T = –20 to +75°C) Item Symbol Unit Figure Write address setup time —...
Page 829 A21–A0 CSD1 CSD2 RSD1 RSD2 (During read) D31–D0 (During read) WSD1 WSD2 WRxx (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn is specified from fastest negate timing of A21–A0, CSn, and RD. Note: t Figure 26.8 Basic Cycle (No Waits)
Page 830 A21–A0 CSD1 CSD2 RSD1 RSD2 (During read) D31–D0 (During read) WSD1 WSD2 WRxx (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn is specified from fastest negate timing of A21–A0, CSn, and RD. Note: t Figure 26.9 Basic Cycle (Software Waits)
Page 831 A21–A0 (During read) D31–D0 (During read) WRxx (During write) D31–D0 (During write) WAIT DACKn Figure 26.10 Basic Cycle (2 Software Waits + Wait due to WAIT Signal)
Page 832 Column address Row address A21–A0 RASD1 RASD2 CASD1 CASD2 CASxx (During read) RDWR (During read) D31– D0 (During read) CASD1 CASD2 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2 WRxx (During write)
Page 833 Tcw1 Column address Row address A21–A0 RASD1 RASD2 CASD1 CASD2 CASxx (During read) RDWR (During read) D31–D0 (During read) CASD2 CASD1 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2 WRxx (During write)
Page 834 Tcw1 Tcw2 A21–A0 Row address Column address RASD1 RASD2 CASD2 CASxx CASD1 (During read) RDWR (During read) D31–D0 (During read) CASD1 CASD2 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2 WRxx...
Page 835 Tcw1 Tcw2 Tcwo Row address Column address A21–A0 RASD1 RASD2 CASD2 CASD1 CASxx (During read) RDWR (During read) D31–D0 (During read) CASD2 CASD1 CASxx (During write) RWD1 RWD2 RDWR (During write) D31–D0 (During write) WAIT DACKD1 DACKD1 DACKn RSD1 RSD2 (During read) WSD1 WSD2...
Page 836 Row address Column address Column address A21–A0 RASD1 RASD2 CASD1 CASD2 CASD1 CASD2 CASxx (During read) RDWR (During read) D31–D0 (During read) CASD1 CASD2 CASD1 CASD2 CASxx (During write) RWD1 RWD2 RWD1 RWD2 RDWR (During write) D31–D0 (During write) DACKD1 DACKD1 DACKD1 DACKn...
Page 837 TRr1 TRr2 TRcc RASD1 RASD2 CASD1 CASD2 CASxx RDWR Figure 26.18 Self Refresh A21–A0 CSD1 CSD2 AHD1 AHD2 RSD1 RSD2 (During read) D15–D0 Address (During read) WSD1 WSD2 WRxx (During write) D15–D0 Address (During write) WAIT DACKD1 DACKD1 DACKn is specified from fastest negate timing of A21–A0, CS3, and RD. Note: t Figure 26.19 Address Data Multiplex I/O Space Cycle (1 Software Wait + External Wait)
Page 838: Direct Memory Access Controller Timing
26.3.4 Direct Memory Access Controller Timing = 3.0 * to 3.6V, AV Table 26.8 Direct Memory Access Controller Timing (Conditions: V = 3.0 * to 3.6V, AV = 3.0 * to AV ± 10%, AV = AV = 0V, T –20 to +75°C) Item Symbol Min...
Page 839 DREQ0 DREQ1 Edge DRQW Figure 26.21 DREQ0 and DREQ1 Input Timing (2) DRAKD DRAKD DRAKn Figure 26.22 DRAK Output Delay Time...
Page 840: Multifunction Timer Pulse Unit Timing
26.3.5 Multifunction Timer Pulse Unit Timing = 3.0 * to 3.6V, AV Table 26.9 Multifunction Timer Pulse Unit Timing (Conditions:V 3.0 * to 3.6V, AV = 3.0 * to AV ± 10%, AV = AV = 0V, T –20 to +75°C) Item Symbol Min Unit...
Page 841: I/O Port Timing
26.3.6 I/O Port Timing = 3.0 * to 3.6V, AV = 3.0 * to 3.6V, AV Table 26.10 I/O Port Timing (Conditions:V = 3.0 * to AV ± 10%, AV = AV = 0V, T = –20 to +75°C) Item Symbol Min Unit Figure...
Page 842: Watchdog Timer Timing
26.3.7 Watchdog Timer Timing = 3.0 * to 3.6V, AV = 3.0 * to 3.6V, Table 26.11 Watchdog Timer Timing (Conditions:V = 3.0 * to AV ± 10%, AV = AV = 0V, T = –20 to +75°C) Item Symbol Min Unit Figure WDTOVF delay time...
Page 843: Serial Communication Interface Timing
26.3.8 Serial Communication Interface Timing = 3.0 * to 3.6V, AV Table 26.12 Serial Communication Interface Timing (Conditions:V 3.0 * to 3.6V, AV = 3.0 * to AV ± 10%, AV = AV = 0V, T = –20 to +75°C) Item Symbol Min Unit...
Page 844: High-Speed A/D Converter Timing (Excluding A Mask)
26.3.9 High-speed A/D Converter Timing (excluding A mask) = 3.0 * to 3.6V, AV = 3.0 * Table 26.13 High-speed A/D Converter Timing (Conditions:V = 3.0 * to AV to 3.6V, AV ± 10%, AV = AV = 0V, T = –20 to +75°C) Item...
Page 845 φ Address Write signal ADST Sampling timing CONV : A/D conversion start delay time : Input sampling time : A/D conversion time CONV : Operation time Figure 26.30 Analog Conversion Timing...
Page 846: Mid-Speed Converter Timing (A Mask)
26.3.10 Mid-speed Converter Timing (A mask) = 3.0 * to 3.6V, AV = 3.0 * Table 26.14 Mid-speed A/D Converter Timing (Conditions:V = 3.0 * to AV to 3.6V, AV ± 10%, AV = AV = 0V, T = –20 to +75°C) Item Symbol Min...
Page 847 Address Write signal Input sampling timing CONV Legend: : ADCSR write cycle : ADCSR address : A/D conversion start delay time : Input sampling time : A/D conversion time CONV Figure 26.32 Analog Conversion Timing...
Page 848: 26.3.11 Measurement Conditions For Ac Characteristic
26.3.11 Measurement Conditions for AC Characteristic • Input reference levels:  High level: 2.2 V  Low level: 0.8 V • Output reference levels:  High level: 2.0 V  Low level: 0.8 V DUT output output pin Note: is set with the following pins, including the total capacitance of the measurement equipment etc: CK, RAS, CASxx, RDWR, CS0–CS3, AH, BREQ, BACK, DACK0, 30 pF:...
Page 849: A/D Converter Characteristics
26.4 A/D Converter Characteristics = 3.0 * Table 26.15 A/D Converter Characteristics (excluding A mask) (Conditions:V = 3.0 * = 3.0 * 3.6V, AV to 3.6V, AV ± 10%, AV to AV = 0V, T = –20 to +75°C) 16.7MHz Item Unit Resolution...
Page 851: Appendix A On-Chip Supporting Module Registers
Appendix A On-Chip Supporting Module Registers Addresses Table A.1 On-Chip I/O Register Addresses Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — DTMR CHNE DISEL NMIM —...
Page 852 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF81B0 SMR1 STOP CKS1 CKS0 H'FFFF81B1 BRR1 H'FFFF81B2 SCR1 MPIE TEIE CKE1 CKE0 H'FFFF81B3 TDR1...
Page 853 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF821A TGR3B H'FFFF821B H'FFFF821C TGR4A H'FFFF821D H'FFFF821E TGR4B H'FFFF821F H'FFFF8220 TCNTS H'FFFF8221 H'FFFF8222 TCBR H'FFFF8223...
Page 854 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF8268 TGR0A H'FFFF8269 H'FFFF826A TGR0B H'FFFF826B H'FFFF826C TGR0C H'FFFF826D H'FFFF826E TGR0D H'FFFF826F H'FFFF8270 —...
Page 855 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF82AC — — — — — — — — — H'FFFF8347 H'FFFF8348 IPRA INTC H'FFFF8349...
Page 856 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF838A — — — — — — — — — H'FFFF838B — —...
Page 857 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF83AC PDCRL PD15MD PD14MD PD13MD PD12MD PD11MD PD10MD PD9MD PD8MD H'FFFF83AD PD7MD PD6MD PD5MD...
Page 858 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF83D6 CMCOR0 H'FFFF83D7 H'FFFF83D8 CMCSR1 — — — — — — —...
Page 859 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF8406 ADDRD0 A/D(Mid- H'FFFF8407 — — — — — — speed) H'FFFF8408 ADDRA1 (A mask H'FFFF8409...
Page 860 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF8610 TCNT * H'FFFF8611 TCNT * H'FFFF8612 RSTCSR * WOVF RSTE RSTS —...
Page 861 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF8632 — — — — — — — — — H'FFFF86AF H'FFFF86B0 DMAOR —...
Page 862 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF86DC CHCR1 — — — — — — — — DMAC H'FFFF86DD —...
Page 863 Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Address Abbr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF8700 DTEA DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 H'FFFF8701 DTEB DTE7 DTE6 DTE5...
Page 864: Appendix B Block Diagrams
Appendix B Block Diagrams Internal data bus PAn/ PAnDR RXDm Q PAnMD Q PAnIOR SBYCR Standby Q HIZ RXDm n = 0, 3 m = 0, 1 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.1 PAn/RXDm Block Diagram...
Page 865 Internal data bus PAn/ PAnDR SCKm/ DREQm/ SCKmOUT IRQm Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ INTC IRQm DMAC DREQm SCKmIN n = 2, 5 m = 0, 1 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.2 PAn/SCKm/DREQm/IRQm Block Diagram...
Page 866 Internal data bus PA6/ TCLKA/ PAnDR CS2, PA7/ TCLKB/ CS2, CS3 Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ TCLKA, TCLKB n = 6, 7 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.3 PA6/TCLKA/CS2, PA7/TCLKB/CS3 (ZTAT, Mask) Block Diagram...
Page 867 On-chip flash memory Writer mode Q PA7DR Q PA7MD0 Q PA7MD1 Q PA7IOR SBYCR Standby Q HIZ TCLKB PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.4 PA7/TCLKB/CS3 Block Diagram (F-ZTAT Version)
Page 868 Internal data bus PA8/ TCLKC/ PAnDR IRQ2, PA9/ TCLKD/ IRQ3 Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ TCLKC, TLCKD INTC IRQ2, IRQ3 n = 8, 9 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.5 PAn/TCLKm/IRQx Block Diagram (ZTAT, Mask)
Page 869 On-chip flash memory OE, CE Writer mode Q PAnDR Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ TCLKC,D INTC IRQ2,IRQ3 n=8, 9 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.6 PAn/TCLKm/IRQx Block Diagram (F-ZTAT Version)
Page 870 Internal data bus PAnDR PAn/ TXDm TXDm Q PAnMD Q PAnIOR Standby STBCR Q HIZ n = 1, 4 m = 0, 1 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.7 PAn/TXDm Block Diagram...
Page 871 Internal data bus PA15DR PA15/CK Single mode MCU mode 2 MCU mode 1 MCU mode 0 Q PA15MD Q PA15IOR Standby STBCR Q HIZ PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.8 PA15/CK Block Diagram...
Page 872 Internal data bus PA18DR PA18/ DRAK0/ BREQ DRAK0 Q PA18MD0 Q PA18IMD1 Q PA18IOR SBYCR Standby Q HIZ BREQ PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.9 PA18/DRAK0/BREQ Block Diagram...
Page 873 Internal data bus PA19DR PA19/ DRAK1/ BACK DRAK1 BACK Bus right release Q PA19MD0 Q PA19MD1 Q PA19IOR SBYCR Standby Q HIZ PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.10 PA19/DRAQ1/BACK Block Diagram...
Page 874 Internal data bus PAnDR PAn/ CS0, CS1,WRL, WRH,RD Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Q PAnMD Q PAnIOR Standby SBYCR Q HIZ n = 10-14 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.11 PAn/XXX Block Diagram...
Page 875 Internal data bus PAnDR PAn/ AH, CASHL, XXXX CASHH,WRHL, WRHH Single mode Q PAnMD Bus right release Q PAnIOR Standby SBYCR Q HIZ n = 16,20-23 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.12 PAn/XXXX Block Diagram...
Page 876 Internal data bus PA17/ PAnDR WAIT Single mode Q PA17MD Bus right release Q PA17IOR Standby SBYCR Q HIZ WAIT request PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.13 PA17/WAIT Block Diagram...
Page 877 On-chip * EPROM Internal data bus PROM mode PB0DR PB0/ Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Q PB0MD Q PB0IOR Standby SBYCR Q HIZ PBR: Port B read signal PBW: Port B write signal RES: Reset signal Note: * Not available with the mask versions.
Page 878 On-chip flash memory Writer mode PB0DR Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Q PB0MD0 Q PB0IOR Standby SBYCR Q HIZ PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.15 PB0/A16 Block Diagram (F-ZTAT Version)
Page 879 Internal data bus PB1DR PB1/ Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Q PB1MD Q PB1IOR Standby SBYCR Q HIZ PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.16 PB1/A17 Block Diagram...
Page 880 Internal data bus PB6/ PB6DR IRQ4/ A18/ BACK BACK Q PB6MD0 Q PB6MD1 Q PB6IOR SBYCR Standby Q HIZ Bus right release INTC IRQ4 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.17 PB6/IRQ4/A18/BACK Block Diagram...
Page 881 On-chip * EPROM OE, PGM Internal data bus PROM mode PBn/ PBnDR IRQm/ POEm/ CASx CASL, CASH Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Q HIZ Bus right release POEm INTC IRQm n = 3, 4 m = 1, 2 PBR: Port B read signal PBW: Port B write signal RES: Reset signal...
Page 882 On-chip flash memory * Writer mode PBnDR CASL,CASH Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Q HIZ Bus right release POEm INTC IRQm n=3, 4 m=1, 2 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Note: * Only when n = 4.
Page 883 Internal data bus PBn/ PBnDR IRQm/ XXX/ A19–A21 Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Q HIZ Bus right BSC/AD release BREQ, WAIT, ADTRG INTC IRQm n = 7-9 m = 5-7 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.20 PBn/IRQm/XXX/YYY Block Diagram...
Page 884 Internal data bus PBn/ PBnDR IRQm/ XXX/ RAS, RDWR Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Q HIZ Bus right release POE0, POE3 INTC IRQm n = 2, 5 m = 0, 3 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.21 PBn/IRQm/XXXX/YYYY Block Diagram...
Page 885 On-chip * EPROM Internal data bus PROM mode PCnDR PCn/ Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Q PBnMD Q PBnIOR Standby SBYCR Q HIZ n = 0–15 PCR: Port C read signal PCW: Port C write signal RES: Reset signal Note: * Not available with the mask versions.
Page 886 On-chip flash memory Writer mode PCnDR Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Q PCnMD Q PCnIOR Standby SBYCR Q HIZ n=0–15 PCR: Port C read signal PCW: Port C write signal RES: Reset signal Figure B.23 PCn/An Block Diagram (F-ZTAT Version)
Page 887 On-chip * EPROM Internal data bus PROM mode PDnDR PDn/ Dout Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Q PDnMD SLEEP Q PDnIOR Standby SBYCR Q HIZ n = 0–7 PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data output timing signal...
Page 888 On-chip flash memory Writer mode PDnDR Dout Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release Sleep Q PDnMD0 Q PDnIOR Standby SBYCR Q HIZ n=0–15 PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data bus output timing signal Din: Data bus input timing signal...
Page 889 Internal data bus PDnDR PDn/ IRQm Dout Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby SBYCR Q HIZ INTC IRQm RES: Reset signal n = 16–23 m = 0–7 Dout: Data output timing signal PDR: Port D read signal Din: Data bus input timing signal...
Page 890 Internal data bus PDnDR PDn/ DREQm Dout Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby SBYCR Q HIZ DMAC DREQm RES: Reset signal n = 24,25 m = 0,1 Dout: Data output timing signal PDR: Port D read signal Din: Data bus input timing signal...
Page 891 Internal data bus PDnDR PDn/ DACKm Dout DACKm Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby SBYCR Q HIZ RES: Reset signal n = 26,27 m = 0,1 Dout: Data output timing signal PDR: Port D read signal Din: Data bus input timing signal PDW: Port D write signal...
Page 892 Internal data bus PDnDR PDn/ Dout Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby SBYCR Q HIZ RES: Reset signal n = 28–29 m = 2–3 Dout: Data output timing signal PDR: Port D read signal Din: Data bus input timing signal PDW: Port D write signal...
Page 893 Internal data bus PDnDR PDn/ IRQOUT Dout IRQOUT Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby SBYCR Q HIZ n = 30 RES: Reset signal PDR: Port D read signal Dout: Data output timing signal PDW: Port D write signal Din: Data bus input timing signal...
Page 894 Internal data bus PD31DR PD31/ D31/ ADTRG Dout Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP QPD31MD0 QPD31MD1 QPD31IOR Standby SBYCR Q HIZ ADTRG PDR: Port D read signal Dout: Data output timing signal PDW: Port D write signal Din: Data bus input timing signal RES: Reset signal...
Page 895 Internal data bus PDnDR PDn/ Dout Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP QPDnMD QPDnIOR Standby SBYCR Q HIZ n = 8–15 RES: Reset signal PDR: Port D read signal Dout: Data output timing signal PDW: Port D write signal Din: Data bus input timing signal Figure B.32 PDn/Dn Block Diagram...
Page 896 Internal data bus PE13DR PE13/ TIOC4B/ MRES TIOC4B QPE13MD0 QPE13MD1 QPE13IOR SBYCR Standby Q HIZ TIOC4B SYSC MRES PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.33 PE13/TIOC4B/MRES Block Diagram...
Page 897 Internal data bus PE14/ PE14DR TIOC4C/ DACK0/ TIOC4C DRAK0 QPE14MD0 QPE14MD1 QPE14IOR SBYCR Standby Q HIZ TIOC4C PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.34 PE14/TIOC4C/DACK0/AH Block Diagram...
Page 898 Internal data bus PE15/ PE15DR TIOC4D/ DACK1/ IRQOUT TIOC4D DRAK1 IRQOUT QPE15MD0 QPE15MD1 QPE15IOR SBYCR Standby Q HIZ TIOC4D PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.35 PEn/TIOC4D/DACK1/IRQOUT Block Diagram...
Page 899 Internal data bus PEnDR PEn/ TIOC1A, TIOC1B, TIOCxx TIOC2A, TIOC2B, TIOC3A, TIOC3B, TIOC3C, TIOC3D, TIOC4A QPEnMD QPEnIOR SBYCR Standby Q HIZ TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A, TIOC3B, TIOC3C, TIOC3D, TIOC4A n = 4-12 PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.36 PEn/TIOCXX Block Diagram...
Page 900 Internal data bus PEnDR PEn/ TIOCxx/ DRACm TIOC0B TIOC0D DRAKm QPEnMD0 QPEnMD1 QPEnIOR SBYCR Standby Q HIZ TIOC0B TIOC0D n = 1, 3 m = 0, 1 PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.37 PEn/TIOCXX/DRAKm Block Diagram...
Page 901 Internal data bus PEn/ PEnDR TIOCxx/ DREQm TIOC0A TIOC0C QPEnMD0 QPEnMD1 QPEnIOR SBYCR Standby Q HIZ TIOC0A TIOC0C DREQm n = 0, 2 m = 0, 1 PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.38 PEn/TIOCXX/DREQm Block Diagram...
Page 902 Internal data bus PFn/ SBYCR Standby Q HIZ n = 0–7 PFR: Port F read signal Figure B.39 PFn/ANn Block Diagram...
Page 903: Appendix C Pin States
Appendix C Pin States Table C.1 Pin Modes During Reset, Power-Down, and Bus Right Release Modes (144 Pin) Pin modes Pin Function Reset Power-Down Bus Right Standby in Bus Class Pin Name Power-OnManual Standby Sleep Release Right Release Clock System control MRES WDTOVF...
Page 904 Table C.1 Pin Modes During Reset, Power-Down, and Bus Right Release Modes (144 Pin) (cont) Pin modes Pin Function Reset Power-Down Bus Right Standby in Bus Class Pin Name Power-OnManual Standby Sleep Release Right Release TIOC0A–TIOC0D, TIOC1A–TIOC1D, TIOC2A–TIOC2D, TIOC3A, TIOC3C TIOC3B,TIOC3D, TIOC4A–TIOC4D TCLKA–TCLKD...
Page 905 Table C.2 Pin Modes During Reset, Power-Down, and Bus Right Release Modes (112 Pin, 120 Pin) Pin modes Pin Function Reset Power-Down Bus Right Standby in Bus Class Pin Name Power-On Manual Standby Sleep Release Right Release Clock System control MRES WDTOVF BREQ...
Page 906 Table C.2 Pin Modes During Reset, Power-Down, and Bus Right Release Modes (112 Pin, 120 Pin) (cont) Pin modes Pin Function Reset Power-Down Bus Right Standby in Bus Class Pin Name Power-On Manual Standby Sleep Release Right Release POE0–POE3 Port control SCK0–SCK1 TXD0–TCD1...
Page 907 Table C.3 Pin Settings for On-Chip Peripheral Modules On-Chip Peripheral Module 16-Bit Space On-Chip On-Chip Upper Lower Word/ Pin Name 8-Bit Space Byte Byte Longword CS0–CS3 RAS * CASHH * CASHL * CASLH * CASLL * RD/WR — WRHH — WRHL —...
Page 908 Table C.4 Pin Settings for Normal External Space 16-Bit Space Pin Name 8-Bit Space Upper Word Lower Word Word/Longword CS0–CS3 Valid Valid Valid Valid RAS * CASHH * CASHL * CASLH * CASLL * RD/WR WRHH WRHL WRLH WRLL A21–A0 Address Address Address...
Page 909 Table C.4 Pin Settings for Normal External Space (cont) 32-Bit Space Upper Lower Pin Name 2nd Byte 3rd Byte Word Word Longword CS0–CS3 Valid Valid Valid Valid Valid Valid Valid RAS * CASHH * CASHL * CASLH * CASLL * RD/WR WRHH WRHL...
Page 910 Table C.5 Pin Settings for Multiplex I/O Space 16-Bit Space Pin Name 8-Bit Space Upper Byte Lower Byte Word/Longword CS0–CS2 RAS * CASHH * CASHL * CASLH * CASLL * RD/WR Valid Valid Valid Valid WRHH WRHL A21–A0 Address Address Address Address D31–D24...
Page 911 Table C.6 Pin Settings for DRAM Space 16-Bit Space Pin Name 8-Bit Space Upper Word Lower Word Word/Longword CS0–CS3 RAS * Valid Valid Valid Valid CASHH * CASHL * CASLH * Valid Valid CASLL * Valid Valid Valid RD/WR WRHH WRHL A21–A0 Address...
Page 912 Table C.6 Pin Settings for DRAM Space (cont) 32-Bit Space Upper Lower Pin Name 2nd Byte 3rd Byte Word Word Longword CS0–CS3 RAS * Valid Valid Valid Valid Valid Valid Valid CASHH * Valid Valid Valid CASHL * Valid Valid Valid CASLH * Valid...
Page 913: Appendix D Notes When Converting The F-Ztat Application Software To The Mask-Rom Versions
Appendix D Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM of the mask-ROM version and F– ZTAT version differ as follows.
Page 914: Appendix E Product Code Lineup
Appendix E Product Code Lineup Table E.1 SH7040, SH7041, SH7042, SH7043, SH7044, and SH7045 Product Lineup Product Mask Order Model No. * Type Version Product Code Mark Code Package SH7040A Mask ROM A MASK HD6437040AF28 HD6437040A (***)F28 QFP2020-112 HD6437040A***F verion HD6437040AVF16 HD6437040A(***)VF16 QFP2020-112...
Page 915 Table E.1 SH7040, SH7041, SH7042, SH7043, SH7044, and SH7045 Product Lineup (cont) Product Mask Order Model No. * Type Version Product Code Mark Code Package SH7042A Z-TAT A MASK HD6477042AF28 HD6477042AF28 QFP2020-112 HD6477042AF28 version HD6477042AVF16 HD6477042AVF16 QFP2020-112 HD6477042AVF16 HD6477042AVX16 HD6477042AVX16 TQFP1414-120 HD6477042AVX16 QFP2020-112Cu *...
Page 916: Appendix F Package Dimensions
Appendix F Package Dimensions Package dimensions of the SH7040, SH7042, SH7044 (FP-112) are shown in figures F.1 and F.2. Package dimensions of the SH7040, SH7042 (TFP-120) are shown in figure F.3. Package dimensions of the SH7041, SH7043, SH7045 (FP-144) are shown in figures F.4 and F.5. Unit: mm 23.2 ±...
Page 917 This package (FP-112B) uses copper leads. Unit: mm 23.2 ± 0.2 0.32 ± 0.08 0.13 M 0.30 ± 0.06 1.23 0˚ – 8˚ 0.8 ± 0.2 0.10 Package Code FP-112B JEDEC — JEITA Conforms *Dimension including the plating thickness Base material dimension Mass (reference value) 2.4 g Figure F.2 Package Dimensions (FP-112B)
Page 918 Unit: mm 16.0 ± 0.2 *0.17 ± 0.05 0.07 0.15 ± 0.04 0˚ – 8˚ 0.5 ± 0.1 0.10 Package Code TFP-120 JEDEC — JEITA Conforms *Dimension including the plating thickness Base material dimension Mass (reference value) 0.5 g Figure F.3 Package Dimensions (TFP-120)
Page 919 22.0 ± 0.2 Unit: mm 0.22 ± 0.05 1.25 0.10 M 0.20 ± 0.04 0˚ – 8˚ 0.5 ± 0.1 0.10 Package Code FP-144J JEDEC — JEITA Conforms *Dimension including the plating thickness Base material dimension Mass (reference value) 2.4 g Figure F.4 Package Dimensions (FP-144J)
Page 920 This package (FP-144G) uses copper leads. 22.0 ± 0.2 Unit: mm 0.22 ± 0.05 1.25 0.10 M 0.20 ± 0.04 0˚ – 8˚ 0.5 ± 0.1 0.10 Package Code FP-144G JEDEC — JEITA Conforms *Dimension including the plating thickness Base material dimension Mass (reference value) 2.4 g Figure F.5 Package Dimensions (FP-144G)
Page 921 Publication Date: 1st Edition, February, 1997 Rev.6.00, May 26, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 1997, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan.
Page 922 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Colophon 0.0...
Page 923 SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Group Hardware Manual REJ09B0044-0600O...

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Renesas SuperH RISC Series Hardware Manual

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