Renesas SH-4A User Manual page 66

Table 1.4 Measurement Items
Classification Type
Disabled
CPU Cycle
performance
Instruction
Branch
Exception,
interruption
42
Measurement Item
Elapsed cycles
Cycles executed in
privileged mode
Cycles for asserting
the SR.BL bit
Number of effective
instructions issued
Number of 2
instruction executed
simultaneously
Number of
unconditional branch
Number of
exceptions accepted
Number of interrupts
accepted
Number of UBC
channel hit
Option Note
None Not measured.
AC Except for power-on period;
counted by the CPU clock.
PM The number of privileged-
mode cycles among the
number of elapsed cycles.
BL The number of cycles when
the SR.BL bit = 1 among the
number of elapsed cycles.
I The number of execution
instructions = number of valid
instructions issued + number
of cases of simultaneous
execution of two instructions.
The number of valid
instructions means the
number of completed
instructions.
2I The number of times that two
instructions are executed
simultaneously among the
valid instructions issued.
BT The number of unconditional
branches other than branches
occurring after an exception.
However, RTE is counted.
EA Interrupts are included.
INT NMI is included.
UBC Performs OR to count the
number of channel-hits in the
CPU.