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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
Count source
Measurement pulse
Reload register
counter
transfer timing
Timing at which counter
reaches "0000
"
16
TBiS bit
IR bit in the TBiIC
register
MR3 bit in theTBiMR
register
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
i = 0 to 2
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "00
from falling edge to falling edge of the measurement pulse).
Figure 12.2.3.2 Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
Timing at which counter
reaches "0000
"
16
TBiS bit
IR bit in the TBiIC
register
MR3 bit in the TBiMR
register
i = 0 to 2
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "10
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of
the measurement pulse).
Figure 12.2.3.3 Operation timing when measuring a pulse width
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
"H"
"L"
"1"
"0"
"1"
"0"
Set to "0" upon accepting an interrupt request or by writing in
program
"1"
"0"
"H"
"L"
counter
"1"
"0"
"1"
"0"
Set to "0" upon accepting an interrupt request or by
"1"
writing in program
"0"
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
page 114
f o
3
2
9
1
6
C
2 /
6
) T
Transfer
(indeterminate value)
(1)
Transfer
Transfer
Transfer
(indeterminate
(measured value)
(measured
value)
value)
(1)
(1)
Transfer
(measured value)
(1)
(2)
" (measure the interval
2
Transfer
(measured value)
(1)
(1)
(2)
" (measure the
2
12. Timer
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