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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Timer B2 Special Mode Register
b7
b6
b5
b4
b3
b2
0
0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer
B2 underflow).
3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD8
mode).
4. Related pins are U(P8
and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a low-
level ("L") signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time,
when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1,
pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used.
5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode).
6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02
bit to 1 (three-phase motor control timer function).
The effect of SD pin input is below.
1.Case of INV03 = 1(Three-phase motor control timer output enabled)
IVPCR1 bit
1
(Three-phase output
forcrible cutoff enable)
0
(Three-phase output
forcrible cutoff disable)
NOTES:
1. When "L" is applied to the SD pin, INV03 bit is changed to 0 at the same time.
2. The value of the port register and the port direction register becomes effective.
3. When SD function is not used, set to 0 (Input) in PD8
4. To leave the high-impedance state and restart the three-phase PWM signal output after the three-phase PWM signal
output forced cutoff, set the IVPCR1 bit to 0 after the SD pin input level becomes high ("H").
2.Case of INV03 = 0(Three-phase motor control timer output disabled)
IVPCR1 bit
1
(Three-phase output
forcrible cutoff enable)
0
(Three-phase output
forcrible cutoff disable)
NOTE:
1. The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is set to 1 (three-phase output
forcrible cutoff function enable) even when the INV03 bit is 0 (three-phase motor control timer output disalbe)
Figure 12.3.6. TB2SC Registers
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
(1)
b1
b0
Symbol
Address
TB2SC
039E
Bit Symbol
Bit Name
Timer B2 reload timing
PWCON
switch bit
Three-phase output port
IVPCR1
SD control bit 1
Timer B0 operation mode
TB0EN
select bit
Timer B1 operation mode
TB1EN
select bit
TB2SEL
Trigger select bit
Reserved bits
(b6-b5)
Nothing is assigned. If necessary, set to 0.
(b7)
When read, the content is 0.
), U(P8
), V(P7
), V(P7
0
1
2
(3)
SD pin inputs
H
(1)
L
H
(1)
L
SD pin inputs
H
L
H
L
page 123
f o
3
2
9
C
2 /
6
) T
After Reset
X0000000
16
2
0: Timer B2 underflow
(2)
1: Timer A output at odd-numbered
0: Three-phase output forcible cutoff by SD pin input
(high impedance) disabled
(3, 4, 7)
1: Three-phase output forcible cutoff by SD pin input
(high impedance) enabled
0: Other than A/D trigger mode
1: A/D trigger mode
0: Other than A/D trigger mode
1: A/D trigger mode
(6)
0: TB2 interrupt
1: Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Set to 0
), W(P7
), W(P7
). When a high-level ("H") signal is applied to the SD pin
3
4
5
Status of U/V/W pins
Three-phase PWM output
(4)
High impedance
Three-phase PWM output
(2)
Input/output port
and pullup to "H" in SD pin from outside.
5
Status of U/V/W pins
Peripheral input/output
or input/output port
High impedance
Peripheral input/output
or input/output port
Peripheral input/output
or input/output port
Function
(5)
(5)
bit to 0 (= input
5
Remarks
Three-phase output
forcrible cutoff
Remarks
Three-phase output
(1)
forcrible cutoff
12. Timer
RW
RW
RW
RW
RW
RW
RW
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