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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Interrupt request cause select register
b7
b6
b5
NOTE:
1. When setting this bit to "1" (= both edges), make sure the POL bit in the INT0IC to INT5IC register is set to
"0" (= falling edge).
Interrupt request cause select register 2
b7
b6
b5
NOTE:
1. Set this bit to "1" before you enable interrupt after resetting.
Figure 9.3.2. IFSR Register and IFSR2A Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
b4
b3
b2
b1
b0
Symbol
IFSR
Bit symbol
IFSR0
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
b4
b3
b2
b1
b0
1
Symbol
IFSR2A
Bit symbol
IFSR20
(b7-b1)
page 68
f o
3
2
9
6
C
2 /
6
) T
Address
035F
16
Bit name
INT0 interrupt polarity
switching bit
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
Interrupt request cause
select bit
Interrupt request cause
select bit
Address
035E
16
Bit name
Reserved bit
(1)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
After reset
00
16
Function
0 : One edge
1 : Both edges
(1)
0 : One edge
1 : Both edges
(1)
0 : One edge
1 : Both edges
(1)
0 : One edge
(1)
1 : Both edges
0 : One edge
1 : Both edges
(1)
0 : One edge
(1)
1 : Both edges
0 : Reserved
1 : INT4
0 : Reserved
1 : INT5
After reset
XXXXXXX0
2
Function
Must be set to "1".
9. Interrupt
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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