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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
RxD2
reverse circuit
STPS=0
SP
2SP
2SP
SP
SP
1SP
Figure 13.1.3. Block diagram of UART2 transmit/receive unit
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
No reverse
IOPOL=0
RxD data
IOPOL=1
Reverse
Clock
PAR
1SP
synchronous
disabled
type
PRYE=0
0
SP
PAR
1
STPS=1
PRYE=1
PAR
UART
enabled
SMD2 to SMD0
0
0
0
0
0
SMD2 to SMD0
UART
PAR
enabled
STPS=1
PRYE=1
1
PAR
STPS=0
0
PRYE=0
Clock
synchronous
PAR
type
disabled
0
page 135
f o
3
2
9
6
C
2 /
6
) T
Clock
synchronous type
UART
(7 bits)
UART(7 bits)
UART
(8 bits)
0
0
1
1
Clock
synchronous type
UART
UART
(9 bits)
(8 bits)
UART
(9 bits)
0
0
D
D
D
8
7
6
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D
D
D
7
6
8
UART
(8 bits)
UART
(9 bits)
UART
Clock
(9 bits)
synchronous type
1
1
0
0
UART(7 bits)
UART
(7 bits)
UART
(8 bits)
Clock
Error signal output
synchronous type
U2ERE
disable
=0
U2ERE
Error signal output
=1
enable
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the U2MR register
U2ERE : Bit in the U2C1 register
UARTi receive register
D
D
D
D
D
D
5
4
3
2
1
0
D
D
D
D
D
D
5
4
3
2
1
0
UARTi transmit register
No reverse
IOPOL
=0
TxD data
Error signal
reverse circuit
output circuit
IOPOL
Reverse
=1
SP: Stop bit
PAR: Parity bit
13. Serial I/O
UART2 receive
buffer register
Address 037E
16
Address 037F
16
UART2 transmit
buffer register
Address 037A
16
Address 037B
16
TxD2
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