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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
UART2 special mode register 3
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1. The DL2 to DL0 bits are used to generate a delay in SDA2 output by digital means during I
2
I
C bus mode, set these bits to "000
2. The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 Special Mode Register 4
b7 b6 b5 b4 b3 b2 b1 b0
NOTE:
1. Set to "0" when each condition is generated.
Figure 13.1.9. U2SMR3 register and U2SMR4 register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
Symbol
U2SMR3
Bit
Bit name
symbol
Nothing is assigned.
(b0)
When write, set "0". When read, its content is indeterminate.
CKPH
Clock phase set bit
Nothing is assigned.
(b2)
When write, set "0". When read, its content is indeterminate.
NODC
Clock output select bit
Nothing is assigned.
(b4)
When write, set "0". When read, its content is indeterminate.
DL0
SDA digital delay
setup bit
DL1
DL2
" (no delay).
2
Symbol
U2SMR4
Bit Symbol
STAREQ
Restart condition
RSTAREQ
generate bit
Stop condition
STPREQ
STSPSEL
SCL
ACK data bit
ACKD
ACK data output
ACKC
SCL
SCLHI
SCL
SWC9
page 141
f o
3
2
9
6
C
2 /
6
) T
Address
0375
16
0 : Without clock delay
1 : With clock delay
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
b7 b6 b5
(1, 2)
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Address
After Reset
0374
00
16
Bit Name
Start condition
0: Clear
(1)
generate bit
1: Start
0: Clear
(1)
1: Start
0: Clear
1: Start
0: Start and stop conditions not output
, SDA
output
2
2
1: Start and stop conditions output
0: ACK
1: NACK
0: Serial I/O data output
1: ACK data output
0: Disabled
output stop
2
1: Enabled
0: SCL
wait bit 3
2
1: SCL
After reset
000X0X0X
2
Function
2
C bus mode. In other than
16
Function
"L" hold disabled
2
"L" hold enabled
2
13. Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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