Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Table 4.3 SFR Information(3)
Address
0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
~ ~
01B0
16
01B1
16
01B2
16
Flash memory control register 4
01B3
16
01B4
16
01B5
Flash memory control register 1
16
01B6
16
01B7
Flash memory control register 0
16
01B8
16
01B9
16
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
~ ~
0250
16
0251
16
0252
16
0253
16
0254
16
0255
16
0256
16
0257
16
0258
16
0259
16
025A
Three phase protect control register
16
025B
16
025C
On-chip oscillator control register
16
025D
Pin assignment control register
16
025E
Peripheral clock select register
16
025F
16
~ ~
0330
16
0331
16
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
0339
16
033A
16
033B
16
033C
16
033D
16
033E
NMI digital debounce register
16
033F
Port1
digital debounce register
16
7
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. This register is included in the flash memory version.
X: Undefined
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
(1)
Register
page 22
f o
3
2
9
C
2 /
6
) T
(2)
(2)
(2)
Symbol
After reset
FMR4
01000000
FMR1
000XXX0X
FMR0
01
16
TPRC
00
16
ROCR
X0000101
PACR
00
16
PCLKR
00000011
NDDR
FF
16
P17DDR
FF
16
4. SFRs
~ ~
2
2
~ ~
2
2
~ ~
Advertisement
Table of Contents
