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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
RxDi
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
The above timing diagram applies to the case where the register bits are set as follows:
• Set the PRYE bit in the UiMR register to "0"(parity disabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)
i = 0 to 2
Figure 13.1.2.2. Receive Operation
13.1.2.1. Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 13.1.2.1.1 lists example of bit rate and settings.
Table 13.1.2.1.1 Example of Bit Rates and Settings
Bit Rate
Count Source
(bps)
of BRG
1200
2400
4800
9600
14400
19200
28800
31250
38400
51200
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
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"1"
"0"
Start bit
Sampled "L"
Reception triggered when transfer clock
"1"
is generated by falling edge of start bit
"0"
"H"
"L"
"1"
"0"
Cleared to "0" when interrupt request is accepted, or cleared to "0" by program
Peripheral Function Clock : 16MHz
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
f8
103(67h)
f8
51(33h)
f8
25(19h)
f1
103(67h)
f1
68(44h)
f1
51(33h)
f1
34(22h)
f1
31(1Fh)
f1
25(19h)
f1
19(13h)
page 154
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D
D
0
1
Receive data taken in
Transferred from UARTi receive
register to UiRB register
1202
2404
4808
9615
14493
19231
28571
31250
38462
50000
Stop bit
D
7
Read out from
UiRB register
Peripheral Function Clock : 20MHz
129(81h)
64(40h)
32(20h)
129(81h)
86(56h)
64(40h)
42(2Ah)
39(27h)
32(20h)
24(18h)
13. Serial I/O
1202
2404
4735
9615
14368
19231
29070
31250
37879
50000
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