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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
b7
b6
b5
b4
b3
0
NOTES:
1. During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
2. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are '00
3. Count down when input on TAi
direction bit for TAi
Figure 12.1.2.1. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
b2
b1
b0
Symbol
0 1
TA0MR to TA4MR
Bit symbol
TMOD0
Operation mode select bit
TMOD1
MR0
Pulse output function
select bit
MR1
Count polarity
select bit (2)
MR2
Up/down switching
cause select bit
MR3
Must be set to "0" in event counter mode
TCK0
Count operation type
select bit
TCK1
Can be "0" or "1" when not using two-phase pulse signal
processing
pin is low or count up when input on that pin is high. The port
OUT
pin must be set to "0" (= input mode).
OUT
page 99
f o
3
2
9
6
C
2 /
6
) T
Address
0396
to 039A
16
16
Bit name
b1 b0
0 1 : Event counter mode (1)
0 : Pulse is not output
(TA
iOUT
1 : Pulse is output
(TAi
OUT
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
0 : UDF register
1 : Input signal to TA
0 : Reload type
1 : Free-run type
After reset
00
16
Function
pin functions as I/O port)
pin functions as pulse output pin)
pin (3)
iOUT
' (TAi
pin input).
2
IN
12. Timer
RW
R
W
RW
RW
RW
RW
RW
RW
RW
RW
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