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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
1SP
STPS=0
SP
RxDi
STPS=1
2SP
2SP
SP
SP
1SP
Figure 13.1.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
Clock
PAR
synchronous
type
disabled
PRYE=0
0
SP
PAR
1
PRYE=1
UART
enabled
SMD2 to SMD0
0
0
0
0
0
0
SMD2 to SMD0
UART
PAR
STPS=1
enabled
PRYE=1
1
PAR
PRYE=0
0
STPS=0
Clock
synchronous
PAR
type
disabled
0
page 134
f o
3
2
9
6
C
2 /
6
) T
Clock
synchronous type
UART (7 bits)
UART (7 bits)
UART (8 bits)
0
0
1
1
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
D
D
D
D
8
7
6
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D
D
D
D
7
6
8
UART (8 bits)
UART (9 bits)
Clock synchronous
UART (9 bits)
type
1
1
0
0
UART (7 bits)
UART (8 bits)
UART (7 bits)
Clock synchronous
type
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the UiMR register
UARTi receive register
D
D
D
D
D
5
4
3
2
1
0
D
D
D
D
D
5
4
3
2
1
0
UARTi transmit register
SP: Stop bit
PAR: Parity bit
13. Serial I/O
UARTi receive
buffer register
Address 03A6
16
Address 03A7
16
Address 03AE
16
Address 03AF
16
UARTiÜ transmit
buffer register
Address 03A2
16
Address 03A3
16
Address 03AA
16
Address 03AB
16
TxDi
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